1
2
3
4
5
6
7#include <linux/err.h>
8#include <linux/of.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include "cpufreq-dt.h"
13
14
15
16
17
18static const struct of_device_id whitelist[] __initconst = {
19 { .compatible = "allwinner,sun4i-a10", },
20 { .compatible = "allwinner,sun5i-a10s", },
21 { .compatible = "allwinner,sun5i-a13", },
22 { .compatible = "allwinner,sun5i-r8", },
23 { .compatible = "allwinner,sun6i-a31", },
24 { .compatible = "allwinner,sun6i-a31s", },
25 { .compatible = "allwinner,sun7i-a20", },
26 { .compatible = "allwinner,sun8i-a23", },
27 { .compatible = "allwinner,sun8i-a83t", },
28 { .compatible = "allwinner,sun8i-h3", },
29
30 { .compatible = "apm,xgene-shadowcat", },
31
32 { .compatible = "arm,integrator-ap", },
33 { .compatible = "arm,integrator-cp", },
34
35 { .compatible = "hisilicon,hi3660", },
36
37 { .compatible = "fsl,imx27", },
38 { .compatible = "fsl,imx51", },
39 { .compatible = "fsl,imx53", },
40
41 { .compatible = "marvell,berlin", },
42 { .compatible = "marvell,pxa250", },
43 { .compatible = "marvell,pxa270", },
44
45 { .compatible = "samsung,exynos3250", },
46 { .compatible = "samsung,exynos4210", },
47 { .compatible = "samsung,exynos5250", },
48#ifndef CONFIG_BL_SWITCHER
49 { .compatible = "samsung,exynos5800", },
50#endif
51
52 { .compatible = "renesas,emev2", },
53 { .compatible = "renesas,r7s72100", },
54 { .compatible = "renesas,r8a73a4", },
55 { .compatible = "renesas,r8a7740", },
56 { .compatible = "renesas,r8a7742", },
57 { .compatible = "renesas,r8a7743", },
58 { .compatible = "renesas,r8a7744", },
59 { .compatible = "renesas,r8a7745", },
60 { .compatible = "renesas,r8a7778", },
61 { .compatible = "renesas,r8a7779", },
62 { .compatible = "renesas,r8a7790", },
63 { .compatible = "renesas,r8a7791", },
64 { .compatible = "renesas,r8a7792", },
65 { .compatible = "renesas,r8a7793", },
66 { .compatible = "renesas,r8a7794", },
67 { .compatible = "renesas,sh73a0", },
68
69 { .compatible = "rockchip,rk2928", },
70 { .compatible = "rockchip,rk3036", },
71 { .compatible = "rockchip,rk3066a", },
72 { .compatible = "rockchip,rk3066b", },
73 { .compatible = "rockchip,rk3188", },
74 { .compatible = "rockchip,rk3228", },
75 { .compatible = "rockchip,rk3288", },
76 { .compatible = "rockchip,rk3328", },
77 { .compatible = "rockchip,rk3366", },
78 { .compatible = "rockchip,rk3368", },
79 { .compatible = "rockchip,rk3399",
80 .data = &(struct cpufreq_dt_platform_data)
81 { .have_governor_per_policy = true, },
82 },
83
84 { .compatible = "st-ericsson,u8500", },
85 { .compatible = "st-ericsson,u8540", },
86 { .compatible = "st-ericsson,u9500", },
87 { .compatible = "st-ericsson,u9540", },
88
89 { .compatible = "ti,omap2", },
90 { .compatible = "ti,omap4", },
91 { .compatible = "ti,omap5", },
92
93 { .compatible = "xlnx,zynq-7000", },
94 { .compatible = "xlnx,zynqmp", },
95
96 { }
97};
98
99
100
101
102
103static const struct of_device_id blacklist[] __initconst = {
104 { .compatible = "allwinner,sun50i-h6", },
105
106 { .compatible = "calxeda,highbank", },
107 { .compatible = "calxeda,ecx-2000", },
108
109 { .compatible = "fsl,imx7ulp", },
110 { .compatible = "fsl,imx7d", },
111 { .compatible = "fsl,imx8mq", },
112 { .compatible = "fsl,imx8mm", },
113 { .compatible = "fsl,imx8mn", },
114 { .compatible = "fsl,imx8mp", },
115
116 { .compatible = "marvell,armadaxp", },
117
118 { .compatible = "mediatek,mt2701", },
119 { .compatible = "mediatek,mt2712", },
120 { .compatible = "mediatek,mt7622", },
121 { .compatible = "mediatek,mt7623", },
122 { .compatible = "mediatek,mt817x", },
123 { .compatible = "mediatek,mt8173", },
124 { .compatible = "mediatek,mt8176", },
125 { .compatible = "mediatek,mt8183", },
126
127 { .compatible = "nvidia,tegra20", },
128 { .compatible = "nvidia,tegra30", },
129 { .compatible = "nvidia,tegra124", },
130 { .compatible = "nvidia,tegra210", },
131
132 { .compatible = "qcom,apq8096", },
133 { .compatible = "qcom,msm8996", },
134 { .compatible = "qcom,qcs404", },
135 { .compatible = "qcom,sc7180", },
136 { .compatible = "qcom,sdm845", },
137
138 { .compatible = "st,stih407", },
139 { .compatible = "st,stih410", },
140
141 { .compatible = "sigma,tango4", },
142
143 { .compatible = "ti,am33xx", },
144 { .compatible = "ti,am43", },
145 { .compatible = "ti,dra7", },
146 { .compatible = "ti,omap3", },
147
148 { .compatible = "qcom,ipq8064", },
149 { .compatible = "qcom,apq8064", },
150 { .compatible = "qcom,msm8974", },
151 { .compatible = "qcom,msm8960", },
152
153 { }
154};
155
156static bool __init cpu0_node_has_opp_v2_prop(void)
157{
158 struct device_node *np = of_cpu_device_node_get(0);
159 bool ret = false;
160
161 if (of_get_property(np, "operating-points-v2", NULL))
162 ret = true;
163
164 of_node_put(np);
165 return ret;
166}
167
168static int __init cpufreq_dt_platdev_init(void)
169{
170 struct device_node *np = of_find_node_by_path("/");
171 const struct of_device_id *match;
172 const void *data = NULL;
173
174 if (!np)
175 return -ENODEV;
176
177 match = of_match_node(whitelist, np);
178 if (match) {
179 data = match->data;
180 goto create_pdev;
181 }
182
183 if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
184 goto create_pdev;
185
186 of_node_put(np);
187 return -ENODEV;
188
189create_pdev:
190 of_node_put(np);
191 return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
192 -1, data,
193 sizeof(struct cpufreq_dt_platform_data)));
194}
195core_initcall(cpufreq_dt_platdev_init);
196
