1
2
3#include <adf_accel_devices.h>
4#include <adf_common_drv.h>
5#include <adf_pf2vf_msg.h>
6#include "adf_c62x_hw_data.h"
7
8
9static const u32 thrd_to_arb_map_8_me_sku[] = {
10 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
11 0x11222AAA, 0x12222AAA, 0x11222AAA, 0, 0
12};
13
14static const u32 thrd_to_arb_map_10_me_sku[] = {
15 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
16 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
17};
18
19static struct adf_hw_device_class c62x_class = {
20 .name = ADF_C62X_DEVICE_NAME,
21 .type = DEV_C62X,
22 .instances = 0
23};
24
25static u32 get_accel_mask(u32 fuse)
26{
27 return (~fuse) >> ADF_C62X_ACCELERATORS_REG_OFFSET &
28 ADF_C62X_ACCELERATORS_MASK;
29}
30
31static u32 get_ae_mask(u32 fuse)
32{
33 return (~fuse) & ADF_C62X_ACCELENGINES_MASK;
34}
35
36static u32 get_num_accels(struct adf_hw_device_data *self)
37{
38 u32 i, ctr = 0;
39
40 if (!self || !self->accel_mask)
41 return 0;
42
43 for (i = 0; i < ADF_C62X_MAX_ACCELERATORS; i++) {
44 if (self->accel_mask & (1 << i))
45 ctr++;
46 }
47 return ctr;
48}
49
50static u32 get_num_aes(struct adf_hw_device_data *self)
51{
52 u32 i, ctr = 0;
53
54 if (!self || !self->ae_mask)
55 return 0;
56
57 for (i = 0; i < ADF_C62X_MAX_ACCELENGINES; i++) {
58 if (self->ae_mask & (1 << i))
59 ctr++;
60 }
61 return ctr;
62}
63
64static u32 get_misc_bar_id(struct adf_hw_device_data *self)
65{
66 return ADF_C62X_PMISC_BAR;
67}
68
69static u32 get_etr_bar_id(struct adf_hw_device_data *self)
70{
71 return ADF_C62X_ETR_BAR;
72}
73
74static u32 get_sram_bar_id(struct adf_hw_device_data *self)
75{
76 return ADF_C62X_SRAM_BAR;
77}
78
79static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
80{
81 int aes = get_num_aes(self);
82
83 if (aes == 8)
84 return DEV_SKU_2;
85 else if (aes == 10)
86 return DEV_SKU_4;
87
88 return DEV_SKU_UNKNOWN;
89}
90
91static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
92 u32 const **arb_map_config)
93{
94 switch (accel_dev->accel_pci_dev.sku) {
95 case DEV_SKU_2:
96 *arb_map_config = thrd_to_arb_map_8_me_sku;
97 break;
98 case DEV_SKU_4:
99 *arb_map_config = thrd_to_arb_map_10_me_sku;
100 break;
101 default:
102 dev_err(&GET_DEV(accel_dev),
103 "The configuration doesn't match any SKU");
104 *arb_map_config = NULL;
105 }
106}
107
108static u32 get_pf2vf_offset(u32 i)
109{
110 return ADF_C62X_PF2VF_OFFSET(i);
111}
112
113static u32 get_vintmsk_offset(u32 i)
114{
115 return ADF_C62X_VINTMSK_OFFSET(i);
116}
117
118static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
119{
120 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
121 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR];
122 void __iomem *csr = misc_bar->virt_addr;
123 unsigned int val, i;
124
125
126 for (i = 0; i < hw_device->get_num_aes(hw_device); i++) {
127 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
128 val |= ADF_C62X_ENABLE_AE_ECC_ERR;
129 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val);
130 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i));
131 val |= ADF_C62X_ENABLE_AE_ECC_PARITY_CORR;
132 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val);
133 }
134
135
136 for (i = 0; i < hw_device->get_num_accels(hw_device); i++) {
137 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
138 val |= ADF_C62X_ERRSSMSH_EN;
139 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val);
140 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i));
141 val |= ADF_C62X_ERRSSMSH_EN;
142 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val);
143 }
144}
145
146static void adf_enable_ints(struct adf_accel_dev *accel_dev)
147{
148 void __iomem *addr;
149
150 addr = (&GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR])->virt_addr;
151
152
153 ADF_CSR_WR(addr, ADF_C62X_SMIAPF0_MASK_OFFSET,
154 ADF_C62X_SMIA0_MASK);
155 ADF_CSR_WR(addr, ADF_C62X_SMIAPF1_MASK_OFFSET,
156 ADF_C62X_SMIA1_MASK);
157}
158
159static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
160{
161 return 0;
162}
163
164void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
165{
166 hw_data->dev_class = &c62x_class;
167 hw_data->instance_id = c62x_class.instances++;
168 hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
169 hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;
170 hw_data->num_logical_accel = 1;
171 hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
172 hw_data->tx_rx_gap = ADF_C62X_RX_RINGS_OFFSET;
173 hw_data->tx_rings_mask = ADF_C62X_TX_RINGS_MASK;
174 hw_data->alloc_irq = adf_isr_resource_alloc;
175 hw_data->free_irq = adf_isr_resource_free;
176 hw_data->enable_error_correction = adf_enable_error_correction;
177 hw_data->get_accel_mask = get_accel_mask;
178 hw_data->get_ae_mask = get_ae_mask;
179 hw_data->get_num_accels = get_num_accels;
180 hw_data->get_num_aes = get_num_aes;
181 hw_data->get_sram_bar_id = get_sram_bar_id;
182 hw_data->get_etr_bar_id = get_etr_bar_id;
183 hw_data->get_misc_bar_id = get_misc_bar_id;
184 hw_data->get_pf2vf_offset = get_pf2vf_offset;
185 hw_data->get_vintmsk_offset = get_vintmsk_offset;
186 hw_data->get_sku = get_sku;
187 hw_data->fw_name = ADF_C62X_FW;
188 hw_data->fw_mmp_name = ADF_C62X_MMP;
189 hw_data->init_admin_comms = adf_init_admin_comms;
190 hw_data->exit_admin_comms = adf_exit_admin_comms;
191 hw_data->disable_iov = adf_disable_sriov;
192 hw_data->send_admin_init = adf_send_admin_init;
193 hw_data->init_arb = adf_init_arb;
194 hw_data->exit_arb = adf_exit_arb;
195 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
196 hw_data->enable_ints = adf_enable_ints;
197 hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
198 hw_data->reset_device = adf_reset_flr;
199 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
200}
201
202void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)
203{
204 hw_data->dev_class->instances--;
205}
206
