linux/drivers/gpio/gpio-ml-ioh.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   4 */
   5#include <linux/module.h>
   6#include <linux/kernel.h>
   7#include <linux/slab.h>
   8#include <linux/pci.h>
   9#include <linux/gpio/driver.h>
  10#include <linux/interrupt.h>
  11#include <linux/irq.h>
  12
  13#define IOH_EDGE_FALLING        0
  14#define IOH_EDGE_RISING         BIT(0)
  15#define IOH_LEVEL_L             BIT(1)
  16#define IOH_LEVEL_H             (BIT(0) | BIT(1))
  17#define IOH_EDGE_BOTH           BIT(2)
  18#define IOH_IM_MASK             (BIT(0) | BIT(1) | BIT(2))
  19
  20#define IOH_IRQ_BASE            0
  21
  22struct ioh_reg_comn {
  23        u32     ien;
  24        u32     istatus;
  25        u32     idisp;
  26        u32     iclr;
  27        u32     imask;
  28        u32     imaskclr;
  29        u32     po;
  30        u32     pi;
  31        u32     pm;
  32        u32     im_0;
  33        u32     im_1;
  34        u32     reserved;
  35};
  36
  37struct ioh_regs {
  38        struct ioh_reg_comn regs[8];
  39        u32 reserve1[16];
  40        u32 ioh_sel_reg[4];
  41        u32 reserve2[11];
  42        u32 srst;
  43};
  44
  45/**
  46 * struct ioh_gpio_reg_data - The register store data.
  47 * @ien_reg:    To store contents of interrupt enable register.
  48 * @imask_reg:  To store contents of interrupt mask regist
  49 * @po_reg:     To store contents of PO register.
  50 * @pm_reg:     To store contents of PM register.
  51 * @im0_reg:    To store contents of interrupt mode regist0
  52 * @im1_reg:    To store contents of interrupt mode regist1
  53 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
  54 */
  55struct ioh_gpio_reg_data {
  56        u32 ien_reg;
  57        u32 imask_reg;
  58        u32 po_reg;
  59        u32 pm_reg;
  60        u32 im0_reg;
  61        u32 im1_reg;
  62        u32 use_sel_reg;
  63};
  64
  65/**
  66 * struct ioh_gpio - GPIO private data structure.
  67 * @base:                       PCI base address of Memory mapped I/O register.
  68 * @reg:                        Memory mapped IOH GPIO register list.
  69 * @dev:                        Pointer to device structure.
  70 * @gpio:                       Data for GPIO infrastructure.
  71 * @ioh_gpio_reg:               Memory mapped Register data is saved here
  72 *                              when suspend.
  73 * @gpio_use_sel:               Save GPIO_USE_SEL1~4 register for PM
  74 * @ch:                         Indicate GPIO channel
  75 * @irq_base:           Save base of IRQ number for interrupt
  76 * @spinlock:           Used for register access protection
  77 */
  78struct ioh_gpio {
  79        void __iomem *base;
  80        struct ioh_regs __iomem *reg;
  81        struct device *dev;
  82        struct gpio_chip gpio;
  83        struct ioh_gpio_reg_data ioh_gpio_reg;
  84        u32 gpio_use_sel;
  85        int ch;
  86        int irq_base;
  87        spinlock_t spinlock;
  88};
  89
  90static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  91
  92static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  93{
  94        u32 reg_val;
  95        struct ioh_gpio *chip = gpiochip_get_data(gpio);
  96        unsigned long flags;
  97
  98        spin_lock_irqsave(&chip->spinlock, flags);
  99        reg_val = ioread32(&chip->reg->regs[chip->ch].po);
 100        if (val)
 101                reg_val |= (1 << nr);
 102        else
 103                reg_val &= ~(1 << nr);
 104
 105        iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
 106        spin_unlock_irqrestore(&chip->spinlock, flags);
 107}
 108
 109static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
 110{
 111        struct ioh_gpio *chip = gpiochip_get_data(gpio);
 112
 113        return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
 114}
 115
 116static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 117                                     int val)
 118{
 119        struct ioh_gpio *chip = gpiochip_get_data(gpio);
 120        u32 pm;
 121        u32 reg_val;
 122        unsigned long flags;
 123
 124        spin_lock_irqsave(&chip->spinlock, flags);
 125        pm = ioread32(&chip->reg->regs[chip->ch].pm) &
 126                                        ((1 << num_ports[chip->ch]) - 1);
 127        pm |= (1 << nr);
 128        iowrite32(pm, &chip->reg->regs[chip->ch].pm);
 129
 130        reg_val = ioread32(&chip->reg->regs[chip->ch].po);
 131        if (val)
 132                reg_val |= (1 << nr);
 133        else
 134                reg_val &= ~(1 << nr);
 135        iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
 136
 137        spin_unlock_irqrestore(&chip->spinlock, flags);
 138
 139        return 0;
 140}
 141
 142static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
 143{
 144        struct ioh_gpio *chip = gpiochip_get_data(gpio);
 145        u32 pm;
 146        unsigned long flags;
 147
 148        spin_lock_irqsave(&chip->spinlock, flags);
 149        pm = ioread32(&chip->reg->regs[chip->ch].pm) &
 150                                ((1 << num_ports[chip->ch]) - 1);
 151        pm &= ~(1 << nr);
 152        iowrite32(pm, &chip->reg->regs[chip->ch].pm);
 153        spin_unlock_irqrestore(&chip->spinlock, flags);
 154
 155        return 0;
 156}
 157
 158#ifdef CONFIG_PM
 159/*
 160 * Save register configuration and disable interrupts.
 161 */
 162static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
 163{
 164        int i;
 165
 166        for (i = 0; i < 8; i ++, chip++) {
 167                chip->ioh_gpio_reg.po_reg =
 168                                        ioread32(&chip->reg->regs[chip->ch].po);
 169                chip->ioh_gpio_reg.pm_reg =
 170                                        ioread32(&chip->reg->regs[chip->ch].pm);
 171                chip->ioh_gpio_reg.ien_reg =
 172                                       ioread32(&chip->reg->regs[chip->ch].ien);
 173                chip->ioh_gpio_reg.imask_reg =
 174                                     ioread32(&chip->reg->regs[chip->ch].imask);
 175                chip->ioh_gpio_reg.im0_reg =
 176                                      ioread32(&chip->reg->regs[chip->ch].im_0);
 177                chip->ioh_gpio_reg.im1_reg =
 178                                      ioread32(&chip->reg->regs[chip->ch].im_1);
 179                if (i < 4)
 180                        chip->ioh_gpio_reg.use_sel_reg =
 181                                           ioread32(&chip->reg->ioh_sel_reg[i]);
 182        }
 183}
 184
 185/*
 186 * This function restores the register configuration of the GPIO device.
 187 */
 188static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
 189{
 190        int i;
 191
 192        for (i = 0; i < 8; i ++, chip++) {
 193                iowrite32(chip->ioh_gpio_reg.po_reg,
 194                          &chip->reg->regs[chip->ch].po);
 195                iowrite32(chip->ioh_gpio_reg.pm_reg,
 196                          &chip->reg->regs[chip->ch].pm);
 197                iowrite32(chip->ioh_gpio_reg.ien_reg,
 198                          &chip->reg->regs[chip->ch].ien);
 199                iowrite32(chip->ioh_gpio_reg.imask_reg,
 200                          &chip->reg->regs[chip->ch].imask);
 201                iowrite32(chip->ioh_gpio_reg.im0_reg,
 202                          &chip->reg->regs[chip->ch].im_0);
 203                iowrite32(chip->ioh_gpio_reg.im1_reg,
 204                          &chip->reg->regs[chip->ch].im_1);
 205                if (i < 4)
 206                        iowrite32(chip->ioh_gpio_reg.use_sel_reg,
 207                                  &chip->reg->ioh_sel_reg[i]);
 208        }
 209}
 210#endif
 211
 212static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
 213{
 214        struct ioh_gpio *chip = gpiochip_get_data(gpio);
 215        return chip->irq_base + offset;
 216}
 217
 218static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
 219{
 220        struct gpio_chip *gpio = &chip->gpio;
 221
 222        gpio->label = dev_name(chip->dev);
 223        gpio->owner = THIS_MODULE;
 224        gpio->direction_input = ioh_gpio_direction_input;
 225        gpio->get = ioh_gpio_get;
 226        gpio->direction_output = ioh_gpio_direction_output;
 227        gpio->set = ioh_gpio_set;
 228        gpio->dbg_show = NULL;
 229        gpio->base = -1;
 230        gpio->ngpio = num_port;
 231        gpio->can_sleep = false;
 232        gpio->to_irq = ioh_gpio_to_irq;
 233}
 234
 235static int ioh_irq_type(struct irq_data *d, unsigned int type)
 236{
 237        u32 im;
 238        void __iomem *im_reg;
 239        u32 ien;
 240        u32 im_pos;
 241        int ch;
 242        unsigned long flags;
 243        u32 val;
 244        int irq = d->irq;
 245        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 246        struct ioh_gpio *chip = gc->private;
 247
 248        ch = irq - chip->irq_base;
 249        if (irq <= chip->irq_base + 7) {
 250                im_reg = &chip->reg->regs[chip->ch].im_0;
 251                im_pos = ch;
 252        } else {
 253                im_reg = &chip->reg->regs[chip->ch].im_1;
 254                im_pos = ch - 8;
 255        }
 256        dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
 257                __func__, irq, type, ch, im_pos, type);
 258
 259        spin_lock_irqsave(&chip->spinlock, flags);
 260
 261        switch (type) {
 262        case IRQ_TYPE_EDGE_RISING:
 263                val = IOH_EDGE_RISING;
 264                break;
 265        case IRQ_TYPE_EDGE_FALLING:
 266                val = IOH_EDGE_FALLING;
 267                break;
 268        case IRQ_TYPE_EDGE_BOTH:
 269                val = IOH_EDGE_BOTH;
 270                break;
 271        case IRQ_TYPE_LEVEL_HIGH:
 272                val = IOH_LEVEL_H;
 273                break;
 274        case IRQ_TYPE_LEVEL_LOW:
 275                val = IOH_LEVEL_L;
 276                break;
 277        case IRQ_TYPE_PROBE:
 278                goto end;
 279        default:
 280                dev_warn(chip->dev, "%s: unknown type(%dd)",
 281                        __func__, type);
 282                goto end;
 283        }
 284
 285        /* Set interrupt mode */
 286        im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
 287        iowrite32(im | (val << (im_pos * 4)), im_reg);
 288
 289        /* iclr */
 290        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
 291
 292        /* IMASKCLR */
 293        iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
 294
 295        /* Enable interrupt */
 296        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 297        iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
 298end:
 299        spin_unlock_irqrestore(&chip->spinlock, flags);
 300
 301        return 0;
 302}
 303
 304static void ioh_irq_unmask(struct irq_data *d)
 305{
 306        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 307        struct ioh_gpio *chip = gc->private;
 308
 309        iowrite32(1 << (d->irq - chip->irq_base),
 310                  &chip->reg->regs[chip->ch].imaskclr);
 311}
 312
 313static void ioh_irq_mask(struct irq_data *d)
 314{
 315        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 316        struct ioh_gpio *chip = gc->private;
 317
 318        iowrite32(1 << (d->irq - chip->irq_base),
 319                  &chip->reg->regs[chip->ch].imask);
 320}
 321
 322static void ioh_irq_disable(struct irq_data *d)
 323{
 324        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 325        struct ioh_gpio *chip = gc->private;
 326        unsigned long flags;
 327        u32 ien;
 328
 329        spin_lock_irqsave(&chip->spinlock, flags);
 330        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 331        ien &= ~(1 << (d->irq - chip->irq_base));
 332        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
 333        spin_unlock_irqrestore(&chip->spinlock, flags);
 334}
 335
 336static void ioh_irq_enable(struct irq_data *d)
 337{
 338        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 339        struct ioh_gpio *chip = gc->private;
 340        unsigned long flags;
 341        u32 ien;
 342
 343        spin_lock_irqsave(&chip->spinlock, flags);
 344        ien = ioread32(&chip->reg->regs[chip->ch].ien);
 345        ien |= 1 << (d->irq - chip->irq_base);
 346        iowrite32(ien, &chip->reg->regs[chip->ch].ien);
 347        spin_unlock_irqrestore(&chip->spinlock, flags);
 348}
 349
 350static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
 351{
 352        struct ioh_gpio *chip = dev_id;
 353        u32 reg_val;
 354        int i, j;
 355        int ret = IRQ_NONE;
 356
 357        for (i = 0; i < 8; i++, chip++) {
 358                reg_val = ioread32(&chip->reg->regs[i].istatus);
 359                for (j = 0; j < num_ports[i]; j++) {
 360                        if (reg_val & BIT(j)) {
 361                                dev_dbg(chip->dev,
 362                                        "%s:[%d]:irq=%d status=0x%x\n",
 363                                        __func__, j, irq, reg_val);
 364                                iowrite32(BIT(j),
 365                                          &chip->reg->regs[chip->ch].iclr);
 366                                generic_handle_irq(chip->irq_base + j);
 367                                ret = IRQ_HANDLED;
 368                        }
 369                }
 370        }
 371        return ret;
 372}
 373
 374static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
 375                                       unsigned int irq_start,
 376                                       unsigned int num)
 377{
 378        struct irq_chip_generic *gc;
 379        struct irq_chip_type *ct;
 380        int rv;
 381
 382        gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
 383                                         chip->base, handle_simple_irq);
 384        if (!gc)
 385                return -ENOMEM;
 386
 387        gc->private = chip;
 388        ct = gc->chip_types;
 389
 390        ct->chip.irq_mask = ioh_irq_mask;
 391        ct->chip.irq_unmask = ioh_irq_unmask;
 392        ct->chip.irq_set_type = ioh_irq_type;
 393        ct->chip.irq_disable = ioh_irq_disable;
 394        ct->chip.irq_enable = ioh_irq_enable;
 395
 396        rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
 397                                         IRQ_GC_INIT_MASK_CACHE,
 398                                         IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 399
 400        return rv;
 401}
 402
 403static int ioh_gpio_probe(struct pci_dev *pdev,
 404                                    const struct pci_device_id *id)
 405{
 406        int ret;
 407        int i, j;
 408        struct ioh_gpio *chip;
 409        void __iomem *base;
 410        void *chip_save;
 411        int irq_base;
 412
 413        ret = pci_enable_device(pdev);
 414        if (ret) {
 415                dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
 416                goto err_pci_enable;
 417        }
 418
 419        ret = pci_request_regions(pdev, KBUILD_MODNAME);
 420        if (ret) {
 421                dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
 422                goto err_request_regions;
 423        }
 424
 425        base = pci_iomap(pdev, 1, 0);
 426        if (!base) {
 427                dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
 428                ret = -ENOMEM;
 429                goto err_iomap;
 430        }
 431
 432        chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
 433        if (chip_save == NULL) {
 434                ret = -ENOMEM;
 435                goto err_kzalloc;
 436        }
 437
 438        chip = chip_save;
 439        for (i = 0; i < 8; i++, chip++) {
 440                chip->dev = &pdev->dev;
 441                chip->base = base;
 442                chip->reg = chip->base;
 443                chip->ch = i;
 444                spin_lock_init(&chip->spinlock);
 445                ioh_gpio_setup(chip, num_ports[i]);
 446                ret = gpiochip_add_data(&chip->gpio, chip);
 447                if (ret) {
 448                        dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
 449                        goto err_gpiochip_add;
 450                }
 451        }
 452
 453        chip = chip_save;
 454        for (j = 0; j < 8; j++, chip++) {
 455                irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
 456                                                num_ports[j], NUMA_NO_NODE);
 457                if (irq_base < 0) {
 458                        dev_warn(&pdev->dev,
 459                                "ml_ioh_gpio: Failed to get IRQ base num\n");
 460                        ret = irq_base;
 461                        goto err_gpiochip_add;
 462                }
 463                chip->irq_base = irq_base;
 464
 465                ret = ioh_gpio_alloc_generic_chip(chip,
 466                                                  irq_base, num_ports[j]);
 467                if (ret)
 468                        goto err_gpiochip_add;
 469        }
 470
 471        chip = chip_save;
 472        ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
 473                               IRQF_SHARED, KBUILD_MODNAME, chip);
 474        if (ret != 0) {
 475                dev_err(&pdev->dev,
 476                        "%s request_irq failed\n", __func__);
 477                goto err_gpiochip_add;
 478        }
 479
 480        pci_set_drvdata(pdev, chip);
 481
 482        return 0;
 483
 484err_gpiochip_add:
 485        chip = chip_save;
 486        while (--i >= 0) {
 487                gpiochip_remove(&chip->gpio);
 488                chip++;
 489        }
 490        kfree(chip_save);
 491
 492err_kzalloc:
 493        pci_iounmap(pdev, base);
 494
 495err_iomap:
 496        pci_release_regions(pdev);
 497
 498err_request_regions:
 499        pci_disable_device(pdev);
 500
 501err_pci_enable:
 502
 503        dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
 504        return ret;
 505}
 506
 507static void ioh_gpio_remove(struct pci_dev *pdev)
 508{
 509        int i;
 510        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 511        void *chip_save;
 512
 513        chip_save = chip;
 514
 515        for (i = 0; i < 8; i++, chip++)
 516                gpiochip_remove(&chip->gpio);
 517
 518        chip = chip_save;
 519        pci_iounmap(pdev, chip->base);
 520        pci_release_regions(pdev);
 521        pci_disable_device(pdev);
 522        kfree(chip);
 523}
 524
 525#ifdef CONFIG_PM
 526static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
 527{
 528        s32 ret;
 529        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 530        unsigned long flags;
 531
 532        spin_lock_irqsave(&chip->spinlock, flags);
 533        ioh_gpio_save_reg_conf(chip);
 534        spin_unlock_irqrestore(&chip->spinlock, flags);
 535
 536        ret = pci_save_state(pdev);
 537        if (ret) {
 538                dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
 539                return ret;
 540        }
 541        pci_disable_device(pdev);
 542        pci_set_power_state(pdev, PCI_D0);
 543        ret = pci_enable_wake(pdev, PCI_D0, 1);
 544        if (ret)
 545                dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
 546
 547        return 0;
 548}
 549
 550static int ioh_gpio_resume(struct pci_dev *pdev)
 551{
 552        s32 ret;
 553        struct ioh_gpio *chip = pci_get_drvdata(pdev);
 554        unsigned long flags;
 555
 556        ret = pci_enable_wake(pdev, PCI_D0, 0);
 557
 558        pci_set_power_state(pdev, PCI_D0);
 559        ret = pci_enable_device(pdev);
 560        if (ret) {
 561                dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
 562                return ret;
 563        }
 564        pci_restore_state(pdev);
 565
 566        spin_lock_irqsave(&chip->spinlock, flags);
 567        iowrite32(0x01, &chip->reg->srst);
 568        iowrite32(0x00, &chip->reg->srst);
 569        ioh_gpio_restore_reg_conf(chip);
 570        spin_unlock_irqrestore(&chip->spinlock, flags);
 571
 572        return 0;
 573}
 574#else
 575#define ioh_gpio_suspend NULL
 576#define ioh_gpio_resume NULL
 577#endif
 578
 579static const struct pci_device_id ioh_gpio_pcidev_id[] = {
 580        { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
 581        { 0, }
 582};
 583MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
 584
 585static struct pci_driver ioh_gpio_driver = {
 586        .name = "ml_ioh_gpio",
 587        .id_table = ioh_gpio_pcidev_id,
 588        .probe = ioh_gpio_probe,
 589        .remove = ioh_gpio_remove,
 590        .suspend = ioh_gpio_suspend,
 591        .resume = ioh_gpio_resume
 592};
 593
 594module_pci_driver(ioh_gpio_driver);
 595
 596MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
 597MODULE_LICENSE("GPL");
 598