linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
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   1/* Copyright 2016 Advanced Micro Devices, Inc.
   2 *
   3 * Permission is hereby granted, free of charge, to any person obtaining a
   4 * copy of this software and associated documentation files (the "Software"),
   5 * to deal in the Software without restriction, including without limitation
   6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7 * and/or sell copies of the Software, and to permit persons to whom the
   8 * Software is furnished to do so, subject to the following conditions:
   9 *
  10 * The above copyright notice and this permission notice shall be included in
  11 * all copies or substantial portions of the Software.
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  19 * OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * Authors: AMD
  22 *
  23 */
  24
  25#ifndef __DAL_DPP_DCN10_H__
  26#define __DAL_DPP_DCN10_H__
  27
  28#include "dpp.h"
  29
  30#define TO_DCN10_DPP(dpp)\
  31        container_of(dpp, struct dcn10_dpp, base)
  32
  33/* TODO: Use correct number of taps. Using polaris values for now */
  34#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
  35#define LB_BITS_PER_ENTRY 144
  36
  37#define TF_SF(reg_name, field_name, post_fix)\
  38        .field_name = reg_name ## __ ## field_name ## post_fix
  39
  40//Used to resolve corner case
  41#define TF2_SF(reg_name, field_name, post_fix)\
  42        .field_name = reg_name ## _ ## field_name ## post_fix
  43
  44#define TF_REG_LIST_DCN(id) \
  45        SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
  46        SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
  47        SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
  48        SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
  49        SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
  50        SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
  51        SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
  52        SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
  53        SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
  54        SRI(OTG_H_BLANK, DSCL, id), \
  55        SRI(OTG_V_BLANK, DSCL, id), \
  56        SRI(SCL_MODE, DSCL, id), \
  57        SRI(LB_DATA_FORMAT, DSCL, id), \
  58        SRI(LB_MEMORY_CTRL, DSCL, id), \
  59        SRI(DSCL_AUTOCAL, DSCL, id), \
  60        SRI(SCL_BLACK_OFFSET, DSCL, id), \
  61        SRI(SCL_TAP_CONTROL, DSCL, id), \
  62        SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
  63        SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
  64        SRI(DSCL_2TAP_CONTROL, DSCL, id), \
  65        SRI(MPC_SIZE, DSCL, id), \
  66        SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
  67        SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
  68        SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
  69        SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
  70        SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
  71        SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
  72        SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
  73        SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
  74        SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
  75        SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
  76        SRI(RECOUT_START, DSCL, id), \
  77        SRI(RECOUT_SIZE, DSCL, id), \
  78        SRI(CM_ICSC_CONTROL, CM, id), \
  79        SRI(CM_ICSC_C11_C12, CM, id), \
  80        SRI(CM_ICSC_C33_C34, CM, id), \
  81        SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
  82        SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
  83        SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
  84        SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
  85        SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
  86        SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
  87        SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
  88        SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
  89        SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
  90        SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
  91        SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
  92        SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
  93        SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
  94        SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
  95        SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
  96        SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
  97        SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
  98        SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
  99        SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
 100        SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
 101        SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
 102        SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
 103        SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
 104        SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
 105        SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
 106        SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
 107        SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
 108        SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
 109        SRI(CM_MEM_PWR_CTRL, CM, id), \
 110        SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
 111        SRI(CM_DGAM_LUT_INDEX, CM, id), \
 112        SRI(CM_DGAM_LUT_DATA, CM, id), \
 113        SRI(CM_CONTROL, CM, id), \
 114        SRI(CM_DGAM_CONTROL, CM, id), \
 115        SRI(CM_TEST_DEBUG_INDEX, CM, id), \
 116        SRI(CM_TEST_DEBUG_DATA, CM, id), \
 117        SRI(FORMAT_CONTROL, CNVC_CFG, id), \
 118        SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
 119        SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
 120        SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
 121        SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
 122        SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
 123        SRI(DPP_CONTROL, DPP_TOP, id), \
 124        SRI(CM_HDR_MULT_COEF, CM, id)
 125
 126
 127
 128#define TF_REG_LIST_DCN10(id) \
 129        TF_REG_LIST_DCN(id), \
 130        SRI(CM_COMA_C11_C12, CM, id),\
 131        SRI(CM_COMA_C33_C34, CM, id),\
 132        SRI(CM_COMB_C11_C12, CM, id),\
 133        SRI(CM_COMB_C33_C34, CM, id),\
 134        SRI(CM_OCSC_CONTROL, CM, id), \
 135        SRI(CM_OCSC_C11_C12, CM, id), \
 136        SRI(CM_OCSC_C33_C34, CM, id), \
 137        SRI(CM_BNS_VALUES_R, CM, id), \
 138        SRI(CM_BNS_VALUES_G, CM, id), \
 139        SRI(CM_BNS_VALUES_B, CM, id), \
 140        SRI(CM_MEM_PWR_CTRL, CM, id), \
 141        SRI(CM_RGAM_LUT_DATA, CM, id), \
 142        SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
 143        SRI(CM_RGAM_LUT_INDEX, CM, id), \
 144        SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
 145        SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
 146        SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
 147        SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
 148        SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
 149        SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
 150        SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
 151        SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
 152        SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
 153        SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
 154        SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
 155        SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
 156        SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
 157        SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
 158        SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
 159        SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
 160        SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
 161        SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
 162        SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
 163        SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
 164        SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
 165        SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
 166        SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
 167        SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
 168        SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
 169        SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
 170        SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
 171        SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
 172        SRI(CM_RGAM_CONTROL, CM, id), \
 173        SRI(CM_IGAM_CONTROL, CM, id), \
 174        SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
 175        SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
 176        SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
 177        SRI(CURSOR_CONTROL, CURSOR, id), \
 178        SRI(CM_CMOUT_CONTROL, CM, id)
 179
 180
 181#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
 182        TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
 183        TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
 184        TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
 185        TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
 186        TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
 187        TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
 188        TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
 189        TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
 190        TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
 191        TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
 192        TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
 193        TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
 194        TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
 195        TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
 196        TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
 197        TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
 198        TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
 199        TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
 200        TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
 201        TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
 202        TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
 203        TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
 204        TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
 205        TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
 206        TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
 207        TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
 208        TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
 209        TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
 210        TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
 211        TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
 212        TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
 213        TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
 214        TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
 215        TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
 216        TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
 217        TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
 218        TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
 219        TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
 220        TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
 221        TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
 222        TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
 223        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
 224        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
 225        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
 226        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
 227        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
 228        TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
 229        TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
 230        TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
 231        TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
 232        TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
 233        TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
 234        TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
 235        TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
 236        TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
 237        TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
 238        TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
 239        TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
 240        TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
 241        TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
 242        TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
 243        TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
 244        TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
 245        TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
 246        TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
 247        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
 248        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
 249        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
 250        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
 251        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
 252        TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
 253        TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
 254        TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
 255        TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
 256        TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
 257        TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
 258        TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
 259        TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
 260        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
 261        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
 262        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
 263        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
 264        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
 265        TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
 266        TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
 267        TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
 268        TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
 269        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
 270        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
 271        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
 272        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
 273        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
 274        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
 275        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
 276        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
 277        TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
 278        TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
 279        TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
 280        TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
 281        TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
 282        TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
 283        TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
 284        TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
 285        TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
 286        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
 287        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
 288        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
 289        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
 290        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
 291        TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
 292        TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
 293        TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
 294        TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
 295        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
 296        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
 297        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
 298        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
 299        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
 300        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
 301        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
 302        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
 303        TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
 304        TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
 305        TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
 306        TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
 307        TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
 308        TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
 309        TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
 310        TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
 311        TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
 312        TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
 313        TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
 314        TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
 315        TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
 316        TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
 317        TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
 318        TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
 319        TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
 320        TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
 321        TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
 322        TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
 323        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
 324        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
 325        TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
 326        TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
 327        TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
 328        TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
 329        TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
 330        TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
 331        TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
 332
 333#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
 334        TF_REG_LIST_SH_MASK_DCN(mask_sh),\
 335        TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
 336        TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
 337        TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
 338        TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
 339        TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
 340        TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
 341        TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
 342        TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
 343        TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
 344        TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
 345        TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
 346        TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
 347        TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
 348        TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
 349        TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
 350        TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
 351        TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
 352        TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
 353        TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
 354        TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
 355        TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
 356        TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
 357        TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
 358        TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
 359        TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
 360        TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
 361        TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
 362        TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
 363        TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
 364        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
 365        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
 366        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
 367        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
 368        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
 369        TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
 370        TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
 371        TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
 372        TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
 373        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
 374        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
 375        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
 376        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
 377        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
 378        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
 379        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
 380        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
 381        TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
 382        TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
 383        TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
 384        TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
 385        TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
 386        TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
 387        TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
 388        TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
 389        TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
 390        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
 391        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
 392        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
 393        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
 394        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
 395        TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
 396        TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
 397        TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
 398        TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
 399        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
 400        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
 401        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
 402        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
 403        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
 404        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
 405        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
 406        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
 407        TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
 408        TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
 409        TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
 410        TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
 411        TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
 412        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
 413        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
 414        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
 415        TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
 416        TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
 417        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
 418        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
 419        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
 420        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
 421        TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
 422        TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
 423        TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
 424        TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
 425        TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
 426        TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
 427        TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
 428        TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
 429        TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
 430        TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
 431        TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
 432        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
 433        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
 434        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
 435        TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
 436        TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
 437
 438/*
 439 *
 440        DCN1 CM debug status register definition
 441
 442        register :ID9_CM_STATUS do
 443        implement_ref :cm
 444        map to:  :cmdebugind, at: j
 445        width 32
 446        disclosure   NEVER
 447
 448                field :ID9_VUPDATE_CFG, [0], R
 449                field :ID9_IGAM_LUT_MODE, [2..1], R
 450                field :ID9_BNS_BYPASS, [3], R
 451                field :ID9_ICSC_MODE, [5..4], R
 452                field :ID9_DGAM_LUT_MODE, [8..6], R
 453                field :ID9_HDR_BYPASS, [9], R
 454                field :ID9_GAMUT_REMAP_MODE, [11..10], R
 455                field :ID9_RGAM_LUT_MODE, [14..12], R
 456                #1 free bit
 457                field :ID9_OCSC_MODE, [18..16], R
 458                field :ID9_DENORM_MODE, [21..19], R
 459                field :ID9_ROUND_TRUNC_MODE, [25..22], R
 460                field :ID9_DITHER_EN, [26], R
 461                field :ID9_DITHER_MODE, [28..27], R
 462        end
 463*/
 464
 465#define TF_DEBUG_REG_LIST_SH_DCN10 \
 466        .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
 467        .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
 468
 469#define TF_DEBUG_REG_LIST_MASK_DCN10 \
 470        .CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
 471        .CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
 472
 473#define TF_REG_FIELD_LIST(type) \
 474        type EXT_OVERSCAN_LEFT; \
 475        type EXT_OVERSCAN_RIGHT; \
 476        type EXT_OVERSCAN_BOTTOM; \
 477        type EXT_OVERSCAN_TOP; \
 478        type OTG_H_BLANK_START; \
 479        type OTG_H_BLANK_END; \
 480        type OTG_V_BLANK_START; \
 481        type OTG_V_BLANK_END; \
 482        type PIXEL_DEPTH; \
 483        type PIXEL_EXPAN_MODE; \
 484        type PIXEL_REDUCE_MODE; \
 485        type DYNAMIC_PIXEL_DEPTH; \
 486        type DITHER_EN; \
 487        type INTERLEAVE_EN; \
 488        type LB_DATA_FORMAT__ALPHA_EN; \
 489        type MEMORY_CONFIG; \
 490        type LB_MAX_PARTITIONS; \
 491        type AUTOCAL_MODE; \
 492        type AUTOCAL_NUM_PIPE; \
 493        type AUTOCAL_PIPE_ID; \
 494        type SCL_BLACK_OFFSET_RGB_Y; \
 495        type SCL_BLACK_OFFSET_CBCR; \
 496        type SCL_V_NUM_TAPS; \
 497        type SCL_H_NUM_TAPS; \
 498        type SCL_V_NUM_TAPS_C; \
 499        type SCL_H_NUM_TAPS_C; \
 500        type SCL_COEF_RAM_TAP_PAIR_IDX; \
 501        type SCL_COEF_RAM_PHASE; \
 502        type SCL_COEF_RAM_FILTER_TYPE; \
 503        type SCL_COEF_RAM_EVEN_TAP_COEF; \
 504        type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
 505        type SCL_COEF_RAM_ODD_TAP_COEF; \
 506        type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
 507        type SCL_H_2TAP_HARDCODE_COEF_EN; \
 508        type SCL_H_2TAP_SHARP_EN; \
 509        type SCL_H_2TAP_SHARP_FACTOR; \
 510        type SCL_V_2TAP_HARDCODE_COEF_EN; \
 511        type SCL_V_2TAP_SHARP_EN; \
 512        type SCL_V_2TAP_SHARP_FACTOR; \
 513        type SCL_COEF_RAM_SELECT; \
 514        type DSCL_MODE; \
 515        type RECOUT_START_X; \
 516        type RECOUT_START_Y; \
 517        type RECOUT_WIDTH; \
 518        type RECOUT_HEIGHT; \
 519        type MPC_WIDTH; \
 520        type MPC_HEIGHT; \
 521        type SCL_H_SCALE_RATIO; \
 522        type SCL_V_SCALE_RATIO; \
 523        type SCL_H_SCALE_RATIO_C; \
 524        type SCL_V_SCALE_RATIO_C; \
 525        type SCL_H_INIT_FRAC; \
 526        type SCL_H_INIT_INT; \
 527        type SCL_H_INIT_FRAC_C; \
 528        type SCL_H_INIT_INT_C; \
 529        type SCL_V_INIT_FRAC; \
 530        type SCL_V_INIT_INT; \
 531        type SCL_V_INIT_FRAC_BOT; \
 532        type SCL_V_INIT_INT_BOT; \
 533        type SCL_V_INIT_FRAC_C; \
 534        type SCL_V_INIT_INT_C; \
 535        type SCL_V_INIT_FRAC_BOT_C; \
 536        type SCL_V_INIT_INT_BOT_C; \
 537        type SCL_CHROMA_COEF_MODE; \
 538        type SCL_COEF_RAM_SELECT_CURRENT; \
 539        type CM_GAMUT_REMAP_MODE; \
 540        type CM_GAMUT_REMAP_C11; \
 541        type CM_GAMUT_REMAP_C12; \
 542        type CM_GAMUT_REMAP_C13; \
 543        type CM_GAMUT_REMAP_C14; \
 544        type CM_GAMUT_REMAP_C21; \
 545        type CM_GAMUT_REMAP_C22; \
 546        type CM_GAMUT_REMAP_C23; \
 547        type CM_GAMUT_REMAP_C24; \
 548        type CM_GAMUT_REMAP_C31; \
 549        type CM_GAMUT_REMAP_C32; \
 550        type CM_GAMUT_REMAP_C33; \
 551        type CM_GAMUT_REMAP_C34; \
 552        type CM_COMA_C11; \
 553        type CM_COMA_C12; \
 554        type CM_COMA_C33; \
 555        type CM_COMA_C34; \
 556        type CM_COMB_C11; \
 557        type CM_COMB_C12; \
 558        type CM_COMB_C33; \
 559        type CM_COMB_C34; \
 560        type CM_OCSC_MODE; \
 561        type CM_OCSC_C11; \
 562        type CM_OCSC_C12; \
 563        type CM_OCSC_C33; \
 564        type CM_OCSC_C34; \
 565        type RGAM_MEM_PWR_FORCE; \
 566        type CM_RGAM_LUT_DATA; \
 567        type CM_RGAM_LUT_WRITE_EN_MASK; \
 568        type CM_RGAM_LUT_WRITE_SEL; \
 569        type CM_RGAM_LUT_INDEX; \
 570        type CM_RGAM_RAMB_EXP_REGION_START_B; \
 571        type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
 572        type CM_RGAM_RAMB_EXP_REGION_START_G; \
 573        type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
 574        type CM_RGAM_RAMB_EXP_REGION_START_R; \
 575        type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
 576        type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
 577        type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
 578        type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
 579        type CM_RGAM_RAMB_EXP_REGION_END_B; \
 580        type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
 581        type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
 582        type CM_RGAM_RAMB_EXP_REGION_END_G; \
 583        type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
 584        type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
 585        type CM_RGAM_RAMB_EXP_REGION_END_R; \
 586        type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
 587        type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
 588        type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
 589        type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
 590        type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
 591        type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
 592        type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
 593        type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
 594        type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
 595        type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
 596        type CM_RGAM_RAMA_EXP_REGION_START_B; \
 597        type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
 598        type CM_RGAM_RAMA_EXP_REGION_START_G; \
 599        type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
 600        type CM_RGAM_RAMA_EXP_REGION_START_R; \
 601        type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
 602        type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
 603        type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
 604        type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
 605        type CM_RGAM_RAMA_EXP_REGION_END_B; \
 606        type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
 607        type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
 608        type CM_RGAM_RAMA_EXP_REGION_END_G; \
 609        type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
 610        type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
 611        type CM_RGAM_RAMA_EXP_REGION_END_R; \
 612        type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
 613        type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
 614        type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
 615        type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
 616        type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
 617        type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
 618        type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
 619        type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
 620        type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
 621        type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
 622        type CM_RGAM_LUT_MODE; \
 623        type CM_CMOUT_ROUND_TRUNC_MODE; \
 624        type CM_BLNDGAM_LUT_MODE; \
 625        type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
 626        type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
 627        type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \
 628        type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
 629        type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \
 630        type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
 631        type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
 632        type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
 633        type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
 634        type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \
 635        type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \
 636        type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \
 637        type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \
 638        type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \
 639        type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \
 640        type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \
 641        type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \
 642        type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \
 643        type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
 644        type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
 645        type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
 646        type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
 647        type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
 648        type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
 649        type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
 650        type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
 651        type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
 652        type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
 653        type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
 654        type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
 655        type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
 656        type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
 657        type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
 658        type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
 659        type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
 660        type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
 661        type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
 662        type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
 663        type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
 664        type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
 665        type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
 666        type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
 667        type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
 668        type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
 669        type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
 670        type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
 671        type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
 672        type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
 673        type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
 674        type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
 675        type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
 676        type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
 677        type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
 678        type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
 679        type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
 680        type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
 681        type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
 682        type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
 683        type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
 684        type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
 685        type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
 686        type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
 687        type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
 688        type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
 689        type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
 690        type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
 691        type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
 692        type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
 693        type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
 694        type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
 695        type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
 696        type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
 697        type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
 698        type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
 699        type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
 700        type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
 701        type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
 702        type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
 703        type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
 704        type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
 705        type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
 706        type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
 707        type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
 708        type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
 709        type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
 710        type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
 711        type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \
 712        type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
 713        type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \
 714        type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
 715        type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \
 716        type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
 717        type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
 718        type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
 719        type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
 720        type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \
 721        type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \
 722        type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \
 723        type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \
 724        type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \
 725        type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \
 726        type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \
 727        type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \
 728        type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \
 729        type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
 730        type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
 731        type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
 732        type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
 733        type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
 734        type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
 735        type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
 736        type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
 737        type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
 738        type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
 739        type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
 740        type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
 741        type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
 742        type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
 743        type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
 744        type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
 745        type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
 746        type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
 747        type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
 748        type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
 749        type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
 750        type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
 751        type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
 752        type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
 753        type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
 754        type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
 755        type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
 756        type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
 757        type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
 758        type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
 759        type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
 760        type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
 761        type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
 762        type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
 763        type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
 764        type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
 765        type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
 766        type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
 767        type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
 768        type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
 769        type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
 770        type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
 771        type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
 772        type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
 773        type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
 774        type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
 775        type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
 776        type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
 777        type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
 778        type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
 779        type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
 780        type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
 781        type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
 782        type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
 783        type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
 784        type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
 785        type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
 786        type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
 787        type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
 788        type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
 789        type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
 790        type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
 791        type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
 792        type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
 793        type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
 794        type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
 795        type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
 796        type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
 797        type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
 798        type CM_BLNDGAM_LUT_WRITE_SEL; \
 799        type CM_BLNDGAM_CONFIG_STATUS; \
 800        type CM_BLNDGAM_LUT_INDEX; \
 801        type BLNDGAM_MEM_PWR_FORCE; \
 802        type CM_3DLUT_MODE; \
 803        type CM_3DLUT_SIZE; \
 804        type CM_3DLUT_INDEX; \
 805        type CM_3DLUT_DATA0; \
 806        type CM_3DLUT_DATA1; \
 807        type CM_3DLUT_DATA_30BIT; \
 808        type CM_3DLUT_WRITE_EN_MASK; \
 809        type CM_3DLUT_RAM_SEL; \
 810        type CM_3DLUT_30BIT_EN; \
 811        type CM_3DLUT_CONFIG_STATUS; \
 812        type CM_3DLUT_READ_SEL; \
 813        type CM_SHAPER_LUT_MODE; \
 814        type CM_SHAPER_RAMB_EXP_REGION_START_B; \
 815        type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \
 816        type CM_SHAPER_RAMB_EXP_REGION_START_G; \
 817        type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \
 818        type CM_SHAPER_RAMB_EXP_REGION_START_R; \
 819        type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \
 820        type CM_SHAPER_RAMB_EXP_REGION_END_B; \
 821        type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \
 822        type CM_SHAPER_RAMB_EXP_REGION_END_G; \
 823        type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \
 824        type CM_SHAPER_RAMB_EXP_REGION_END_R; \
 825        type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \
 826        type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \
 827        type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
 828        type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \
 829        type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \
 830        type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \
 831        type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \
 832        type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \
 833        type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \
 834        type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \
 835        type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \
 836        type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \
 837        type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \
 838        type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \
 839        type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \
 840        type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \
 841        type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \
 842        type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \
 843        type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \
 844        type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \
 845        type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \
 846        type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \
 847        type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \
 848        type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \
 849        type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \
 850        type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \
 851        type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \
 852        type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \
 853        type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \
 854        type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \
 855        type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \
 856        type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \
 857        type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \
 858        type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \
 859        type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \
 860        type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \
 861        type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \
 862        type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \
 863        type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \
 864        type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \
 865        type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \
 866        type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \
 867        type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \
 868        type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \
 869        type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \
 870        type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \
 871        type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \
 872        type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \
 873        type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \
 874        type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \
 875        type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \
 876        type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \
 877        type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \
 878        type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \
 879        type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \
 880        type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \
 881        type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \
 882        type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \
 883        type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \
 884        type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \
 885        type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \
 886        type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \
 887        type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \
 888        type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \
 889        type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \
 890        type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \
 891        type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \
 892        type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \
 893        type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \
 894        type CM_SHAPER_RAMA_EXP_REGION_START_B; \
 895        type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \
 896        type CM_SHAPER_RAMA_EXP_REGION_START_G; \
 897        type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \
 898        type CM_SHAPER_RAMA_EXP_REGION_START_R; \
 899        type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \
 900        type CM_SHAPER_RAMA_EXP_REGION_END_B; \
 901        type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \
 902        type CM_SHAPER_RAMA_EXP_REGION_END_G; \
 903        type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \
 904        type CM_SHAPER_RAMA_EXP_REGION_END_R; \
 905        type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \
 906        type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \
 907        type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
 908        type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \
 909        type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
 910        type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \
 911        type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \
 912        type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \
 913        type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \
 914        type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \
 915        type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \
 916        type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \
 917        type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \
 918        type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \
 919        type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \
 920        type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \
 921        type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \
 922        type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \
 923        type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \
 924        type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \
 925        type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \
 926        type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \
 927        type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \
 928        type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \
 929        type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \
 930        type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \
 931        type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \
 932        type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \
 933        type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \
 934        type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \
 935        type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \
 936        type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \
 937        type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \
 938        type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \
 939        type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \
 940        type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \
 941        type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \
 942        type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \
 943        type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \
 944        type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \
 945        type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \
 946        type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \
 947        type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \
 948        type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \
 949        type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \
 950        type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \
 951        type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \
 952        type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \
 953        type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \
 954        type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \
 955        type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \
 956        type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \
 957        type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \
 958        type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \
 959        type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \
 960        type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \
 961        type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \
 962        type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \
 963        type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \
 964        type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \
 965        type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \
 966        type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \
 967        type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \
 968        type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \
 969        type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \
 970        type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \
 971        type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \
 972        type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
 973        type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
 974        type CM_SHAPER_LUT_WRITE_EN_MASK; \
 975        type CM_SHAPER_CONFIG_STATUS; \
 976        type CM_SHAPER_LUT_WRITE_SEL; \
 977        type CM_SHAPER_LUT_INDEX; \
 978        type CM_SHAPER_LUT_DATA; \
 979        type CM_DGAM_CONFIG_STATUS; \
 980        type CM_ICSC_MODE; \
 981        type CM_ICSC_C11; \
 982        type CM_ICSC_C12; \
 983        type CM_ICSC_C33; \
 984        type CM_ICSC_C34; \
 985        type CM_BNS_BIAS_R; \
 986        type CM_BNS_BIAS_G; \
 987        type CM_BNS_BIAS_B; \
 988        type CM_BNS_SCALE_R; \
 989        type CM_BNS_SCALE_G; \
 990        type CM_BNS_SCALE_B; \
 991        type CM_DGAM_RAMB_EXP_REGION_START_B; \
 992        type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
 993        type CM_DGAM_RAMB_EXP_REGION_START_G; \
 994        type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
 995        type CM_DGAM_RAMB_EXP_REGION_START_R; \
 996        type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
 997        type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
 998        type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
 999        type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
1000        type CM_DGAM_RAMB_EXP_REGION_END_B; \
1001        type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
1002        type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
1003        type CM_DGAM_RAMB_EXP_REGION_END_G; \
1004        type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
1005        type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
1006        type CM_DGAM_RAMB_EXP_REGION_END_R; \
1007        type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
1008        type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
1009        type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
1010        type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
1011        type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
1012        type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
1013        type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
1014        type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
1015        type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
1016        type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
1017        type CM_DGAM_RAMA_EXP_REGION_START_B; \
1018        type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
1019        type CM_DGAM_RAMA_EXP_REGION_START_G; \
1020        type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
1021        type CM_DGAM_RAMA_EXP_REGION_START_R; \
1022        type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
1023        type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
1024        type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
1025        type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
1026        type CM_DGAM_RAMA_EXP_REGION_END_B; \
1027        type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
1028        type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
1029        type CM_DGAM_RAMA_EXP_REGION_END_G; \
1030        type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
1031        type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
1032        type CM_DGAM_RAMA_EXP_REGION_END_R; \
1033        type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
1034        type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
1035        type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
1036        type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
1037        type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
1038        type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
1039        type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
1040        type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
1041        type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
1042        type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
1043        type SHARED_MEM_PWR_DIS; \
1044        type CM_IGAM_LUT_FORMAT_R; \
1045        type CM_IGAM_LUT_FORMAT_G; \
1046        type CM_IGAM_LUT_FORMAT_B; \
1047        type CM_IGAM_LUT_HOST_EN; \
1048        type CM_IGAM_LUT_RW_MODE; \
1049        type CM_IGAM_LUT_WRITE_EN_MASK; \
1050        type CM_IGAM_LUT_SEL; \
1051        type CM_IGAM_LUT_SEQ_COLOR; \
1052        type CM_IGAM_DGAM_CONFIG_STATUS; \
1053        type CM_DGAM_LUT_WRITE_EN_MASK; \
1054        type CM_DGAM_LUT_WRITE_SEL; \
1055        type CM_DGAM_LUT_INDEX; \
1056        type CM_DGAM_LUT_DATA; \
1057        type CM_DGAM_LUT_MODE; \
1058        type CM_IGAM_LUT_MODE; \
1059        type CM_IGAM_INPUT_FORMAT; \
1060        type CM_IGAM_LUT_RW_INDEX; \
1061        type CM_BYPASS_EN; \
1062        type FORMAT_EXPANSION_MODE; \
1063        type CNVC_BYPASS; \
1064        type OUTPUT_FP; \
1065        type CNVC_SURFACE_PIXEL_FORMAT; \
1066        type CURSOR_MODE; \
1067        type CURSOR_PITCH; \
1068        type CURSOR_LINES_PER_CHUNK; \
1069        type CURSOR_ENABLE; \
1070        type CUR0_MODE; \
1071        type CUR0_EXPANSION_MODE; \
1072        type CUR0_ENABLE; \
1073        type CM_BYPASS; \
1074        type CM_TEST_DEBUG_INDEX; \
1075        type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
1076        type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
1077        type FORMAT_CONTROL__ALPHA_EN; \
1078        type CUR0_COLOR0; \
1079        type CUR0_COLOR1; \
1080        type DPPCLK_RATE_CONTROL; \
1081        type DPP_CLOCK_ENABLE; \
1082        type CM_HDR_MULT_COEF; \
1083        type CUR0_FP_BIAS; \
1084        type CUR0_FP_SCALE;
1085
1086struct dcn_dpp_shift {
1087        TF_REG_FIELD_LIST(uint8_t)
1088};
1089
1090struct dcn_dpp_mask {
1091        TF_REG_FIELD_LIST(uint32_t)
1092};
1093
1094#define DPP_COMMON_REG_VARIABLE_LIST \
1095        uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
1096        uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
1097        uint32_t OTG_H_BLANK; \
1098        uint32_t OTG_V_BLANK; \
1099        uint32_t SCL_MODE; \
1100        uint32_t LB_DATA_FORMAT; \
1101        uint32_t LB_MEMORY_CTRL; \
1102        uint32_t DSCL_AUTOCAL; \
1103        uint32_t SCL_BLACK_OFFSET; \
1104        uint32_t SCL_TAP_CONTROL; \
1105        uint32_t SCL_COEF_RAM_TAP_SELECT; \
1106        uint32_t SCL_COEF_RAM_TAP_DATA; \
1107        uint32_t DSCL_2TAP_CONTROL; \
1108        uint32_t MPC_SIZE; \
1109        uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
1110        uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
1111        uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
1112        uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
1113        uint32_t SCL_HORZ_FILTER_INIT; \
1114        uint32_t SCL_HORZ_FILTER_INIT_C; \
1115        uint32_t SCL_VERT_FILTER_INIT; \
1116        uint32_t SCL_VERT_FILTER_INIT_BOT; \
1117        uint32_t SCL_VERT_FILTER_INIT_C; \
1118        uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
1119        uint32_t RECOUT_START; \
1120        uint32_t RECOUT_SIZE; \
1121        uint32_t CM_GAMUT_REMAP_CONTROL; \
1122        uint32_t CM_GAMUT_REMAP_C11_C12; \
1123        uint32_t CM_GAMUT_REMAP_C13_C14; \
1124        uint32_t CM_GAMUT_REMAP_C21_C22; \
1125        uint32_t CM_GAMUT_REMAP_C23_C24; \
1126        uint32_t CM_GAMUT_REMAP_C31_C32; \
1127        uint32_t CM_GAMUT_REMAP_C33_C34; \
1128        uint32_t CM_COMA_C11_C12; \
1129        uint32_t CM_COMA_C33_C34; \
1130        uint32_t CM_COMB_C11_C12; \
1131        uint32_t CM_COMB_C33_C34; \
1132        uint32_t CM_OCSC_CONTROL; \
1133        uint32_t CM_OCSC_C11_C12; \
1134        uint32_t CM_OCSC_C33_C34; \
1135        uint32_t CM_MEM_PWR_CTRL; \
1136        uint32_t CM_RGAM_LUT_DATA; \
1137        uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
1138        uint32_t CM_RGAM_LUT_INDEX; \
1139        uint32_t CM_RGAM_RAMB_START_CNTL_B; \
1140        uint32_t CM_RGAM_RAMB_START_CNTL_G; \
1141        uint32_t CM_RGAM_RAMB_START_CNTL_R; \
1142        uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
1143        uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
1144        uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
1145        uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
1146        uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
1147        uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
1148        uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
1149        uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
1150        uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
1151        uint32_t CM_RGAM_RAMB_REGION_0_1; \
1152        uint32_t CM_RGAM_RAMB_REGION_32_33; \
1153        uint32_t CM_RGAM_RAMA_START_CNTL_B; \
1154        uint32_t CM_RGAM_RAMA_START_CNTL_G; \
1155        uint32_t CM_RGAM_RAMA_START_CNTL_R; \
1156        uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
1157        uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
1158        uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
1159        uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
1160        uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
1161        uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
1162        uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
1163        uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
1164        uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
1165        uint32_t CM_RGAM_RAMA_REGION_0_1; \
1166        uint32_t CM_RGAM_RAMA_REGION_32_33; \
1167        uint32_t CM_RGAM_CONTROL; \
1168        uint32_t CM_CMOUT_CONTROL; \
1169        uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
1170        uint32_t CM_BLNDGAM_CONTROL; \
1171        uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
1172        uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \
1173        uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \
1174        uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \
1175        uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \
1176        uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \
1177        uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \
1178        uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \
1179        uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \
1180        uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \
1181        uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \
1182        uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \
1183        uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \
1184        uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \
1185        uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \
1186        uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \
1187        uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \
1188        uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \
1189        uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \
1190        uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \
1191        uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \
1192        uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \
1193        uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \
1194        uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \
1195        uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \
1196        uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \
1197        uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \
1198        uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \
1199        uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \
1200        uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \
1201        uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \
1202        uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \
1203        uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \
1204        uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \
1205        uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \
1206        uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \
1207        uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \
1208        uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \
1209        uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \
1210        uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \
1211        uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \
1212        uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \
1213        uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \
1214        uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \
1215        uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \
1216        uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \
1217        uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \
1218        uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \
1219        uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \
1220        uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \
1221        uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \
1222        uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \
1223        uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \
1224        uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \
1225        uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \
1226        uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \
1227        uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
1228        uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
1229        uint32_t CM_BLNDGAM_LUT_INDEX; \
1230        uint32_t CM_3DLUT_MODE; \
1231        uint32_t CM_3DLUT_INDEX; \
1232        uint32_t CM_3DLUT_DATA; \
1233        uint32_t CM_3DLUT_DATA_30BIT; \
1234        uint32_t CM_3DLUT_READ_WRITE_CONTROL; \
1235        uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
1236        uint32_t CM_SHAPER_CONTROL; \
1237        uint32_t CM_SHAPER_RAMB_START_CNTL_B; \
1238        uint32_t CM_SHAPER_RAMB_START_CNTL_G; \
1239        uint32_t CM_SHAPER_RAMB_START_CNTL_R; \
1240        uint32_t CM_SHAPER_RAMB_END_CNTL_B; \
1241        uint32_t CM_SHAPER_RAMB_END_CNTL_G; \
1242        uint32_t CM_SHAPER_RAMB_END_CNTL_R; \
1243        uint32_t CM_SHAPER_RAMB_REGION_0_1; \
1244        uint32_t CM_SHAPER_RAMB_REGION_2_3; \
1245        uint32_t CM_SHAPER_RAMB_REGION_4_5; \
1246        uint32_t CM_SHAPER_RAMB_REGION_6_7; \
1247        uint32_t CM_SHAPER_RAMB_REGION_8_9; \
1248        uint32_t CM_SHAPER_RAMB_REGION_10_11; \
1249        uint32_t CM_SHAPER_RAMB_REGION_12_13; \
1250        uint32_t CM_SHAPER_RAMB_REGION_14_15; \
1251        uint32_t CM_SHAPER_RAMB_REGION_16_17; \
1252        uint32_t CM_SHAPER_RAMB_REGION_18_19; \
1253        uint32_t CM_SHAPER_RAMB_REGION_20_21; \
1254        uint32_t CM_SHAPER_RAMB_REGION_22_23; \
1255        uint32_t CM_SHAPER_RAMB_REGION_24_25; \
1256        uint32_t CM_SHAPER_RAMB_REGION_26_27; \
1257        uint32_t CM_SHAPER_RAMB_REGION_28_29; \
1258        uint32_t CM_SHAPER_RAMB_REGION_30_31; \
1259        uint32_t CM_SHAPER_RAMB_REGION_32_33; \
1260        uint32_t CM_SHAPER_RAMA_START_CNTL_B; \
1261        uint32_t CM_SHAPER_RAMA_START_CNTL_G; \
1262        uint32_t CM_SHAPER_RAMA_START_CNTL_R; \
1263        uint32_t CM_SHAPER_RAMA_END_CNTL_B; \
1264        uint32_t CM_SHAPER_RAMA_END_CNTL_G; \
1265        uint32_t CM_SHAPER_RAMA_END_CNTL_R; \
1266        uint32_t CM_SHAPER_RAMA_REGION_0_1; \
1267        uint32_t CM_SHAPER_RAMA_REGION_2_3; \
1268        uint32_t CM_SHAPER_RAMA_REGION_4_5; \
1269        uint32_t CM_SHAPER_RAMA_REGION_6_7; \
1270        uint32_t CM_SHAPER_RAMA_REGION_8_9; \
1271        uint32_t CM_SHAPER_RAMA_REGION_10_11; \
1272        uint32_t CM_SHAPER_RAMA_REGION_12_13; \
1273        uint32_t CM_SHAPER_RAMA_REGION_14_15; \
1274        uint32_t CM_SHAPER_RAMA_REGION_16_17; \
1275        uint32_t CM_SHAPER_RAMA_REGION_18_19; \
1276        uint32_t CM_SHAPER_RAMA_REGION_20_21; \
1277        uint32_t CM_SHAPER_RAMA_REGION_22_23; \
1278        uint32_t CM_SHAPER_RAMA_REGION_24_25; \
1279        uint32_t CM_SHAPER_RAMA_REGION_26_27; \
1280        uint32_t CM_SHAPER_RAMA_REGION_28_29; \
1281        uint32_t CM_SHAPER_RAMA_REGION_30_31; \
1282        uint32_t CM_SHAPER_RAMA_REGION_32_33; \
1283        uint32_t CM_SHAPER_LUT_INDEX; \
1284        uint32_t CM_SHAPER_LUT_DATA; \
1285        uint32_t CM_ICSC_CONTROL; \
1286        uint32_t CM_ICSC_C11_C12; \
1287        uint32_t CM_ICSC_C33_C34; \
1288        uint32_t CM_BNS_VALUES_R; \
1289        uint32_t CM_BNS_VALUES_G; \
1290        uint32_t CM_BNS_VALUES_B; \
1291        uint32_t CM_DGAM_RAMB_START_CNTL_B; \
1292        uint32_t CM_DGAM_RAMB_START_CNTL_G; \
1293        uint32_t CM_DGAM_RAMB_START_CNTL_R; \
1294        uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \
1295        uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \
1296        uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \
1297        uint32_t CM_DGAM_RAMB_END_CNTL1_B; \
1298        uint32_t CM_DGAM_RAMB_END_CNTL2_B; \
1299        uint32_t CM_DGAM_RAMB_END_CNTL1_G; \
1300        uint32_t CM_DGAM_RAMB_END_CNTL2_G; \
1301        uint32_t CM_DGAM_RAMB_END_CNTL1_R; \
1302        uint32_t CM_DGAM_RAMB_END_CNTL2_R; \
1303        uint32_t CM_DGAM_RAMB_REGION_0_1; \
1304        uint32_t CM_DGAM_RAMB_REGION_14_15; \
1305        uint32_t CM_DGAM_RAMA_START_CNTL_B; \
1306        uint32_t CM_DGAM_RAMA_START_CNTL_G; \
1307        uint32_t CM_DGAM_RAMA_START_CNTL_R; \
1308        uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \
1309        uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \
1310        uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \
1311        uint32_t CM_DGAM_RAMA_END_CNTL1_B; \
1312        uint32_t CM_DGAM_RAMA_END_CNTL2_B; \
1313        uint32_t CM_DGAM_RAMA_END_CNTL1_G; \
1314        uint32_t CM_DGAM_RAMA_END_CNTL2_G; \
1315        uint32_t CM_DGAM_RAMA_END_CNTL1_R; \
1316        uint32_t CM_DGAM_RAMA_END_CNTL2_R; \
1317        uint32_t CM_DGAM_RAMA_REGION_0_1; \
1318        uint32_t CM_DGAM_RAMA_REGION_14_15; \
1319        uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
1320        uint32_t CM_DGAM_LUT_INDEX; \
1321        uint32_t CM_DGAM_LUT_DATA; \
1322        uint32_t CM_CONTROL; \
1323        uint32_t CM_DGAM_CONTROL; \
1324        uint32_t CM_IGAM_CONTROL; \
1325        uint32_t CM_IGAM_LUT_RW_CONTROL; \
1326        uint32_t CM_IGAM_LUT_RW_INDEX; \
1327        uint32_t CM_IGAM_LUT_SEQ_COLOR; \
1328        uint32_t CM_TEST_DEBUG_INDEX; \
1329        uint32_t CM_TEST_DEBUG_DATA; \
1330        uint32_t FORMAT_CONTROL; \
1331        uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
1332        uint32_t CURSOR_CONTROL; \
1333        uint32_t CURSOR0_CONTROL; \
1334        uint32_t CURSOR0_COLOR0; \
1335        uint32_t CURSOR0_COLOR1; \
1336        uint32_t DPP_CONTROL; \
1337        uint32_t CM_HDR_MULT_COEF; \
1338        uint32_t CURSOR0_FP_SCALE_BIAS;
1339
1340struct dcn_dpp_registers {
1341        DPP_COMMON_REG_VARIABLE_LIST
1342};
1343
1344struct dcn10_dpp {
1345        struct dpp base;
1346
1347        const struct dcn_dpp_registers *tf_regs;
1348        const struct dcn_dpp_shift *tf_shift;
1349        const struct dcn_dpp_mask *tf_mask;
1350
1351        const uint16_t *filter_v;
1352        const uint16_t *filter_h;
1353        const uint16_t *filter_v_c;
1354        const uint16_t *filter_h_c;
1355        int lb_pixel_depth_supported;
1356        int lb_memory_size;
1357        int lb_bits_per_entry;
1358        bool is_write_to_ram_a_safe;
1359        struct scaler_data scl_data;
1360        struct pwl_params pwl_data;
1361};
1362
1363enum dcn10_input_csc_select {
1364        INPUT_CSC_SELECT_BYPASS = 0,
1365        INPUT_CSC_SELECT_ICSC = 1,
1366        INPUT_CSC_SELECT_COMA = 2
1367};
1368
1369void dpp1_set_cursor_attributes(
1370                struct dpp *dpp_base,
1371                struct dc_cursor_attributes *cursor_attributes);
1372
1373void dpp1_set_cursor_position(
1374                struct dpp *dpp_base,
1375                const struct dc_cursor_position *pos,
1376                const struct dc_cursor_mi_param *param,
1377                uint32_t width,
1378                uint32_t height);
1379
1380void dpp1_cnv_set_optional_cursor_attributes(
1381                        struct dpp *dpp_base,
1382                        struct dpp_cursor_attributes *attr);
1383
1384bool dpp1_dscl_is_lb_conf_valid(
1385                int ceil_vratio,
1386                int num_partitions,
1387                int vtaps);
1388
1389void dpp1_dscl_calc_lb_num_partitions(
1390                const struct scaler_data *scl_data,
1391                enum lb_memory_config lb_config,
1392                int *num_part_y,
1393                int *num_part_c);
1394
1395void dpp1_degamma_ram_select(
1396                struct dpp *dpp_base,
1397                                                        bool use_ram_a);
1398
1399void dpp1_program_degamma_luta_settings(
1400                struct dpp *dpp_base,
1401                const struct pwl_params *params);
1402
1403void dpp1_program_degamma_lutb_settings(
1404                struct dpp *dpp_base,
1405                const struct pwl_params *params);
1406
1407void dpp1_program_degamma_lut(
1408                struct dpp *dpp_base,
1409                const struct pwl_result_data *rgb,
1410                uint32_t num,
1411                bool is_ram_a);
1412
1413void dpp1_power_on_degamma_lut(
1414                struct dpp *dpp_base,
1415        bool power_on);
1416
1417void dpp1_program_input_csc(
1418                struct dpp *dpp_base,
1419                enum dc_color_space color_space,
1420                enum dcn10_input_csc_select select,
1421                const struct out_csc_color_matrix *tbl_entry);
1422
1423void dpp1_program_bias_and_scale(
1424                struct dpp *dpp_base,
1425                struct dc_bias_and_scale *params);
1426
1427void dpp1_program_input_lut(
1428                struct dpp *dpp_base,
1429                const struct dc_gamma *gamma);
1430
1431void dpp1_full_bypass(struct dpp *dpp_base);
1432
1433void dpp1_set_degamma(
1434                struct dpp *dpp_base,
1435                enum ipp_degamma_mode mode);
1436
1437void dpp1_set_degamma_pwl(struct dpp *dpp_base,
1438                const struct pwl_params *params);
1439
1440
1441void dpp_read_state(struct dpp *dpp_base,
1442                struct dcn_dpp_state *s);
1443
1444void dpp_reset(struct dpp *dpp_base);
1445
1446void dpp1_cm_program_regamma_lut(
1447                struct dpp *dpp_base,
1448                const struct pwl_result_data *rgb,
1449                uint32_t num);
1450
1451void dpp1_cm_power_on_regamma_lut(
1452        struct dpp *dpp_base,
1453        bool power_on);
1454
1455void dpp1_cm_configure_regamma_lut(
1456                struct dpp *dpp_base,
1457                bool is_ram_a);
1458
1459/*program re gamma RAM A*/
1460void dpp1_cm_program_regamma_luta_settings(
1461                struct dpp *dpp_base,
1462                const struct pwl_params *params);
1463
1464/*program re gamma RAM B*/
1465void dpp1_cm_program_regamma_lutb_settings(
1466                struct dpp *dpp_base,
1467                const struct pwl_params *params);
1468void dpp1_cm_set_output_csc_adjustment(
1469                struct dpp *dpp_base,
1470                const uint16_t *regval);
1471
1472void dpp1_cm_set_output_csc_default(
1473                struct dpp *dpp_base,
1474                enum dc_color_space colorspace);
1475
1476void dpp1_cm_set_gamut_remap(
1477        struct dpp *dpp,
1478        const struct dpp_grph_csc_adjustment *adjust);
1479
1480void dpp1_dscl_set_scaler_manual_scale(
1481        struct dpp *dpp_base,
1482        const struct scaler_data *scl_data);
1483
1484void dpp1_cnv_setup (
1485                struct dpp *dpp_base,
1486                enum surface_pixel_format format,
1487                enum expansion_mode mode,
1488                struct dc_csc_transform input_csc_color_matrix,
1489                enum dc_color_space input_color_space,
1490                struct cnv_alpha_2bit_lut *alpha_2bit_lut);
1491
1492void dpp1_full_bypass(struct dpp *dpp_base);
1493
1494void dpp1_dppclk_control(
1495                struct dpp *dpp_base,
1496                bool dppclk_div,
1497                bool enable);
1498
1499void dpp1_set_hdr_multiplier(
1500                struct dpp *dpp_base,
1501                uint32_t multiplier);
1502
1503bool dpp1_get_optimal_number_of_taps(
1504                struct dpp *dpp,
1505                struct scaler_data *scl_data,
1506                const struct scaling_taps *in_taps);
1507
1508void dpp1_construct(struct dcn10_dpp *dpp1,
1509        struct dc_context *ctx,
1510        uint32_t inst,
1511        const struct dcn_dpp_registers *tf_regs,
1512        const struct dcn_dpp_shift *tf_shift,
1513        const struct dcn_dpp_mask *tf_mask);
1514#endif
1515