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26#ifndef __DC_LINK_ENCODER__DCN10_H__
27#define __DC_LINK_ENCODER__DCN10_H__
28
29#include "link_encoder.h"
30
31#define TO_DCN10_LINK_ENC(link_encoder)\
32 container_of(link_encoder, struct dcn10_link_encoder, base)
33
34#define AUX_REG_LIST(id)\
35 SRI(AUX_CONTROL, DP_AUX, id), \
36 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
37 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
38
39#define HPD_REG_LIST(id)\
40 SRI(DC_HPD_CONTROL, HPD, id)
41
42#define LE_DCN_COMMON_REG_LIST(id) \
43 SRI(DIG_BE_CNTL, DIG, id), \
44 SRI(DIG_BE_EN_CNTL, DIG, id), \
45 SRI(TMDS_CTL_BITS, DIG, id), \
46 SRI(DP_CONFIG, DP, id), \
47 SRI(DP_DPHY_CNTL, DP, id), \
48 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
49 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
50 SRI(DP_DPHY_SYM0, DP, id), \
51 SRI(DP_DPHY_SYM1, DP, id), \
52 SRI(DP_DPHY_SYM2, DP, id), \
53 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
54 SRI(DP_LINK_CNTL, DP, id), \
55 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
56 SRI(DP_MSE_SAT0, DP, id), \
57 SRI(DP_MSE_SAT1, DP, id), \
58 SRI(DP_MSE_SAT2, DP, id), \
59 SRI(DP_MSE_SAT_UPDATE, DP, id), \
60 SRI(DP_SEC_CNTL, DP, id), \
61 SRI(DP_VID_STREAM_CNTL, DP, id), \
62 SRI(DP_DPHY_FAST_TRAINING, DP, id), \
63 SRI(DP_SEC_CNTL1, DP, id), \
64 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
65 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
66
67
68#define LE_DCN10_REG_LIST(id)\
69 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
70 LE_DCN_COMMON_REG_LIST(id)
71
72struct dcn10_link_enc_aux_registers {
73 uint32_t AUX_CONTROL;
74 uint32_t AUX_DPHY_RX_CONTROL0;
75 uint32_t AUX_DPHY_TX_CONTROL;
76 uint32_t AUX_DPHY_RX_CONTROL1;
77};
78
79struct dcn10_link_enc_hpd_registers {
80 uint32_t DC_HPD_CONTROL;
81};
82
83struct dcn10_link_enc_registers {
84 uint32_t DIG_BE_CNTL;
85 uint32_t DIG_BE_EN_CNTL;
86 uint32_t DP_CONFIG;
87 uint32_t DP_DPHY_CNTL;
88 uint32_t DP_DPHY_INTERNAL_CTRL;
89 uint32_t DP_DPHY_PRBS_CNTL;
90 uint32_t DP_DPHY_SCRAM_CNTL;
91 uint32_t DP_DPHY_SYM0;
92 uint32_t DP_DPHY_SYM1;
93 uint32_t DP_DPHY_SYM2;
94 uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
95 uint32_t DP_LINK_CNTL;
96 uint32_t DP_LINK_FRAMING_CNTL;
97 uint32_t DP_MSE_SAT0;
98 uint32_t DP_MSE_SAT1;
99 uint32_t DP_MSE_SAT2;
100 uint32_t DP_MSE_SAT_UPDATE;
101 uint32_t DP_SEC_CNTL;
102 uint32_t DP_VID_STREAM_CNTL;
103 uint32_t DP_DPHY_FAST_TRAINING;
104 uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
105 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
106 uint32_t DP_SEC_CNTL1;
107 uint32_t TMDS_CTL_BITS;
108
109 uint32_t CLOCK_ENABLE;
110
111 uint32_t DIG_LANE_ENABLE;
112
113 uint32_t CHANNEL_XBAR_CNTL;
114
115 uint32_t RDPCSTX_PHY_CNTL3;
116 uint32_t RDPCSTX_PHY_CNTL4;
117 uint32_t RDPCSTX_PHY_CNTL5;
118 uint32_t RDPCSTX_PHY_CNTL6;
119 uint32_t RDPCSTX_PHY_CNTL7;
120 uint32_t RDPCSTX_PHY_CNTL8;
121 uint32_t RDPCSTX_PHY_CNTL9;
122 uint32_t RDPCSTX_PHY_CNTL10;
123 uint32_t RDPCSTX_PHY_CNTL11;
124 uint32_t RDPCSTX_PHY_CNTL12;
125 uint32_t RDPCSTX_PHY_CNTL13;
126 uint32_t RDPCSTX_PHY_CNTL14;
127 uint32_t RDPCSTX_PHY_CNTL15;
128 uint32_t RDPCSTX_CNTL;
129 uint32_t RDPCSTX_CLOCK_CNTL;
130 uint32_t RDPCSTX_PHY_CNTL0;
131 uint32_t RDPCSTX_PHY_CNTL2;
132 uint32_t RDPCSTX_PLL_UPDATE_DATA;
133 uint32_t RDPCS_TX_CR_ADDR;
134 uint32_t RDPCS_TX_CR_DATA;
135 uint32_t DPCSTX_TX_CLOCK_CNTL;
136 uint32_t DPCSTX_TX_CNTL;
137 uint32_t RDPCSTX_INTERRUPT_CONTROL;
138 uint32_t RDPCSTX_PHY_FUSE0;
139 uint32_t RDPCSTX_PHY_FUSE1;
140 uint32_t RDPCSTX_PHY_FUSE2;
141 uint32_t RDPCSTX_PHY_FUSE3;
142 uint32_t RDPCSTX_PHY_RX_LD_VAL;
143 uint32_t DPCSTX_DEBUG_CONFIG;
144 uint32_t RDPCSTX_DEBUG_CONFIG;
145 uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
146 uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
147 uint32_t DCIO_SOFT_RESET;
148
149 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
150 uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
151 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
152 uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
153 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
154 uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
155 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
156 uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
157#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
158 uint32_t TMDS_DCBALANCER_CONTROL;
159 uint32_t PHYA_LINK_CNTL2;
160 uint32_t PHYB_LINK_CNTL2;
161 uint32_t PHYC_LINK_CNTL2;
162#endif
163};
164
165#define LE_SF(reg_name, field_name, post_fix)\
166 .field_name = reg_name ## __ ## field_name ## post_fix
167
168#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
169 LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
170 LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
171 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
172 LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
173 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
174 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
175 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
176 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
177 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
178 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
179 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
180 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
181 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
182 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
183 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
184 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
185 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
186 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
187 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
188 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
189 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
190 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
191 LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
192 LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
193 LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
194 LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
195 LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
196 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
197 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
198 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
199 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
200 LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
201 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
202 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
203 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
204 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
205 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
206 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
207 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
208 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
209 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
210 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
211 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
212 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
213 LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
214 LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
215 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
216 LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
217
218#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
219 type DIG_ENABLE;\
220 type DIG_HPD_SELECT;\
221 type DIG_MODE;\
222 type DIG_FE_SOURCE_SELECT;\
223 type DPHY_BYPASS;\
224 type DPHY_ATEST_SEL_LANE0;\
225 type DPHY_ATEST_SEL_LANE1;\
226 type DPHY_ATEST_SEL_LANE2;\
227 type DPHY_ATEST_SEL_LANE3;\
228 type DPHY_PRBS_EN;\
229 type DPHY_PRBS_SEL;\
230 type DPHY_SYM1;\
231 type DPHY_SYM2;\
232 type DPHY_SYM3;\
233 type DPHY_SYM4;\
234 type DPHY_SYM5;\
235 type DPHY_SYM6;\
236 type DPHY_SYM7;\
237 type DPHY_SYM8;\
238 type DPHY_SCRAMBLER_BS_COUNT;\
239 type DPHY_SCRAMBLER_ADVANCE;\
240 type DPHY_RX_FAST_TRAINING_CAPABLE;\
241 type DPHY_LOAD_BS_COUNT;\
242 type DPHY_TRAINING_PATTERN_SEL;\
243 type DP_DPHY_HBR2_PATTERN_CONTROL;\
244 type DP_LINK_TRAINING_COMPLETE;\
245 type DP_IDLE_BS_INTERVAL;\
246 type DP_VBID_DISABLE;\
247 type DP_VID_ENHANCED_FRAME_MODE;\
248 type DP_VID_STREAM_ENABLE;\
249 type DP_UDI_LANES;\
250 type DP_SEC_GSP0_LINE_NUM;\
251 type DP_SEC_GSP0_PRIORITY;\
252 type DP_MSE_SAT_SRC0;\
253 type DP_MSE_SAT_SRC1;\
254 type DP_MSE_SAT_SRC2;\
255 type DP_MSE_SAT_SRC3;\
256 type DP_MSE_SAT_SLOT_COUNT0;\
257 type DP_MSE_SAT_SLOT_COUNT1;\
258 type DP_MSE_SAT_SLOT_COUNT2;\
259 type DP_MSE_SAT_SLOT_COUNT3;\
260 type DP_MSE_SAT_UPDATE;\
261 type DP_MSE_16_MTP_KEEPOUT;\
262 type DC_HPD_EN;\
263 type TMDS_CTL0;\
264 type AUX_HPD_SEL;\
265 type AUX_LS_READ_EN;\
266 type AUX_RX_RECEIVE_WINDOW
267
268
269#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
270 type RDPCS_PHY_DP_TX0_DATA_EN;\
271 type RDPCS_PHY_DP_TX1_DATA_EN;\
272 type RDPCS_PHY_DP_TX2_DATA_EN;\
273 type RDPCS_PHY_DP_TX3_DATA_EN;\
274 type RDPCS_PHY_DP_TX0_PSTATE;\
275 type RDPCS_PHY_DP_TX1_PSTATE;\
276 type RDPCS_PHY_DP_TX2_PSTATE;\
277 type RDPCS_PHY_DP_TX3_PSTATE;\
278 type RDPCS_PHY_DP_TX0_MPLL_EN;\
279 type RDPCS_PHY_DP_TX1_MPLL_EN;\
280 type RDPCS_PHY_DP_TX2_MPLL_EN;\
281 type RDPCS_PHY_DP_TX3_MPLL_EN;\
282 type RDPCS_TX_FIFO_LANE0_EN;\
283 type RDPCS_TX_FIFO_LANE1_EN;\
284 type RDPCS_TX_FIFO_LANE2_EN;\
285 type RDPCS_TX_FIFO_LANE3_EN;\
286 type RDPCS_EXT_REFCLK_EN;\
287 type RDPCS_TX_FIFO_EN;\
288 type UNIPHY_LINK_ENABLE;\
289 type UNIPHY_CHANNEL0_XBAR_SOURCE;\
290 type UNIPHY_CHANNEL1_XBAR_SOURCE;\
291 type UNIPHY_CHANNEL2_XBAR_SOURCE;\
292 type UNIPHY_CHANNEL3_XBAR_SOURCE;\
293 type UNIPHY_CHANNEL0_INVERT;\
294 type UNIPHY_CHANNEL1_INVERT;\
295 type UNIPHY_CHANNEL2_INVERT;\
296 type UNIPHY_CHANNEL3_INVERT;\
297 type UNIPHY_LINK_ENABLE_HPD_MASK;\
298 type UNIPHY_LANE_STAGGER_DELAY;\
299 type RDPCS_SRAMCLK_BYPASS;\
300 type RDPCS_SRAMCLK_EN;\
301 type RDPCS_SRAMCLK_CLOCK_ON;\
302 type DPCS_TX_FIFO_EN;\
303 type RDPCS_PHY_DP_TX0_DISABLE;\
304 type RDPCS_PHY_DP_TX1_DISABLE;\
305 type RDPCS_PHY_DP_TX2_DISABLE;\
306 type RDPCS_PHY_DP_TX3_DISABLE;\
307 type RDPCS_PHY_DP_TX0_CLK_RDY;\
308 type RDPCS_PHY_DP_TX1_CLK_RDY;\
309 type RDPCS_PHY_DP_TX2_CLK_RDY;\
310 type RDPCS_PHY_DP_TX3_CLK_RDY;\
311 type RDPCS_PHY_DP_TX0_REQ;\
312 type RDPCS_PHY_DP_TX1_REQ;\
313 type RDPCS_PHY_DP_TX2_REQ;\
314 type RDPCS_PHY_DP_TX3_REQ;\
315 type RDPCS_PHY_DP_TX0_ACK;\
316 type RDPCS_PHY_DP_TX1_ACK;\
317 type RDPCS_PHY_DP_TX2_ACK;\
318 type RDPCS_PHY_DP_TX3_ACK;\
319 type RDPCS_PHY_DP_TX0_RESET;\
320 type RDPCS_PHY_DP_TX1_RESET;\
321 type RDPCS_PHY_DP_TX2_RESET;\
322 type RDPCS_PHY_DP_TX3_RESET;\
323 type RDPCS_PHY_RESET;\
324 type RDPCS_PHY_CR_MUX_SEL;\
325 type RDPCS_PHY_REF_RANGE;\
326 type RDPCS_PHY_DP4_POR;\
327 type RDPCS_SRAM_BYPASS;\
328 type RDPCS_SRAM_EXT_LD_DONE;\
329 type RDPCS_PHY_DP_TX0_TERM_CTRL;\
330 type RDPCS_PHY_DP_TX1_TERM_CTRL;\
331 type RDPCS_PHY_DP_TX2_TERM_CTRL;\
332 type RDPCS_PHY_DP_TX3_TERM_CTRL;\
333 type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
334 type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
335 type RDPCS_PHY_DP_MPLLB_SSC_EN;\
336 type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
337 type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
338 type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
339 type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
340 type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
341 type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
342 type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
343 type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
344 type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
345 type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
346 type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
347 type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
348 type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
349 type RDPCS_PHY_TX_VBOOST_LVL;\
350 type RDPCS_PHY_HDMIMODE_ENABLE;\
351 type RDPCS_PHY_DP_REF_CLK_EN;\
352 type RDPCS_PLL_UPDATE_DATA;\
353 type RDPCS_SRAM_INIT_DONE;\
354 type RDPCS_TX_CR_ADDR;\
355 type RDPCS_TX_CR_DATA;\
356 type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
357 type RDPCS_PHY_DP_MPLLB_STATE;\
358 type RDPCS_PHY_DP_TX0_WIDTH;\
359 type RDPCS_PHY_DP_TX0_RATE;\
360 type RDPCS_PHY_DP_TX1_WIDTH;\
361 type RDPCS_PHY_DP_TX1_RATE;\
362 type RDPCS_PHY_DP_TX2_WIDTH;\
363 type RDPCS_PHY_DP_TX2_RATE;\
364 type RDPCS_PHY_DP_TX3_WIDTH;\
365 type RDPCS_PHY_DP_TX3_RATE;\
366 type DPCS_SYMCLK_CLOCK_ON;\
367 type DPCS_SYMCLK_GATE_DIS;\
368 type DPCS_SYMCLK_EN;\
369 type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
370 type RDPCS_SYMCLK_DIV2_GATE_DIS;\
371 type RDPCS_SYMCLK_DIV2_EN;\
372 type DPCS_TX_DATA_SWAP;\
373 type DPCS_TX_DATA_ORDER_INVERT;\
374 type DPCS_TX_FIFO_RD_START_DELAY;\
375 type RDPCS_TX_FIFO_RD_START_DELAY;\
376 type RDPCS_REG_FIFO_ERROR_MASK;\
377 type RDPCS_TX_FIFO_ERROR_MASK;\
378 type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
379 type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
380 type RDPCS_PHY_DPALT_DP4;\
381 type RDPCS_PHY_DPALT_DISABLE;\
382 type RDPCS_PHY_DPALT_DISABLE_ACK;\
383 type RDPCS_PHY_DP_MPLLB_V2I;\
384 type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
385 type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
386 type RDPCS_PHY_RX_VREF_CTRL;\
387 type RDPCS_PHY_DP_MPLLB_CP_INT;\
388 type RDPCS_PHY_DP_MPLLB_CP_PROP;\
389 type RDPCS_PHY_RX_REF_LD_VAL;\
390 type RDPCS_PHY_RX_VCO_LD_VAL;\
391 type DPCSTX_DEBUG_CONFIG; \
392 type RDPCSTX_DEBUG_CONFIG; \
393 type RDPCS_PHY_DP_TX0_EQ_MAIN;\
394 type RDPCS_PHY_DP_TX0_EQ_PRE;\
395 type RDPCS_PHY_DP_TX0_EQ_POST;\
396 type RDPCS_PHY_DP_TX1_EQ_MAIN;\
397 type RDPCS_PHY_DP_TX1_EQ_PRE;\
398 type RDPCS_PHY_DP_TX1_EQ_POST;\
399 type RDPCS_PHY_DP_TX2_EQ_MAIN;\
400 type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
401 type RDPCS_PHY_DP_TX2_EQ_PRE;\
402 type RDPCS_PHY_DP_TX2_EQ_POST;\
403 type RDPCS_PHY_DP_TX3_EQ_MAIN;\
404 type RDPCS_PHY_DCO_RANGE;\
405 type RDPCS_PHY_DCO_FINETUNE;\
406 type RDPCS_PHY_DP_TX3_EQ_PRE;\
407 type RDPCS_PHY_DP_TX3_EQ_POST;\
408 type RDPCS_PHY_SUP_PRE_HP;\
409 type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
410 type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
411 type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
412 type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
413 type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
414 type UNIPHYA_SOFT_RESET;\
415 type UNIPHYB_SOFT_RESET;\
416 type UNIPHYC_SOFT_RESET;\
417 type UNIPHYD_SOFT_RESET;\
418 type UNIPHYE_SOFT_RESET;\
419 type UNIPHYF_SOFT_RESET
420
421#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
422 type DIG_LANE0EN;\
423 type DIG_LANE1EN;\
424 type DIG_LANE2EN;\
425 type DIG_LANE3EN;\
426 type DIG_CLK_EN;\
427 type SYMCLKA_CLOCK_ENABLE;\
428 type DPHY_FEC_EN;\
429 type DPHY_FEC_READY_SHADOW;\
430 type DPHY_FEC_ACTIVE_STATUS;\
431 DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
432 type VCO_LD_VAL_OVRD;\
433 type VCO_LD_VAL_OVRD_EN;\
434 type REF_LD_VAL_OVRD;\
435 type REF_LD_VAL_OVRD_EN;\
436 type AUX_RX_START_WINDOW; \
437 type AUX_RX_HALF_SYM_DETECT_LEN; \
438 type AUX_RX_TRANSITION_FILTER_EN; \
439 type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
440 type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
441 type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
442 type AUX_RX_PHASE_DETECT_LEN; \
443 type AUX_RX_DETECTION_THRESHOLD; \
444 type AUX_TX_PRECHARGE_LEN; \
445 type AUX_TX_PRECHARGE_SYMBOLS; \
446 type AUX_MODE_DET_CHECK_DELAY;\
447 type DPCS_DBG_CBUS_DIS;\
448 type AUX_RX_PRECHARGE_SKIP;\
449 type AUX_RX_TIMEOUT_LEN;\
450 type AUX_RX_TIMEOUT_LEN_MUL
451
452struct dcn10_link_enc_shift {
453 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
454 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
455};
456
457struct dcn10_link_enc_mask {
458 DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
459 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
460};
461
462struct dcn10_link_encoder {
463 struct link_encoder base;
464 const struct dcn10_link_enc_registers *link_regs;
465 const struct dcn10_link_enc_aux_registers *aux_regs;
466 const struct dcn10_link_enc_hpd_registers *hpd_regs;
467 const struct dcn10_link_enc_shift *link_shift;
468 const struct dcn10_link_enc_mask *link_mask;
469};
470
471
472void dcn10_link_encoder_construct(
473 struct dcn10_link_encoder *enc10,
474 const struct encoder_init_data *init_data,
475 const struct encoder_feature_support *enc_features,
476 const struct dcn10_link_enc_registers *link_regs,
477 const struct dcn10_link_enc_aux_registers *aux_regs,
478 const struct dcn10_link_enc_hpd_registers *hpd_regs,
479 const struct dcn10_link_enc_shift *link_shift,
480 const struct dcn10_link_enc_mask *link_mask);
481
482bool dcn10_link_encoder_validate_dvi_output(
483 const struct dcn10_link_encoder *enc10,
484 enum signal_type connector_signal,
485 enum signal_type signal,
486 const struct dc_crtc_timing *crtc_timing);
487
488bool dcn10_link_encoder_validate_rgb_output(
489 const struct dcn10_link_encoder *enc10,
490 const struct dc_crtc_timing *crtc_timing);
491
492bool dcn10_link_encoder_validate_dp_output(
493 const struct dcn10_link_encoder *enc10,
494 const struct dc_crtc_timing *crtc_timing);
495
496bool dcn10_link_encoder_validate_wireless_output(
497 const struct dcn10_link_encoder *enc10,
498 const struct dc_crtc_timing *crtc_timing);
499
500bool dcn10_link_encoder_validate_output_with_stream(
501 struct link_encoder *enc,
502 const struct dc_stream_state *stream);
503
504
505
506
507void dcn10_link_encoder_hw_init(struct link_encoder *enc);
508
509void dcn10_link_encoder_destroy(struct link_encoder **enc);
510
511
512
513void dcn10_link_encoder_setup(
514 struct link_encoder *enc,
515 enum signal_type signal);
516
517void enc1_configure_encoder(
518 struct dcn10_link_encoder *enc10,
519 const struct dc_link_settings *link_settings);
520
521
522
523void dcn10_link_encoder_enable_tmds_output(
524 struct link_encoder *enc,
525 enum clock_source_id clock_source,
526 enum dc_color_depth color_depth,
527 enum signal_type signal,
528 uint32_t pixel_clock);
529
530
531void dcn10_link_encoder_enable_dp_output(
532 struct link_encoder *enc,
533 const struct dc_link_settings *link_settings,
534 enum clock_source_id clock_source);
535
536
537void dcn10_link_encoder_enable_dp_mst_output(
538 struct link_encoder *enc,
539 const struct dc_link_settings *link_settings,
540 enum clock_source_id clock_source);
541
542
543void dcn10_link_encoder_disable_output(
544 struct link_encoder *enc,
545 enum signal_type signal);
546
547
548void dcn10_link_encoder_dp_set_lane_settings(
549 struct link_encoder *enc,
550 const struct link_training_settings *link_settings);
551
552void dcn10_link_encoder_dp_set_phy_pattern(
553 struct link_encoder *enc,
554 const struct encoder_set_dp_phy_pattern_param *param);
555
556
557void dcn10_link_encoder_update_mst_stream_allocation_table(
558 struct link_encoder *enc,
559 const struct link_mst_stream_allocation_table *table);
560
561void dcn10_link_encoder_connect_dig_be_to_fe(
562 struct link_encoder *enc,
563 enum engine_id engine,
564 bool connect);
565
566void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
567 struct link_encoder *enc,
568 uint32_t index);
569
570void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
571
572void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
573
574void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
575 bool exit_link_training_required);
576
577void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
578 unsigned int sdp_transmit_line_num_deadline);
579
580bool dcn10_is_dig_enabled(struct link_encoder *enc);
581
582unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
583
584void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
585
586enum signal_type dcn10_get_dig_mode(
587 struct link_encoder *enc);
588
589void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
590 struct dc_link_settings *link_settings);
591#endif
592
