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26
27#include "reg_helper.h"
28#include "dcn10_optc.h"
29#include "dc.h"
30
31#define REG(reg)\
32 optc1->tg_regs->reg
33
34#define CTX \
35 optc1->base.ctx
36
37#undef FN
38#define FN(reg_name, field_name) \
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
40
41#define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
42
43
44
45
46
47
48
49static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
50{
51 if (timing->flags.INTERLACE == 1) {
52 if (timing->v_front_porch < 2)
53 timing->v_front_porch = 2;
54 } else {
55 if (timing->v_front_porch < 1)
56 timing->v_front_porch = 1;
57 }
58}
59
60void optc1_program_global_sync(
61 struct timing_generator *optc,
62 int vready_offset,
63 int vstartup_start,
64 int vupdate_offset,
65 int vupdate_width)
66{
67 struct optc *optc1 = DCN10TG_FROM_TG(optc);
68
69 optc1->vready_offset = vready_offset;
70 optc1->vstartup_start = vstartup_start;
71 optc1->vupdate_offset = vupdate_offset;
72 optc1->vupdate_width = vupdate_width;
73
74 if (optc1->vstartup_start == 0) {
75 BREAK_TO_DEBUGGER();
76 return;
77 }
78
79 REG_SET(OTG_VSTARTUP_PARAM, 0,
80 VSTARTUP_START, optc1->vstartup_start);
81
82 REG_SET_2(OTG_VUPDATE_PARAM, 0,
83 VUPDATE_OFFSET, optc1->vupdate_offset,
84 VUPDATE_WIDTH, optc1->vupdate_width);
85
86 REG_SET(OTG_VREADY_PARAM, 0,
87 VREADY_OFFSET, optc1->vready_offset);
88}
89
90static void optc1_disable_stereo(struct timing_generator *optc)
91{
92 struct optc *optc1 = DCN10TG_FROM_TG(optc);
93
94 REG_SET(OTG_STEREO_CONTROL, 0,
95 OTG_STEREO_EN, 0);
96
97 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
98 OTG_3D_STRUCTURE_EN, 0,
99 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
100}
101
102void optc1_setup_vertical_interrupt0(
103 struct timing_generator *optc,
104 uint32_t start_line,
105 uint32_t end_line)
106{
107 struct optc *optc1 = DCN10TG_FROM_TG(optc);
108
109 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
110 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
111 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
112}
113
114void optc1_setup_vertical_interrupt1(
115 struct timing_generator *optc,
116 uint32_t start_line)
117{
118 struct optc *optc1 = DCN10TG_FROM_TG(optc);
119
120 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
121 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
122}
123
124void optc1_setup_vertical_interrupt2(
125 struct timing_generator *optc,
126 uint32_t start_line)
127{
128 struct optc *optc1 = DCN10TG_FROM_TG(optc);
129
130 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
131 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
132}
133
134
135
136
137
138
139void optc1_program_timing(
140 struct timing_generator *optc,
141 const struct dc_crtc_timing *dc_crtc_timing,
142 int vready_offset,
143 int vstartup_start,
144 int vupdate_offset,
145 int vupdate_width,
146 const enum signal_type signal,
147 bool use_vbios)
148{
149 struct dc_crtc_timing patched_crtc_timing;
150 uint32_t asic_blank_end;
151 uint32_t asic_blank_start;
152 uint32_t v_total;
153 uint32_t v_sync_end;
154 uint32_t h_sync_polarity, v_sync_polarity;
155 uint32_t start_point = 0;
156 uint32_t field_num = 0;
157 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
158
159 struct optc *optc1 = DCN10TG_FROM_TG(optc);
160
161 optc1->signal = signal;
162 optc1->vready_offset = vready_offset;
163 optc1->vstartup_start = vstartup_start;
164 optc1->vupdate_offset = vupdate_offset;
165 optc1->vupdate_width = vupdate_width;
166 patched_crtc_timing = *dc_crtc_timing;
167 apply_front_porch_workaround(&patched_crtc_timing);
168
169
170
171
172 REG_SET(OTG_H_TOTAL, 0,
173 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
174
175
176 REG_UPDATE_2(OTG_H_SYNC_A,
177 OTG_H_SYNC_A_START, 0,
178 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
179
180
181 asic_blank_start = patched_crtc_timing.h_total -
182 patched_crtc_timing.h_front_porch;
183
184
185 asic_blank_end = asic_blank_start -
186 patched_crtc_timing.h_border_right -
187 patched_crtc_timing.h_addressable -
188 patched_crtc_timing.h_border_left;
189
190 REG_UPDATE_2(OTG_H_BLANK_START_END,
191 OTG_H_BLANK_START, asic_blank_start,
192 OTG_H_BLANK_END, asic_blank_end);
193
194
195 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
196 0 : 1;
197
198 REG_UPDATE(OTG_H_SYNC_A_CNTL,
199 OTG_H_SYNC_A_POL, h_sync_polarity);
200
201 v_total = patched_crtc_timing.v_total - 1;
202
203 REG_SET(OTG_V_TOTAL, 0,
204 OTG_V_TOTAL, v_total);
205
206
207
208
209 REG_SET(OTG_V_TOTAL_MAX, 0,
210 OTG_V_TOTAL_MAX, v_total);
211 REG_SET(OTG_V_TOTAL_MIN, 0,
212 OTG_V_TOTAL_MIN, v_total);
213
214
215 v_sync_end = patched_crtc_timing.v_sync_width;
216
217 REG_UPDATE_2(OTG_V_SYNC_A,
218 OTG_V_SYNC_A_START, 0,
219 OTG_V_SYNC_A_END, v_sync_end);
220
221
222 asic_blank_start = patched_crtc_timing.v_total -
223 patched_crtc_timing.v_front_porch;
224
225
226 asic_blank_end = asic_blank_start -
227 patched_crtc_timing.v_border_bottom -
228 patched_crtc_timing.v_addressable -
229 patched_crtc_timing.v_border_top;
230
231 REG_UPDATE_2(OTG_V_BLANK_START_END,
232 OTG_V_BLANK_START, asic_blank_start,
233 OTG_V_BLANK_END, asic_blank_end);
234
235
236 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
237 0 : 1;
238
239 REG_UPDATE(OTG_V_SYNC_A_CNTL,
240 OTG_V_SYNC_A_POL, v_sync_polarity);
241
242 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
243 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
244 optc1->signal == SIGNAL_TYPE_EDP) {
245 start_point = 1;
246 if (patched_crtc_timing.flags.INTERLACE == 1)
247 field_num = 1;
248 }
249
250
251 if (REG(OTG_INTERLACE_CONTROL)) {
252 if (patched_crtc_timing.flags.INTERLACE == 1)
253 REG_UPDATE(OTG_INTERLACE_CONTROL,
254 OTG_INTERLACE_ENABLE, 1);
255 else
256 REG_UPDATE(OTG_INTERLACE_CONTROL,
257 OTG_INTERLACE_ENABLE, 0);
258 }
259
260
261 REG_UPDATE(CONTROL,
262 VTG0_ENABLE, 0);
263
264
265 REG_UPDATE_2(OTG_CONTROL,
266 OTG_START_POINT_CNTL, start_point,
267 OTG_FIELD_NUMBER_CNTL, field_num);
268
269 optc->funcs->program_global_sync(optc,
270 vready_offset,
271 vstartup_start,
272 vupdate_offset,
273 vupdate_width);
274
275 optc->funcs->set_vtg_params(optc, dc_crtc_timing);
276
277
278
279
280
281
282
283
284
285
286
287
288 if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
289 h_div = H_TIMING_DIV_BY2;
290
291#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
292 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
293 if (optc1->opp_count == 4)
294 h_div = H_TIMING_DIV_BY4;
295
296 REG_UPDATE(OTG_H_TIMING_CNTL,
297 OTG_H_TIMING_DIV_MODE, h_div);
298 } else
299#endif
300 {
301 REG_UPDATE(OTG_H_TIMING_CNTL,
302 OTG_H_TIMING_DIV_BY2, h_div);
303 }
304}
305
306void optc1_set_vtg_params(struct timing_generator *optc,
307 const struct dc_crtc_timing *dc_crtc_timing)
308{
309 struct dc_crtc_timing patched_crtc_timing;
310 uint32_t asic_blank_end;
311 uint32_t v_init;
312 uint32_t v_fp2 = 0;
313 int32_t vertical_line_start;
314
315 struct optc *optc1 = DCN10TG_FROM_TG(optc);
316
317 patched_crtc_timing = *dc_crtc_timing;
318 apply_front_porch_workaround(&patched_crtc_timing);
319
320
321 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
322
323
324 asic_blank_end = v_init -
325 patched_crtc_timing.v_border_bottom -
326 patched_crtc_timing.v_addressable -
327 patched_crtc_timing.v_border_top;
328
329
330 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
331 if (vertical_line_start < 0)
332 v_fp2 = -vertical_line_start;
333
334
335 if (REG(OTG_INTERLACE_CONTROL)) {
336 if (patched_crtc_timing.flags.INTERLACE == 1) {
337 v_init = v_init / 2;
338 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
339 v_fp2 = v_fp2 / 2;
340 }
341 }
342
343 REG_UPDATE_2(CONTROL,
344 VTG0_FP2, v_fp2,
345 VTG0_VCOUNT_INIT, v_init);
346}
347
348void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
349{
350 struct optc *optc1 = DCN10TG_FROM_TG(optc);
351
352 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
353
354 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
355 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
356}
357
358
359
360
361
362
363
364
365
366void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
367{
368 struct optc *optc1 = DCN10TG_FROM_TG(optc);
369 uint32_t mode = enable ? 2 : 0;
370
371 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
372 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
373}
374
375
376
377
378
379static void optc1_unblank_crtc(struct timing_generator *optc)
380{
381 struct optc *optc1 = DCN10TG_FROM_TG(optc);
382
383 REG_UPDATE_2(OTG_BLANK_CONTROL,
384 OTG_BLANK_DATA_EN, 0,
385 OTG_BLANK_DE_MODE, 0);
386
387
388
389
390
391
392
393
394 optc1_clear_optc_underflow(optc);
395}
396
397
398
399
400
401
402static void optc1_blank_crtc(struct timing_generator *optc)
403{
404 struct optc *optc1 = DCN10TG_FROM_TG(optc);
405
406 REG_UPDATE_2(OTG_BLANK_CONTROL,
407 OTG_BLANK_DATA_EN, 1,
408 OTG_BLANK_DE_MODE, 0);
409
410 optc1_set_blank_data_double_buffer(optc, false);
411}
412
413void optc1_set_blank(struct timing_generator *optc,
414 bool enable_blanking)
415{
416 if (enable_blanking)
417 optc1_blank_crtc(optc);
418 else
419 optc1_unblank_crtc(optc);
420}
421
422bool optc1_is_blanked(struct timing_generator *optc)
423{
424 struct optc *optc1 = DCN10TG_FROM_TG(optc);
425 uint32_t blank_en;
426 uint32_t blank_state;
427
428 REG_GET_2(OTG_BLANK_CONTROL,
429 OTG_BLANK_DATA_EN, &blank_en,
430 OTG_CURRENT_BLANK_STATE, &blank_state);
431
432 return blank_en && blank_state;
433}
434
435void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
436{
437 struct optc *optc1 = DCN10TG_FROM_TG(optc);
438
439 if (enable) {
440 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
441 OPTC_INPUT_CLK_EN, 1,
442 OPTC_INPUT_CLK_GATE_DIS, 1);
443
444 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
445 OPTC_INPUT_CLK_ON, 1,
446 1, 1000);
447
448
449 REG_UPDATE_2(OTG_CLOCK_CONTROL,
450 OTG_CLOCK_EN, 1,
451 OTG_CLOCK_GATE_DIS, 1);
452 REG_WAIT(OTG_CLOCK_CONTROL,
453 OTG_CLOCK_ON, 1,
454 1, 1000);
455 } else {
456 REG_UPDATE_2(OTG_CLOCK_CONTROL,
457 OTG_CLOCK_GATE_DIS, 0,
458 OTG_CLOCK_EN, 0);
459
460 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
461 OPTC_INPUT_CLK_GATE_DIS, 0,
462 OPTC_INPUT_CLK_EN, 0);
463 }
464}
465
466
467
468
469
470static bool optc1_enable_crtc(struct timing_generator *optc)
471{
472
473
474
475
476 struct optc *optc1 = DCN10TG_FROM_TG(optc);
477
478
479
480
481 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
482 OPTC_SRC_SEL, optc->inst);
483
484
485 REG_UPDATE(CONTROL,
486 VTG0_ENABLE, 1);
487
488 REG_SEQ_START();
489
490
491 REG_UPDATE_2(OTG_CONTROL,
492 OTG_DISABLE_POINT_CNTL, 3,
493 OTG_MASTER_EN, 1);
494
495 REG_SEQ_SUBMIT();
496 REG_SEQ_WAIT_DONE();
497
498 return true;
499}
500
501
502bool optc1_disable_crtc(struct timing_generator *optc)
503{
504 struct optc *optc1 = DCN10TG_FROM_TG(optc);
505
506
507
508
509 REG_UPDATE_2(OTG_CONTROL,
510 OTG_DISABLE_POINT_CNTL, 3,
511 OTG_MASTER_EN, 0);
512
513 REG_UPDATE(CONTROL,
514 VTG0_ENABLE, 0);
515
516
517 REG_WAIT(OTG_CLOCK_CONTROL,
518 OTG_BUSY, 0,
519 1, 100000);
520
521 return true;
522}
523
524
525void optc1_program_blank_color(
526 struct timing_generator *optc,
527 const struct tg_color *black_color)
528{
529 struct optc *optc1 = DCN10TG_FROM_TG(optc);
530
531 REG_SET_3(OTG_BLACK_COLOR, 0,
532 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
533 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
534 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
535}
536
537bool optc1_validate_timing(
538 struct timing_generator *optc,
539 const struct dc_crtc_timing *timing)
540{
541 uint32_t v_blank;
542 uint32_t h_blank;
543 uint32_t min_v_blank;
544 struct optc *optc1 = DCN10TG_FROM_TG(optc);
545
546 ASSERT(timing != NULL);
547
548 v_blank = (timing->v_total - timing->v_addressable -
549 timing->v_border_top - timing->v_border_bottom);
550
551 h_blank = (timing->h_total - timing->h_addressable -
552 timing->h_border_right -
553 timing->h_border_left);
554
555 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
556 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
557 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
558 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
559 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
560 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
561 return false;
562
563
564 if (timing->flags.INTERLACE == 1)
565 return false;
566
567
568
569
570
571
572 if (timing->h_total > optc1->max_h_total ||
573 timing->v_total > optc1->max_v_total)
574 return false;
575
576
577 if (h_blank < optc1->min_h_blank)
578 return false;
579
580 if (timing->h_sync_width < optc1->min_h_sync_width ||
581 timing->v_sync_width < optc1->min_v_sync_width)
582 return false;
583
584 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
585
586 if (v_blank < min_v_blank)
587 return false;
588
589 return true;
590
591}
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
608{
609 struct optc *optc1 = DCN10TG_FROM_TG(optc);
610 uint32_t frame_count;
611
612 REG_GET(OTG_STATUS_FRAME_COUNT,
613 OTG_FRAME_COUNT, &frame_count);
614
615 return frame_count;
616}
617
618void optc1_lock(struct timing_generator *optc)
619{
620 struct optc *optc1 = DCN10TG_FROM_TG(optc);
621 uint32_t regval = 0;
622
623 regval = REG_READ(OTG_CONTROL);
624
625
626 if ((regval & 0x1) == 0x0)
627 return;
628
629 REG_SET(OTG_GLOBAL_CONTROL0, 0,
630 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
631 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
632 OTG_MASTER_UPDATE_LOCK, 1);
633
634
635 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
636
637 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
638 UPDATE_LOCK_STATUS, 1,
639 1, 10);
640 }
641}
642
643void optc1_unlock(struct timing_generator *optc)
644{
645 struct optc *optc1 = DCN10TG_FROM_TG(optc);
646
647 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
648 OTG_MASTER_UPDATE_LOCK, 0);
649}
650
651void optc1_get_position(struct timing_generator *optc,
652 struct crtc_position *position)
653{
654 struct optc *optc1 = DCN10TG_FROM_TG(optc);
655
656 REG_GET_2(OTG_STATUS_POSITION,
657 OTG_HORZ_COUNT, &position->horizontal_count,
658 OTG_VERT_COUNT, &position->vertical_count);
659
660 REG_GET(OTG_NOM_VERT_POSITION,
661 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
662}
663
664bool optc1_is_counter_moving(struct timing_generator *optc)
665{
666 struct crtc_position position1, position2;
667
668 optc->funcs->get_position(optc, &position1);
669 optc->funcs->get_position(optc, &position2);
670
671 if (position1.horizontal_count == position2.horizontal_count &&
672 position1.vertical_count == position2.vertical_count)
673 return false;
674 else
675 return true;
676}
677
678bool optc1_did_triggered_reset_occur(
679 struct timing_generator *optc)
680{
681 struct optc *optc1 = DCN10TG_FROM_TG(optc);
682 uint32_t occurred_force, occurred_vsync;
683
684 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
685 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
686
687 REG_GET(OTG_VERT_SYNC_CONTROL,
688 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
689
690 return occurred_vsync != 0 || occurred_force != 0;
691}
692
693void optc1_disable_reset_trigger(struct timing_generator *optc)
694{
695 struct optc *optc1 = DCN10TG_FROM_TG(optc);
696
697 REG_WRITE(OTG_TRIGA_CNTL, 0);
698
699 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
700 OTG_FORCE_COUNT_NOW_CLEAR, 1);
701
702 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
703 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
704}
705
706void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
707{
708 struct optc *optc1 = DCN10TG_FROM_TG(optc);
709 uint32_t falling_edge;
710
711 REG_GET(OTG_V_SYNC_A_CNTL,
712 OTG_V_SYNC_A_POL, &falling_edge);
713
714 if (falling_edge)
715 REG_SET_3(OTG_TRIGA_CNTL, 0,
716
717
718
719 OTG_TRIGA_SOURCE_SELECT, 20,
720 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
721
722 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
723 else
724 REG_SET_3(OTG_TRIGA_CNTL, 0,
725
726
727
728 OTG_TRIGA_SOURCE_SELECT, 20,
729 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
730
731 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
732
733 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
734
735
736
737 OTG_FORCE_COUNT_NOW_MODE, 2);
738}
739
740void optc1_enable_crtc_reset(
741 struct timing_generator *optc,
742 int source_tg_inst,
743 struct crtc_trigger_info *crtc_tp)
744{
745 struct optc *optc1 = DCN10TG_FROM_TG(optc);
746 uint32_t falling_edge = 0;
747 uint32_t rising_edge = 0;
748
749 switch (crtc_tp->event) {
750
751 case CRTC_EVENT_VSYNC_RISING:
752 rising_edge = 1;
753 break;
754
755 case CRTC_EVENT_VSYNC_FALLING:
756 falling_edge = 1;
757 break;
758 }
759
760 REG_SET_4(OTG_TRIGA_CNTL, 0,
761
762
763
764 OTG_TRIGA_SOURCE_SELECT, 20,
765 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
766
767 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
768 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
769
770 switch (crtc_tp->delay) {
771 case TRIGGER_DELAY_NEXT_LINE:
772 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
773 OTG_AUTO_FORCE_VSYNC_MODE, 1);
774 break;
775 case TRIGGER_DELAY_NEXT_PIXEL:
776 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
777
778
779
780 OTG_FORCE_COUNT_NOW_MODE, 2);
781 break;
782 }
783}
784
785void optc1_wait_for_state(struct timing_generator *optc,
786 enum crtc_state state)
787{
788 struct optc *optc1 = DCN10TG_FROM_TG(optc);
789
790 switch (state) {
791 case CRTC_STATE_VBLANK:
792 REG_WAIT(OTG_STATUS,
793 OTG_V_BLANK, 1,
794 1, 100000);
795 break;
796
797 case CRTC_STATE_VACTIVE:
798 REG_WAIT(OTG_STATUS,
799 OTG_V_ACTIVE_DISP, 1,
800 1, 100000);
801 break;
802
803 default:
804 break;
805 }
806}
807
808void optc1_set_early_control(
809 struct timing_generator *optc,
810 uint32_t early_cntl)
811{
812
813
814
815}
816
817
818void optc1_set_static_screen_control(
819 struct timing_generator *optc,
820 uint32_t event_triggers,
821 uint32_t num_frames)
822{
823 struct optc *optc1 = DCN10TG_FROM_TG(optc);
824
825
826 if (num_frames > 0xFF)
827 num_frames = 0xFF;
828
829
830
831
832 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
833 != 0)
834 event_triggers = event_triggers &
835 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
836
837 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
838 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
839 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
840}
841
842void optc1_setup_manual_trigger(struct timing_generator *optc)
843{
844 struct optc *optc1 = DCN10TG_FROM_TG(optc);
845
846 REG_SET(OTG_GLOBAL_CONTROL2, 0,
847 MANUAL_FLOW_CONTROL_SEL, optc->inst);
848
849 REG_SET_8(OTG_TRIGA_CNTL, 0,
850 OTG_TRIGA_SOURCE_SELECT, 22,
851 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
852 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
853 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
854 OTG_TRIGA_POLARITY_SELECT, 0,
855 OTG_TRIGA_FREQUENCY_SELECT, 0,
856 OTG_TRIGA_DELAY, 0,
857 OTG_TRIGA_CLEAR, 1);
858}
859
860void optc1_program_manual_trigger(struct timing_generator *optc)
861{
862 struct optc *optc1 = DCN10TG_FROM_TG(optc);
863
864 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
865 MANUAL_FLOW_CONTROL, 1);
866
867 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
868 MANUAL_FLOW_CONTROL, 0);
869}
870
871
872
873
874
875
876
877
878
879
880
881void optc1_set_drr(
882 struct timing_generator *optc,
883 const struct drr_params *params)
884{
885 struct optc *optc1 = DCN10TG_FROM_TG(optc);
886
887 if (params != NULL &&
888 params->vertical_total_max > 0 &&
889 params->vertical_total_min > 0) {
890
891 if (params->vertical_total_mid != 0) {
892
893 REG_SET(OTG_V_TOTAL_MID, 0,
894 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
895
896 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
897 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
898 OTG_VTOTAL_MID_FRAME_NUM,
899 (uint8_t)params->vertical_total_mid_frame_num);
900
901 }
902
903 REG_SET(OTG_V_TOTAL_MAX, 0,
904 OTG_V_TOTAL_MAX, params->vertical_total_max - 1);
905
906 REG_SET(OTG_V_TOTAL_MIN, 0,
907 OTG_V_TOTAL_MIN, params->vertical_total_min - 1);
908
909 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
910 OTG_V_TOTAL_MIN_SEL, 1,
911 OTG_V_TOTAL_MAX_SEL, 1,
912 OTG_FORCE_LOCK_ON_EVENT, 0,
913 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
914 OTG_SET_V_TOTAL_MIN_MASK, 0);
915
916
917 optc->funcs->setup_manual_trigger(optc);
918
919 } else {
920 REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
921 OTG_SET_V_TOTAL_MIN_MASK, 0,
922 OTG_V_TOTAL_MIN_SEL, 0,
923 OTG_V_TOTAL_MAX_SEL, 0,
924 OTG_FORCE_LOCK_ON_EVENT, 0);
925
926 REG_SET(OTG_V_TOTAL_MIN, 0,
927 OTG_V_TOTAL_MIN, 0);
928
929 REG_SET(OTG_V_TOTAL_MAX, 0,
930 OTG_V_TOTAL_MAX, 0);
931 }
932}
933
934static void optc1_set_test_pattern(
935 struct timing_generator *optc,
936
937
938
939 enum controller_dp_test_pattern test_pattern,
940 enum dc_color_depth color_depth)
941{
942 struct optc *optc1 = DCN10TG_FROM_TG(optc);
943 enum test_pattern_color_format bit_depth;
944 enum test_pattern_dyn_range dyn_range;
945 enum test_pattern_mode mode;
946 uint32_t pattern_mask;
947 uint32_t pattern_data;
948
949 uint32_t src_bpc = 16;
950
951 uint32_t dst_bpc;
952 uint32_t index;
953
954
955
956
957
958 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
959 0x0000, 0x0000};
960
961 uint16_t dst_color[6];
962 uint32_t inc_base;
963
964
965 switch (color_depth) {
966 case COLOR_DEPTH_666:
967 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
968 break;
969 case COLOR_DEPTH_888:
970 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
971 break;
972 case COLOR_DEPTH_101010:
973 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
974 break;
975 case COLOR_DEPTH_121212:
976 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
977 break;
978 default:
979 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
980 break;
981 }
982
983 switch (test_pattern) {
984 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
985 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
986 {
987 dyn_range = (test_pattern ==
988 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
989 TEST_PATTERN_DYN_RANGE_CEA :
990 TEST_PATTERN_DYN_RANGE_VESA);
991 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
992
993 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
994 OTG_TEST_PATTERN_VRES, 6,
995 OTG_TEST_PATTERN_HRES, 6);
996
997 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
998 OTG_TEST_PATTERN_EN, 1,
999 OTG_TEST_PATTERN_MODE, mode,
1000 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1001 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1002 }
1003 break;
1004
1005 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1006 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1007 {
1008 mode = (test_pattern ==
1009 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1010 TEST_PATTERN_MODE_VERTICALBARS :
1011 TEST_PATTERN_MODE_HORIZONTALBARS);
1012
1013 switch (bit_depth) {
1014 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1015 dst_bpc = 6;
1016 break;
1017 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1018 dst_bpc = 8;
1019 break;
1020 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1021 dst_bpc = 10;
1022 break;
1023 default:
1024 dst_bpc = 8;
1025 break;
1026 }
1027
1028
1029 for (index = 0; index < 6; index++) {
1030
1031
1032
1033 dst_color[index] =
1034 src_color[index] >> (src_bpc - dst_bpc);
1035
1036
1037
1038
1039
1040
1041 dst_color[index] <<= (16 - dst_bpc);
1042 }
1043
1044 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072 pattern_data = 0;
1073 for (index = 0; index < 6; index++) {
1074
1075
1076
1077 pattern_mask = (1 << index);
1078
1079
1080 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1081 OTG_TEST_PATTERN_MASK, pattern_mask,
1082 OTG_TEST_PATTERN_DATA, pattern_data);
1083
1084
1085
1086
1087 pattern_data = dst_color[index];
1088 }
1089
1090
1091
1092 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1093 OTG_TEST_PATTERN_MASK, pattern_mask,
1094 OTG_TEST_PATTERN_DATA, pattern_data);
1095
1096
1097 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1098 OTG_TEST_PATTERN_EN, 1,
1099 OTG_TEST_PATTERN_MODE, mode,
1100 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1101 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1102 }
1103 break;
1104
1105 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1106 {
1107 mode = (bit_depth ==
1108 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1109 TEST_PATTERN_MODE_DUALRAMP_RGB :
1110 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1111
1112 switch (bit_depth) {
1113 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1114 dst_bpc = 6;
1115 break;
1116 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1117 dst_bpc = 8;
1118 break;
1119 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1120 dst_bpc = 10;
1121 break;
1122 default:
1123 dst_bpc = 8;
1124 break;
1125 }
1126
1127
1128
1129
1130
1131 inc_base = (src_bpc - dst_bpc);
1132
1133 switch (bit_depth) {
1134 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1135 {
1136 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1137 OTG_TEST_PATTERN_INC0, inc_base,
1138 OTG_TEST_PATTERN_INC1, 0,
1139 OTG_TEST_PATTERN_HRES, 6,
1140 OTG_TEST_PATTERN_VRES, 6,
1141 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1142 }
1143 break;
1144 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1145 {
1146 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1147 OTG_TEST_PATTERN_INC0, inc_base,
1148 OTG_TEST_PATTERN_INC1, 0,
1149 OTG_TEST_PATTERN_HRES, 8,
1150 OTG_TEST_PATTERN_VRES, 6,
1151 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1152 }
1153 break;
1154 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1155 {
1156 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1157 OTG_TEST_PATTERN_INC0, inc_base,
1158 OTG_TEST_PATTERN_INC1, inc_base + 2,
1159 OTG_TEST_PATTERN_HRES, 8,
1160 OTG_TEST_PATTERN_VRES, 5,
1161 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1162 }
1163 break;
1164 default:
1165 break;
1166 }
1167
1168 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1169
1170
1171 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1172
1173 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1174 OTG_TEST_PATTERN_EN, 1,
1175 OTG_TEST_PATTERN_MODE, mode,
1176 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1177 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1178 }
1179 break;
1180 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1181 {
1182 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1183 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1184 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1185 }
1186 break;
1187 default:
1188 break;
1189
1190 }
1191}
1192
1193void optc1_get_crtc_scanoutpos(
1194 struct timing_generator *optc,
1195 uint32_t *v_blank_start,
1196 uint32_t *v_blank_end,
1197 uint32_t *h_position,
1198 uint32_t *v_position)
1199{
1200 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1201 struct crtc_position position;
1202
1203 REG_GET_2(OTG_V_BLANK_START_END,
1204 OTG_V_BLANK_START, v_blank_start,
1205 OTG_V_BLANK_END, v_blank_end);
1206
1207 optc1_get_position(optc, &position);
1208
1209 *h_position = position.horizontal_count;
1210 *v_position = position.vertical_count;
1211}
1212
1213static void optc1_enable_stereo(struct timing_generator *optc,
1214 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1215{
1216 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1217
1218 if (flags) {
1219 uint32_t stereo_en;
1220 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1221
1222 if (flags->PROGRAM_STEREO)
1223 REG_UPDATE_3(OTG_STEREO_CONTROL,
1224 OTG_STEREO_EN, stereo_en,
1225 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1226 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1227
1228 if (flags->PROGRAM_POLARITY)
1229 REG_UPDATE(OTG_STEREO_CONTROL,
1230 OTG_STEREO_EYE_FLAG_POLARITY,
1231 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1232
1233 if (flags->DISABLE_STEREO_DP_SYNC)
1234 REG_UPDATE(OTG_STEREO_CONTROL,
1235 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1236
1237 if (flags->PROGRAM_STEREO)
1238 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1239 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1240 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1241
1242 }
1243}
1244
1245void optc1_program_stereo(struct timing_generator *optc,
1246 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1247{
1248 if (flags->PROGRAM_STEREO)
1249 optc1_enable_stereo(optc, timing, flags);
1250 else
1251 optc1_disable_stereo(optc);
1252}
1253
1254
1255bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1256{
1257 bool ret = false;
1258 uint32_t left_eye = 0;
1259 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1260
1261 REG_GET(OTG_STEREO_STATUS,
1262 OTG_STEREO_CURRENT_EYE, &left_eye);
1263 if (left_eye == 1)
1264 ret = true;
1265 else
1266 ret = false;
1267
1268 return ret;
1269}
1270
1271bool optc1_get_hw_timing(struct timing_generator *tg,
1272 struct dc_crtc_timing *hw_crtc_timing)
1273{
1274 struct dcn_otg_state s = {0};
1275
1276 if (tg == NULL || hw_crtc_timing == NULL)
1277 return false;
1278
1279 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1280
1281 hw_crtc_timing->h_total = s.h_total + 1;
1282 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1283 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1284 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1285
1286 hw_crtc_timing->v_total = s.v_total + 1;
1287 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1288 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1289 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1290
1291 return true;
1292}
1293
1294
1295void optc1_read_otg_state(struct optc *optc1,
1296 struct dcn_otg_state *s)
1297{
1298 REG_GET(OTG_CONTROL,
1299 OTG_MASTER_EN, &s->otg_enabled);
1300
1301 REG_GET_2(OTG_V_BLANK_START_END,
1302 OTG_V_BLANK_START, &s->v_blank_start,
1303 OTG_V_BLANK_END, &s->v_blank_end);
1304
1305 REG_GET(OTG_V_SYNC_A_CNTL,
1306 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1307
1308 REG_GET(OTG_V_TOTAL,
1309 OTG_V_TOTAL, &s->v_total);
1310
1311 REG_GET(OTG_V_TOTAL_MAX,
1312 OTG_V_TOTAL_MAX, &s->v_total_max);
1313
1314 REG_GET(OTG_V_TOTAL_MIN,
1315 OTG_V_TOTAL_MIN, &s->v_total_min);
1316
1317 REG_GET(OTG_V_TOTAL_CONTROL,
1318 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1319
1320 REG_GET(OTG_V_TOTAL_CONTROL,
1321 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1322
1323 REG_GET_2(OTG_V_SYNC_A,
1324 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1325 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1326
1327 REG_GET_2(OTG_H_BLANK_START_END,
1328 OTG_H_BLANK_START, &s->h_blank_start,
1329 OTG_H_BLANK_END, &s->h_blank_end);
1330
1331 REG_GET_2(OTG_H_SYNC_A,
1332 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1333 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1334
1335 REG_GET(OTG_H_SYNC_A_CNTL,
1336 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1337
1338 REG_GET(OTG_H_TOTAL,
1339 OTG_H_TOTAL, &s->h_total);
1340
1341 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1342 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1343}
1344
1345bool optc1_get_otg_active_size(struct timing_generator *optc,
1346 uint32_t *otg_active_width,
1347 uint32_t *otg_active_height)
1348{
1349 uint32_t otg_enabled;
1350 uint32_t v_blank_start;
1351 uint32_t v_blank_end;
1352 uint32_t h_blank_start;
1353 uint32_t h_blank_end;
1354 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1355
1356
1357 REG_GET(OTG_CONTROL,
1358 OTG_MASTER_EN, &otg_enabled);
1359
1360 if (otg_enabled == 0)
1361 return false;
1362
1363 REG_GET_2(OTG_V_BLANK_START_END,
1364 OTG_V_BLANK_START, &v_blank_start,
1365 OTG_V_BLANK_END, &v_blank_end);
1366
1367 REG_GET_2(OTG_H_BLANK_START_END,
1368 OTG_H_BLANK_START, &h_blank_start,
1369 OTG_H_BLANK_END, &h_blank_end);
1370
1371 *otg_active_width = v_blank_start - v_blank_end;
1372 *otg_active_height = h_blank_start - h_blank_end;
1373 return true;
1374}
1375
1376void optc1_clear_optc_underflow(struct timing_generator *optc)
1377{
1378 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1379
1380 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1381}
1382
1383void optc1_tg_init(struct timing_generator *optc)
1384{
1385 optc1_set_blank_data_double_buffer(optc, true);
1386 optc1_set_timing_double_buffer(optc, true);
1387 optc1_clear_optc_underflow(optc);
1388}
1389
1390bool optc1_is_tg_enabled(struct timing_generator *optc)
1391{
1392 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1393 uint32_t otg_enabled = 0;
1394
1395 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1396
1397 return (otg_enabled != 0);
1398
1399}
1400
1401bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1402{
1403 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1404 uint32_t underflow_occurred = 0;
1405
1406 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1407 OPTC_UNDERFLOW_OCCURRED_STATUS,
1408 &underflow_occurred);
1409
1410 return (underflow_occurred == 1);
1411}
1412
1413bool optc1_configure_crc(struct timing_generator *optc,
1414 const struct crc_params *params)
1415{
1416 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1417
1418
1419 if (!optc1_is_tg_enabled(optc))
1420 return false;
1421
1422 REG_WRITE(OTG_CRC_CNTL, 0);
1423
1424 if (!params->enable)
1425 return true;
1426
1427
1428
1429 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1430 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1431 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1432
1433
1434 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1435 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1436 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1437
1438
1439 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1440 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1441 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1442
1443
1444 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1445 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1446 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1447
1448
1449 REG_UPDATE_3(OTG_CRC_CNTL,
1450 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1451 OTG_CRC0_SELECT, params->selection,
1452 OTG_CRC_EN, 1);
1453
1454 return true;
1455}
1456
1457bool optc1_get_crc(struct timing_generator *optc,
1458 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1459{
1460 uint32_t field = 0;
1461 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1462
1463 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1464
1465
1466 if (!field)
1467 return false;
1468
1469 REG_GET_2(OTG_CRC0_DATA_RG,
1470 CRC0_R_CR, r_cr,
1471 CRC0_G_Y, g_y);
1472
1473 REG_GET(OTG_CRC0_DATA_B,
1474 CRC0_B_CB, b_cb);
1475
1476 return true;
1477}
1478
1479static const struct timing_generator_funcs dcn10_tg_funcs = {
1480 .validate_timing = optc1_validate_timing,
1481 .program_timing = optc1_program_timing,
1482 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1483 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1484 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1485 .program_global_sync = optc1_program_global_sync,
1486 .enable_crtc = optc1_enable_crtc,
1487 .disable_crtc = optc1_disable_crtc,
1488
1489 .is_counter_moving = optc1_is_counter_moving,
1490 .get_position = optc1_get_position,
1491 .get_frame_count = optc1_get_vblank_counter,
1492 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1493 .get_otg_active_size = optc1_get_otg_active_size,
1494 .set_early_control = optc1_set_early_control,
1495
1496 .wait_for_state = optc1_wait_for_state,
1497 .set_blank = optc1_set_blank,
1498 .is_blanked = optc1_is_blanked,
1499 .set_blank_color = optc1_program_blank_color,
1500 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1501 .enable_reset_trigger = optc1_enable_reset_trigger,
1502 .enable_crtc_reset = optc1_enable_crtc_reset,
1503 .disable_reset_trigger = optc1_disable_reset_trigger,
1504 .lock = optc1_lock,
1505 .unlock = optc1_unlock,
1506 .enable_optc_clock = optc1_enable_optc_clock,
1507 .set_drr = optc1_set_drr,
1508 .set_static_screen_control = optc1_set_static_screen_control,
1509 .set_test_pattern = optc1_set_test_pattern,
1510 .program_stereo = optc1_program_stereo,
1511 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1512 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1513 .tg_init = optc1_tg_init,
1514 .is_tg_enabled = optc1_is_tg_enabled,
1515 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1516 .clear_optc_underflow = optc1_clear_optc_underflow,
1517 .get_crc = optc1_get_crc,
1518 .configure_crc = optc1_configure_crc,
1519 .set_vtg_params = optc1_set_vtg_params,
1520 .program_manual_trigger = optc1_program_manual_trigger,
1521 .setup_manual_trigger = optc1_setup_manual_trigger,
1522 .get_hw_timing = optc1_get_hw_timing,
1523};
1524
1525void dcn10_timing_generator_init(struct optc *optc1)
1526{
1527 optc1->base.funcs = &dcn10_tg_funcs;
1528
1529 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1530 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1531
1532 optc1->min_h_blank = 32;
1533 optc1->min_v_blank = 3;
1534 optc1->min_v_blank_interlace = 5;
1535 optc1->min_h_sync_width = 8;
1536 optc1->min_v_sync_width = 1;
1537}
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
1552{
1553 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1554
1555 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1556 && !timing->dsc_cfg.ycbcr422_simple);
1557 return two_pix;
1558}
1559
1560