linux/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
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   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef SMU11_DRIVER_IF_H
  25#define SMU11_DRIVER_IF_H
  26
  27// *** IMPORTANT ***
  28// SMU TEAM: Always increment the interface version if
  29// any structure is changed in this file
  30// Be aware of that the version should be updated in
  31// smu_v11_0.h, rename is also needed.
  32// #define SMU11_DRIVER_IF_VERSION 0x13
  33
  34#define PPTABLE_V20_SMU_VERSION 3
  35
  36#define NUM_GFXCLK_DPM_LEVELS  16
  37#define NUM_VCLK_DPM_LEVELS    8
  38#define NUM_DCLK_DPM_LEVELS    8
  39#define NUM_ECLK_DPM_LEVELS    8
  40#define NUM_MP0CLK_DPM_LEVELS  2
  41#define NUM_SOCCLK_DPM_LEVELS  8
  42#define NUM_UCLK_DPM_LEVELS    4
  43#define NUM_FCLK_DPM_LEVELS    8
  44#define NUM_DCEFCLK_DPM_LEVELS 8
  45#define NUM_DISPCLK_DPM_LEVELS 8
  46#define NUM_PIXCLK_DPM_LEVELS  8
  47#define NUM_PHYCLK_DPM_LEVELS  8
  48#define NUM_LINK_LEVELS        2
  49#define NUM_XGMI_LEVELS        2
  50
  51#define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
  52#define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
  53#define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
  54#define MAX_ECLK_DPM_LEVEL    (NUM_ECLK_DPM_LEVELS    - 1)
  55#define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
  56#define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
  57#define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
  58#define MAX_FCLK_DPM_LEVEL    (NUM_FCLK_DPM_LEVELS    - 1)
  59#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
  60#define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
  61#define MAX_PIXCLK_DPM_LEVEL  (NUM_PIXCLK_DPM_LEVELS  - 1)
  62#define MAX_PHYCLK_DPM_LEVEL  (NUM_PHYCLK_DPM_LEVELS  - 1)
  63#define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
  64#define MAX_XGMI_LEVEL        (NUM_XGMI_LEVELS        - 1)
  65
  66#define PPSMC_GeminiModeNone   0
  67#define PPSMC_GeminiModeMaster 1
  68#define PPSMC_GeminiModeSlave  2
  69
  70
  71#define FEATURE_DPM_PREFETCHER_BIT      0
  72#define FEATURE_DPM_GFXCLK_BIT          1
  73#define FEATURE_DPM_UCLK_BIT            2
  74#define FEATURE_DPM_SOCCLK_BIT          3
  75#define FEATURE_DPM_UVD_BIT             4
  76#define FEATURE_DPM_VCE_BIT             5
  77#define FEATURE_ULV_BIT                 6
  78#define FEATURE_DPM_MP0CLK_BIT          7
  79#define FEATURE_DPM_LINK_BIT            8
  80#define FEATURE_DPM_DCEFCLK_BIT         9
  81#define FEATURE_DS_GFXCLK_BIT           10
  82#define FEATURE_DS_SOCCLK_BIT           11
  83#define FEATURE_DS_LCLK_BIT             12
  84#define FEATURE_PPT_BIT                 13
  85#define FEATURE_TDC_BIT                 14
  86#define FEATURE_THERMAL_BIT             15
  87#define FEATURE_GFX_PER_CU_CG_BIT       16
  88#define FEATURE_RM_BIT                  17
  89#define FEATURE_DS_DCEFCLK_BIT          18
  90#define FEATURE_ACDC_BIT                19
  91#define FEATURE_VR0HOT_BIT              20
  92#define FEATURE_VR1HOT_BIT              21
  93#define FEATURE_FW_CTF_BIT              22
  94#define FEATURE_LED_DISPLAY_BIT         23
  95#define FEATURE_FAN_CONTROL_BIT         24
  96#define FEATURE_GFX_EDC_BIT             25
  97#define FEATURE_GFXOFF_BIT              26
  98#define FEATURE_CG_BIT                  27
  99#define FEATURE_DPM_FCLK_BIT            28
 100#define FEATURE_DS_FCLK_BIT             29
 101#define FEATURE_DS_MP1CLK_BIT           30
 102#define FEATURE_DS_MP0CLK_BIT           31
 103#define FEATURE_XGMI_BIT                32
 104#define FEATURE_ECC_BIT                 33
 105#define FEATURE_SPARE_34_BIT            34
 106#define FEATURE_SPARE_35_BIT            35
 107#define FEATURE_SPARE_36_BIT            36
 108#define FEATURE_SPARE_37_BIT            37
 109#define FEATURE_SPARE_38_BIT            38
 110#define FEATURE_SPARE_39_BIT            39
 111#define FEATURE_SPARE_40_BIT            40
 112#define FEATURE_SPARE_41_BIT            41
 113#define FEATURE_SPARE_42_BIT            42
 114#define FEATURE_SPARE_43_BIT            43
 115#define FEATURE_SPARE_44_BIT            44
 116#define FEATURE_SPARE_45_BIT            45
 117#define FEATURE_SPARE_46_BIT            46
 118#define FEATURE_SPARE_47_BIT            47
 119#define FEATURE_SPARE_48_BIT            48
 120#define FEATURE_SPARE_49_BIT            49
 121#define FEATURE_SPARE_50_BIT            50
 122#define FEATURE_SPARE_51_BIT            51
 123#define FEATURE_SPARE_52_BIT            52
 124#define FEATURE_SPARE_53_BIT            53
 125#define FEATURE_SPARE_54_BIT            54
 126#define FEATURE_SPARE_55_BIT            55
 127#define FEATURE_SPARE_56_BIT            56
 128#define FEATURE_SPARE_57_BIT            57
 129#define FEATURE_SPARE_58_BIT            58
 130#define FEATURE_SPARE_59_BIT            59
 131#define FEATURE_SPARE_60_BIT            60
 132#define FEATURE_SPARE_61_BIT            61
 133#define FEATURE_SPARE_62_BIT            62
 134#define FEATURE_SPARE_63_BIT            63
 135
 136#define NUM_FEATURES                    64
 137
 138#define FEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
 139#define FEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
 140#define FEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
 141#define FEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
 142#define FEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
 143#define FEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
 144#define FEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
 145#define FEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
 146#define FEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
 147#define FEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
 148#define FEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
 149#define FEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
 150#define FEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
 151#define FEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
 152#define FEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
 153#define FEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
 154#define FEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
 155#define FEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
 156#define FEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
 157#define FEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
 158#define FEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
 159#define FEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
 160#define FEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
 161#define FEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
 162#define FEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
 163#define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
 164#define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
 165#define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
 166#define FEATURE_DPM_FCLK_MASK           (1 << FEATURE_DPM_FCLK_BIT           )
 167#define FEATURE_DS_FCLK_MASK            (1 << FEATURE_DS_FCLK_BIT            )
 168#define FEATURE_DS_MP1CLK_MASK          (1 << FEATURE_DS_MP1CLK_BIT          )
 169#define FEATURE_DS_MP0CLK_MASK          (1 << FEATURE_DS_MP0CLK_BIT          )
 170#define FEATURE_XGMI_MASK               (1ULL << FEATURE_XGMI_BIT               )
 171#define FEATURE_ECC_MASK                (1ULL << FEATURE_ECC_BIT                )
 172
 173#define DPM_OVERRIDE_DISABLE_SOCCLK_PID             0x00000001
 174#define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000002
 175#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK    0x00000004
 176#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK      0x00000008
 177#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK   0x00000010
 178#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK     0x00000020
 179#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK   0x00000040
 180#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK     0x00000080
 181#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK    0x00000100
 182#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK      0x00000200
 183#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK   0x00000400
 184#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK     0x00000800
 185#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
 186#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK   0x00002000
 187#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH    0x00004000
 188#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH    0x00008000
 189#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH      0x00010000
 190#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH      0x00020000
 191
 192#define I2C_CONTROLLER_ENABLED     1
 193#define I2C_CONTROLLER_DISABLED    0
 194
 195#define VR_MAPPING_VR_SELECT_MASK  0x01
 196#define VR_MAPPING_VR_SELECT_SHIFT 0x00
 197
 198#define VR_MAPPING_PLANE_SELECT_MASK  0x02
 199#define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
 200
 201
 202#define PSI_SEL_VR0_PLANE0_PSI0  0x01
 203#define PSI_SEL_VR0_PLANE0_PSI1  0x02
 204#define PSI_SEL_VR0_PLANE1_PSI0  0x04
 205#define PSI_SEL_VR0_PLANE1_PSI1  0x08
 206#define PSI_SEL_VR1_PLANE0_PSI0  0x10
 207#define PSI_SEL_VR1_PLANE0_PSI1  0x20
 208#define PSI_SEL_VR1_PLANE1_PSI0  0x40
 209#define PSI_SEL_VR1_PLANE1_PSI1  0x80
 210
 211
 212#define THROTTLER_STATUS_PADDING_BIT      0
 213#define THROTTLER_STATUS_TEMP_EDGE_BIT    1
 214#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
 215#define THROTTLER_STATUS_TEMP_HBM_BIT     3
 216#define THROTTLER_STATUS_TEMP_VR_GFX_BIT  4
 217#define THROTTLER_STATUS_TEMP_VR_SOC_BIT  5
 218#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
 219#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
 220#define THROTTLER_STATUS_TEMP_LIQUID_BIT  8
 221#define THROTTLER_STATUS_TEMP_PLX_BIT     9
 222#define THROTTLER_STATUS_TEMP_SKIN_BIT    10
 223#define THROTTLER_STATUS_TDC_GFX_BIT      11
 224#define THROTTLER_STATUS_TDC_SOC_BIT      12
 225#define THROTTLER_STATUS_PPT_BIT          13
 226#define THROTTLER_STATUS_FIT_BIT          14
 227#define THROTTLER_STATUS_PPM_BIT          15
 228
 229
 230#define TABLE_TRANSFER_OK         0x0
 231#define TABLE_TRANSFER_FAILED     0xFF
 232
 233
 234#define WORKLOAD_DEFAULT_BIT              0
 235#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
 236#define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
 237#define WORKLOAD_PPLIB_VIDEO_BIT          3
 238#define WORKLOAD_PPLIB_VR_BIT             4
 239#define WORKLOAD_PPLIB_COMPUTE_BIT        5
 240#define WORKLOAD_PPLIB_CUSTOM_BIT         6
 241#define WORKLOAD_PPLIB_COUNT              7
 242
 243
 244#define XGMI_STATE_D0 1
 245#define XGMI_STATE_D3 0
 246
 247typedef enum {
 248  I2C_CONTROLLER_PORT_0 = 0,
 249  I2C_CONTROLLER_PORT_1 = 1,
 250} I2cControllerPort_e;
 251
 252typedef enum {
 253  I2C_CONTROLLER_NAME_VR_GFX = 0,
 254  I2C_CONTROLLER_NAME_VR_SOC,
 255  I2C_CONTROLLER_NAME_VR_VDDCI,
 256  I2C_CONTROLLER_NAME_VR_HBM,
 257  I2C_CONTROLLER_NAME_LIQUID_0,
 258  I2C_CONTROLLER_NAME_LIQUID_1,
 259  I2C_CONTROLLER_NAME_PLX,
 260  I2C_CONTROLLER_NAME_COUNT,
 261} I2cControllerName_e;
 262
 263typedef enum {
 264  I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
 265  I2C_CONTROLLER_THROTTLER_VR_GFX,
 266  I2C_CONTROLLER_THROTTLER_VR_SOC,
 267  I2C_CONTROLLER_THROTTLER_VR_VDDCI,
 268  I2C_CONTROLLER_THROTTLER_VR_HBM,
 269  I2C_CONTROLLER_THROTTLER_LIQUID_0,
 270  I2C_CONTROLLER_THROTTLER_LIQUID_1,
 271  I2C_CONTROLLER_THROTTLER_PLX,
 272} I2cControllerThrottler_e;
 273
 274typedef enum {
 275  I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
 276  I2C_CONTROLLER_PROTOCOL_VR_IR35217,
 277  I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
 278  I2C_CONTROLLER_PROTOCOL_SPARE_0,
 279  I2C_CONTROLLER_PROTOCOL_SPARE_1,
 280  I2C_CONTROLLER_PROTOCOL_SPARE_2,
 281} I2cControllerProtocol_e;
 282
 283typedef enum {
 284  I2C_CONTROLLER_SPEED_SLOW = 0,
 285  I2C_CONTROLLER_SPEED_FAST = 1,
 286} I2cControllerSpeed_e;
 287
 288typedef struct {
 289  uint32_t Enabled;
 290  uint32_t SlaveAddress;
 291  uint32_t ControllerPort;
 292  uint32_t ControllerName;
 293
 294  uint32_t ThermalThrottler;
 295  uint32_t I2cProtocol;
 296  uint32_t I2cSpeed;
 297} I2cControllerConfig_t;
 298
 299typedef struct {
 300  uint32_t a;
 301  uint32_t b;
 302  uint32_t c;
 303} QuadraticInt_t;
 304
 305typedef struct {
 306  uint32_t m;
 307  uint32_t b;
 308} LinearInt_t;
 309
 310typedef struct {
 311  uint32_t a;
 312  uint32_t b;
 313  uint32_t c;
 314} DroopInt_t;
 315
 316typedef enum {
 317  PPCLK_GFXCLK,
 318  PPCLK_VCLK,
 319  PPCLK_DCLK,
 320  PPCLK_ECLK,
 321  PPCLK_SOCCLK,
 322  PPCLK_UCLK,
 323  PPCLK_DCEFCLK,
 324  PPCLK_DISPCLK,
 325  PPCLK_PIXCLK,
 326  PPCLK_PHYCLK,
 327  PPCLK_FCLK,
 328  PPCLK_COUNT,
 329} PPCLK_e;
 330
 331typedef enum {
 332  POWER_SOURCE_AC,
 333  POWER_SOURCE_DC,
 334  POWER_SOURCE_COUNT,
 335} POWER_SOURCE_e;
 336
 337typedef enum {
 338  VOLTAGE_MODE_AVFS = 0,
 339  VOLTAGE_MODE_AVFS_SS,
 340  VOLTAGE_MODE_SS,
 341  VOLTAGE_MODE_COUNT,
 342} VOLTAGE_MODE_e;
 343
 344
 345typedef enum {
 346  AVFS_VOLTAGE_GFX = 0,
 347  AVFS_VOLTAGE_SOC,
 348  AVFS_VOLTAGE_COUNT,
 349} AVFS_VOLTAGE_TYPE_e;
 350
 351
 352typedef struct {
 353  uint8_t        VoltageMode;
 354  uint8_t        SnapToDiscrete;
 355  uint8_t        NumDiscreteLevels;
 356  uint8_t        padding;
 357  LinearInt_t    ConversionToAvfsClk;
 358  QuadraticInt_t SsCurve;
 359} DpmDescriptor_t;
 360
 361typedef struct {
 362  uint32_t Version;
 363
 364
 365  uint32_t FeaturesToRun[2];
 366
 367
 368  uint16_t SocketPowerLimitAc0;
 369  uint16_t SocketPowerLimitAc0Tau;
 370  uint16_t SocketPowerLimitAc1;
 371  uint16_t SocketPowerLimitAc1Tau;
 372  uint16_t SocketPowerLimitAc2;
 373  uint16_t SocketPowerLimitAc2Tau;
 374  uint16_t SocketPowerLimitAc3;
 375  uint16_t SocketPowerLimitAc3Tau;
 376  uint16_t SocketPowerLimitDc;
 377  uint16_t SocketPowerLimitDcTau;
 378  uint16_t TdcLimitSoc;
 379  uint16_t TdcLimitSocTau;
 380  uint16_t TdcLimitGfx;
 381  uint16_t TdcLimitGfxTau;
 382
 383  uint16_t TedgeLimit;
 384  uint16_t ThotspotLimit;
 385  uint16_t ThbmLimit;
 386  uint16_t Tvr_gfxLimit;
 387  uint16_t Tvr_memLimit;
 388  uint16_t Tliquid1Limit;
 389  uint16_t Tliquid2Limit;
 390  uint16_t TplxLimit;
 391  uint32_t FitLimit;
 392
 393  uint16_t PpmPowerLimit;
 394  uint16_t PpmTemperatureThreshold;
 395
 396  uint8_t  MemoryOnPackage;
 397  uint8_t  padding8_limits;
 398  uint16_t Tvr_SocLimit;
 399
 400  uint16_t  UlvVoltageOffsetSoc;
 401  uint16_t  UlvVoltageOffsetGfx;
 402
 403  uint8_t  UlvSmnclkDid;
 404  uint8_t  UlvMp1clkDid;
 405  uint8_t  UlvGfxclkBypass;
 406  uint8_t  Padding234;
 407
 408
 409  uint16_t     MinVoltageGfx;
 410  uint16_t     MinVoltageSoc;
 411  uint16_t     MaxVoltageGfx;
 412  uint16_t     MaxVoltageSoc;
 413
 414  uint16_t     LoadLineResistanceGfx;
 415  uint16_t     LoadLineResistanceSoc;
 416
 417  DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
 418
 419  uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];
 420  uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];
 421  uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];
 422  uint16_t       FreqTableEclk     [NUM_ECLK_DPM_LEVELS    ];
 423  uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];
 424  uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];
 425  uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];
 426  uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];
 427  uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];
 428  uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];
 429  uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];
 430
 431  uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];
 432  uint16_t       Padding8_Clks;
 433
 434  uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];
 435  uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];
 436
 437
 438  uint16_t        GfxclkFidle;
 439  uint16_t        GfxclkSlewRate;
 440  uint16_t        CksEnableFreq;
 441  uint16_t        Padding789;
 442  QuadraticInt_t  CksVoltageOffset;
 443  uint8_t         Padding567[4];
 444  uint16_t        GfxclkDsMaxFreq;
 445  uint8_t         GfxclkSource;
 446  uint8_t         Padding456;
 447
 448  uint8_t      LowestUclkReservedForUlv;
 449  uint8_t      Padding8_Uclk[3];
 450
 451
 452  uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
 453  uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
 454  uint16_t     LclkFreq[NUM_LINK_LEVELS];
 455
 456
 457  uint16_t     EnableTdpm;
 458  uint16_t     TdpmHighHystTemperature;
 459  uint16_t     TdpmLowHystTemperature;
 460  uint16_t     GfxclkFreqHighTempLimit;
 461
 462
 463  uint16_t     FanStopTemp;
 464  uint16_t     FanStartTemp;
 465
 466  uint16_t     FanGainEdge;
 467  uint16_t     FanGainHotspot;
 468  uint16_t     FanGainLiquid;
 469  uint16_t     FanGainVrGfx;
 470  uint16_t     FanGainVrSoc;
 471  uint16_t     FanGainPlx;
 472  uint16_t     FanGainHbm;
 473  uint16_t     FanPwmMin;
 474  uint16_t     FanAcousticLimitRpm;
 475  uint16_t     FanThrottlingRpm;
 476  uint16_t     FanMaximumRpm;
 477  uint16_t     FanTargetTemperature;
 478  uint16_t     FanTargetGfxclk;
 479  uint8_t      FanZeroRpmEnable;
 480  uint8_t      FanTachEdgePerRev;
 481
 482
 483
 484  int16_t      FuzzyFan_ErrorSetDelta;
 485  int16_t      FuzzyFan_ErrorRateSetDelta;
 486  int16_t      FuzzyFan_PwmSetDelta;
 487  uint16_t     FuzzyFan_Reserved;
 488
 489
 490  uint8_t           OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
 491  uint8_t           Padding8_Avfs[2];
 492
 493  QuadraticInt_t    qAvfsGb[AVFS_VOLTAGE_COUNT];
 494  DroopInt_t        dBtcGbGfxCksOn;
 495  DroopInt_t        dBtcGbGfxCksOff;
 496  DroopInt_t        dBtcGbGfxAfll;
 497  DroopInt_t        dBtcGbSoc;
 498  LinearInt_t       qAgingGb[AVFS_VOLTAGE_COUNT];
 499
 500  QuadraticInt_t    qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
 501
 502  uint16_t          DcTol[AVFS_VOLTAGE_COUNT];
 503
 504  uint8_t           DcBtcEnabled[AVFS_VOLTAGE_COUNT];
 505  uint8_t           Padding8_GfxBtc[2];
 506
 507  int16_t           DcBtcMin[AVFS_VOLTAGE_COUNT];
 508  uint16_t          DcBtcMax[AVFS_VOLTAGE_COUNT];
 509
 510
 511  uint8_t           XgmiLinkSpeed   [NUM_XGMI_LEVELS];
 512  uint8_t           XgmiLinkWidth   [NUM_XGMI_LEVELS];
 513  uint16_t          XgmiFclkFreq    [NUM_XGMI_LEVELS];
 514  uint16_t          XgmiUclkFreq    [NUM_XGMI_LEVELS];
 515  uint16_t          XgmiSocclkFreq  [NUM_XGMI_LEVELS];
 516  uint16_t          XgmiSocVoltage  [NUM_XGMI_LEVELS];
 517
 518  uint32_t          DebugOverrides;
 519  QuadraticInt_t    ReservedEquation0;
 520  QuadraticInt_t    ReservedEquation1;
 521  QuadraticInt_t    ReservedEquation2;
 522  QuadraticInt_t    ReservedEquation3;
 523
 524  uint16_t     MinVoltageUlvGfx;
 525  uint16_t     MinVoltageUlvSoc;
 526
 527  uint16_t     MGpuFanBoostLimitRpm;
 528  uint16_t     padding16_Fan;
 529
 530  uint16_t     FanGainVrMem0;
 531  uint16_t     FanGainVrMem1;
 532
 533  uint16_t     DcBtcGb[AVFS_VOLTAGE_COUNT];
 534
 535  uint32_t     Reserved[11];
 536
 537  uint32_t     Padding32[3];
 538
 539  uint16_t     MaxVoltageStepGfx;
 540  uint16_t     MaxVoltageStepSoc;
 541
 542  uint8_t      VddGfxVrMapping;
 543  uint8_t      VddSocVrMapping;
 544  uint8_t      VddMem0VrMapping;
 545  uint8_t      VddMem1VrMapping;
 546
 547  uint8_t      GfxUlvPhaseSheddingMask;
 548  uint8_t      SocUlvPhaseSheddingMask;
 549  uint8_t      ExternalSensorPresent;
 550  uint8_t      Padding8_V;
 551
 552
 553  uint16_t     GfxMaxCurrent;
 554  int8_t       GfxOffset;
 555  uint8_t      Padding_TelemetryGfx;
 556
 557  uint16_t     SocMaxCurrent;
 558  int8_t       SocOffset;
 559  uint8_t      Padding_TelemetrySoc;
 560
 561  uint16_t     Mem0MaxCurrent;
 562  int8_t       Mem0Offset;
 563  uint8_t      Padding_TelemetryMem0;
 564
 565  uint16_t     Mem1MaxCurrent;
 566  int8_t       Mem1Offset;
 567  uint8_t      Padding_TelemetryMem1;
 568
 569
 570  uint8_t      AcDcGpio;
 571  uint8_t      AcDcPolarity;
 572  uint8_t      VR0HotGpio;
 573  uint8_t      VR0HotPolarity;
 574
 575  uint8_t      VR1HotGpio;
 576  uint8_t      VR1HotPolarity;
 577  uint8_t      Padding1;
 578  uint8_t      Padding2;
 579
 580
 581
 582  uint8_t      LedPin0;
 583  uint8_t      LedPin1;
 584  uint8_t      LedPin2;
 585  uint8_t      padding8_4;
 586
 587
 588  uint8_t      PllGfxclkSpreadEnabled;
 589  uint8_t      PllGfxclkSpreadPercent;
 590  uint16_t     PllGfxclkSpreadFreq;
 591
 592  uint8_t      UclkSpreadEnabled;
 593  uint8_t      UclkSpreadPercent;
 594  uint16_t     UclkSpreadFreq;
 595
 596  uint8_t      FclkSpreadEnabled;
 597  uint8_t      FclkSpreadPercent;
 598  uint16_t     FclkSpreadFreq;
 599
 600  uint8_t      FllGfxclkSpreadEnabled;
 601  uint8_t      FllGfxclkSpreadPercent;
 602  uint16_t     FllGfxclkSpreadFreq;
 603
 604  I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
 605
 606  uint32_t     BoardReserved[10];
 607
 608
 609  uint32_t     MmHubPadding[8];
 610
 611} PPTable_t;
 612
 613typedef struct {
 614
 615  uint16_t     GfxclkAverageLpfTau;
 616  uint16_t     SocclkAverageLpfTau;
 617  uint16_t     UclkAverageLpfTau;
 618  uint16_t     GfxActivityLpfTau;
 619  uint16_t     UclkActivityLpfTau;
 620  uint16_t     SocketPowerLpfTau;
 621
 622
 623  uint32_t     MmHubPadding[8];
 624} DriverSmuConfig_t;
 625
 626typedef struct {
 627
 628  uint16_t      GfxclkFmin;
 629  uint16_t      GfxclkFmax;
 630  uint16_t      GfxclkFreq1;
 631  uint16_t      GfxclkVolt1;
 632  uint16_t      GfxclkFreq2;
 633  uint16_t      GfxclkVolt2;
 634  uint16_t      GfxclkFreq3;
 635  uint16_t      GfxclkVolt3;
 636  uint16_t      UclkFmax;
 637  int16_t       OverDrivePct;
 638  uint16_t      FanMaximumRpm;
 639  uint16_t      FanMinimumPwm;
 640  uint16_t      FanTargetTemperature;
 641  uint16_t      MaxOpTemp;
 642  uint16_t      FanZeroRpmEnable;
 643  uint16_t      Padding;
 644
 645} OverDriveTable_t;
 646
 647typedef struct {
 648  uint16_t CurrClock[PPCLK_COUNT];
 649  uint16_t AverageGfxclkFrequency;
 650  uint16_t AverageSocclkFrequency;
 651  uint16_t AverageUclkFrequency  ;
 652  uint16_t AverageGfxActivity    ;
 653  uint16_t AverageUclkActivity   ;
 654  uint8_t  CurrSocVoltageOffset  ;
 655  uint8_t  CurrGfxVoltageOffset  ;
 656  uint8_t  CurrMemVidOffset      ;
 657  uint8_t  Padding8              ;
 658  uint16_t CurrSocketPower       ;
 659  uint16_t TemperatureEdge       ;
 660  uint16_t TemperatureHotspot    ;
 661  uint16_t TemperatureHBM        ;
 662  uint16_t TemperatureVrGfx      ;
 663  uint16_t TemperatureVrSoc      ;
 664  uint16_t TemperatureVrMem0     ;
 665  uint16_t TemperatureVrMem1     ;
 666  uint16_t TemperatureLiquid     ;
 667  uint16_t TemperaturePlx        ;
 668  uint32_t ThrottlerStatus       ;
 669
 670  uint8_t  LinkDpmLevel;
 671  uint16_t AverageSocketPower;
 672  uint8_t  Padding;
 673
 674
 675  uint32_t     MmHubPadding[7];
 676} SmuMetrics_t;
 677
 678typedef struct {
 679  uint16_t MinClock;
 680  uint16_t MaxClock;
 681  uint16_t MinUclk;
 682  uint16_t MaxUclk;
 683
 684  uint8_t  WmSetting;
 685  uint8_t  Padding[3];
 686} WatermarkRowGeneric_t;
 687
 688#define NUM_WM_RANGES 4
 689
 690typedef enum {
 691  WM_SOCCLK = 0,
 692  WM_DCEFCLK,
 693  WM_COUNT_PP,
 694} WM_CLOCK_e;
 695
 696typedef struct {
 697
 698  WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
 699
 700  uint32_t     MmHubPadding[7];
 701} Watermarks_t;
 702
 703typedef struct {
 704  uint16_t avgPsmCount[45];
 705  uint16_t minPsmCount[45];
 706  float    avgPsmVoltage[45];
 707  float    minPsmVoltage[45];
 708
 709  uint16_t avgScsPsmCount;
 710  uint16_t minScsPsmCount;
 711  float    avgScsPsmVoltage;
 712  float    minScsPsmVoltage;
 713
 714
 715  uint32_t MmHubPadding[6];
 716} AvfsDebugTable_t;
 717
 718typedef struct {
 719  uint8_t  AvfsVersion;
 720  uint8_t  AvfsEn[AVFS_VOLTAGE_COUNT];
 721
 722  uint8_t  OverrideVFT[AVFS_VOLTAGE_COUNT];
 723  uint8_t  OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
 724
 725  uint8_t  OverrideTemperatures[AVFS_VOLTAGE_COUNT];
 726  uint8_t  OverrideVInversion[AVFS_VOLTAGE_COUNT];
 727  uint8_t  OverrideP2V[AVFS_VOLTAGE_COUNT];
 728  uint8_t  OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
 729
 730  int32_t VFT0_m1[AVFS_VOLTAGE_COUNT];
 731  int32_t VFT0_m2[AVFS_VOLTAGE_COUNT];
 732  int32_t VFT0_b[AVFS_VOLTAGE_COUNT];
 733
 734  int32_t VFT1_m1[AVFS_VOLTAGE_COUNT];
 735  int32_t VFT1_m2[AVFS_VOLTAGE_COUNT];
 736  int32_t VFT1_b[AVFS_VOLTAGE_COUNT];
 737
 738  int32_t VFT2_m1[AVFS_VOLTAGE_COUNT];
 739  int32_t VFT2_m2[AVFS_VOLTAGE_COUNT];
 740  int32_t VFT2_b[AVFS_VOLTAGE_COUNT];
 741
 742  int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT];
 743  int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT];
 744  int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];
 745
 746  int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT];
 747  int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT];
 748  int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];
 749
 750  uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
 751  uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
 752  uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
 753
 754  uint32_t VInversion[AVFS_VOLTAGE_COUNT];
 755
 756
 757  int32_t P2V_m1[AVFS_VOLTAGE_COUNT];
 758  int32_t P2V_m2[AVFS_VOLTAGE_COUNT];
 759  int32_t P2V_b[AVFS_VOLTAGE_COUNT];
 760
 761  uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];
 762
 763  uint32_t EnabledAvfsModules;
 764
 765  uint32_t MmHubPadding[7];
 766} AvfsFuseOverride_t;
 767
 768typedef struct {
 769
 770  uint8_t   Gfx_ActiveHystLimit;
 771  uint8_t   Gfx_IdleHystLimit;
 772  uint8_t   Gfx_FPS;
 773  uint8_t   Gfx_MinActiveFreqType;
 774  uint8_t   Gfx_BoosterFreqType; 
 775  uint8_t   Gfx_UseRlcBusy; 
 776  uint16_t  Gfx_MinActiveFreq;
 777  uint16_t  Gfx_BoosterFreq;
 778  uint16_t  Gfx_PD_Data_time_constant;
 779  uint32_t  Gfx_PD_Data_limit_a;
 780  uint32_t  Gfx_PD_Data_limit_b;
 781  uint32_t  Gfx_PD_Data_limit_c;
 782  uint32_t  Gfx_PD_Data_error_coeff;
 783  uint32_t  Gfx_PD_Data_error_rate_coeff;
 784
 785  uint8_t   Soc_ActiveHystLimit;
 786  uint8_t   Soc_IdleHystLimit;
 787  uint8_t   Soc_FPS;
 788  uint8_t   Soc_MinActiveFreqType;
 789  uint8_t   Soc_BoosterFreqType; 
 790  uint8_t   Soc_UseRlcBusy;
 791  uint16_t  Soc_MinActiveFreq;
 792  uint16_t  Soc_BoosterFreq;
 793  uint16_t  Soc_PD_Data_time_constant;
 794  uint32_t  Soc_PD_Data_limit_a;
 795  uint32_t  Soc_PD_Data_limit_b;
 796  uint32_t  Soc_PD_Data_limit_c;
 797  uint32_t  Soc_PD_Data_error_coeff;
 798  uint32_t  Soc_PD_Data_error_rate_coeff;
 799
 800  uint8_t   Mem_ActiveHystLimit;
 801  uint8_t   Mem_IdleHystLimit;
 802  uint8_t   Mem_FPS;
 803  uint8_t   Mem_MinActiveFreqType;
 804  uint8_t   Mem_BoosterFreqType;
 805  uint8_t   Mem_UseRlcBusy; 
 806  uint16_t  Mem_MinActiveFreq;
 807  uint16_t  Mem_BoosterFreq;
 808  uint16_t  Mem_PD_Data_time_constant;
 809  uint32_t  Mem_PD_Data_limit_a;
 810  uint32_t  Mem_PD_Data_limit_b;
 811  uint32_t  Mem_PD_Data_limit_c;
 812  uint32_t  Mem_PD_Data_error_coeff;
 813  uint32_t  Mem_PD_Data_error_rate_coeff;
 814
 815  uint8_t   Fclk_ActiveHystLimit;
 816  uint8_t   Fclk_IdleHystLimit;
 817  uint8_t   Fclk_FPS;
 818  uint8_t   Fclk_MinActiveFreqType;
 819  uint8_t   Fclk_BoosterFreqType;
 820  uint8_t   Fclk_UseRlcBusy;
 821  uint16_t  Fclk_MinActiveFreq;
 822  uint16_t  Fclk_BoosterFreq;
 823  uint16_t  Fclk_PD_Data_time_constant;
 824  uint32_t  Fclk_PD_Data_limit_a;
 825  uint32_t  Fclk_PD_Data_limit_b;
 826  uint32_t  Fclk_PD_Data_limit_c;
 827  uint32_t  Fclk_PD_Data_error_coeff;
 828  uint32_t  Fclk_PD_Data_error_rate_coeff;
 829
 830} DpmActivityMonitorCoeffInt_t;
 831
 832#define TABLE_PPTABLE                 0
 833#define TABLE_WATERMARKS              1
 834#define TABLE_AVFS                    2
 835#define TABLE_AVFS_PSM_DEBUG          3
 836#define TABLE_AVFS_FUSE_OVERRIDE      4
 837#define TABLE_PMSTATUSLOG             5
 838#define TABLE_SMU_METRICS             6
 839#define TABLE_DRIVER_SMU_CONFIG       7
 840#define TABLE_ACTIVITY_MONITOR_COEFF  8
 841#define TABLE_OVERDRIVE               9
 842#define TABLE_COUNT                  10
 843
 844
 845#define UCLK_SWITCH_SLOW 0
 846#define UCLK_SWITCH_FAST 1
 847
 848
 849#define SQ_Enable_MASK 0x1
 850#define SQ_IR_MASK 0x2
 851#define SQ_PCC_MASK 0x4
 852#define SQ_EDC_MASK 0x8
 853
 854#define TCP_Enable_MASK 0x100
 855#define TCP_IR_MASK 0x200
 856#define TCP_PCC_MASK 0x400
 857#define TCP_EDC_MASK 0x800
 858
 859#define TD_Enable_MASK 0x10000
 860#define TD_IR_MASK 0x20000
 861#define TD_PCC_MASK 0x40000
 862#define TD_EDC_MASK 0x80000
 863
 864#define DB_Enable_MASK 0x1000000
 865#define DB_IR_MASK 0x2000000
 866#define DB_PCC_MASK 0x4000000
 867#define DB_EDC_MASK 0x8000000
 868
 869#define SQ_Enable_SHIFT 0
 870#define SQ_IR_SHIFT 1
 871#define SQ_PCC_SHIFT 2
 872#define SQ_EDC_SHIFT 3
 873
 874#define TCP_Enable_SHIFT 8
 875#define TCP_IR_SHIFT 9
 876#define TCP_PCC_SHIFT 10
 877#define TCP_EDC_SHIFT 11
 878
 879#define TD_Enable_SHIFT 16
 880#define TD_IR_SHIFT 17
 881#define TD_PCC_SHIFT 18
 882#define TD_EDC_SHIFT 19
 883
 884#define DB_Enable_SHIFT 24
 885#define DB_IR_SHIFT 25
 886#define DB_PCC_SHIFT 26
 887#define DB_EDC_SHIFT 27
 888
 889#define REMOVE_FMAX_MARGIN_BIT     0x0
 890#define REMOVE_DCTOL_MARGIN_BIT    0x1
 891#define REMOVE_PLATFORM_MARGIN_BIT 0x2
 892
 893#endif
 894