1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include <linux/pci.h>
28#include <linux/i2c.h>
29#include "amdgpu.h"
30#include "amdgpu_smu.h"
31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
33#include "amdgpu_atombios.h"
34#include "soc15_common.h"
35#include "smu_v11_0.h"
36#include "smu11_driver_if_navi10.h"
37#include "atom.h"
38#include "navi10_ppt.h"
39#include "smu_v11_0_pptable.h"
40#include "smu_v11_0_ppsmc.h"
41#include "nbio/nbio_2_3_offset.h"
42#include "nbio/nbio_2_3_sh_mask.h"
43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
45
46#include "asic_reg/mp/mp_11_0_sh_mask.h"
47#include "smu_cmn.h"
48
49
50
51
52
53
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
60
61#define FEATURE_MASK(feature) (1ULL << feature)
62#define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
71
72static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
73 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
74 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
75 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
76 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
77 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
78 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
79 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
80 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
81 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
82 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
83 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
84 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
85 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
86 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
87 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
88 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
89 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
90 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
91 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
92 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
95 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
96 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
97 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
98 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
99 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
100 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
101 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
102 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
103 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
104 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
105 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
106 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
107 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
108 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
109 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
110 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
111 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
112 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
113 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
114 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
115 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
116 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
117 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
118 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
119 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
120 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
121 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
122 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
123 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
124 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
125 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
126 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
127 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
128 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
129 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
130 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
131 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
132 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
133 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
134 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
135 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
136 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
137 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE,PPSMC_MSG_DALDisableDummyPstateChange, 0),
138 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
139 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
140 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
141};
142
143static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
144 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
145 CLK_MAP(SCLK, PPCLK_GFXCLK),
146 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
147 CLK_MAP(FCLK, PPCLK_SOCCLK),
148 CLK_MAP(UCLK, PPCLK_UCLK),
149 CLK_MAP(MCLK, PPCLK_UCLK),
150 CLK_MAP(DCLK, PPCLK_DCLK),
151 CLK_MAP(VCLK, PPCLK_VCLK),
152 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
153 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
154 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
155 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
156};
157
158static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
159 FEA_MAP(DPM_PREFETCHER),
160 FEA_MAP(DPM_GFXCLK),
161 FEA_MAP(DPM_GFX_PACE),
162 FEA_MAP(DPM_UCLK),
163 FEA_MAP(DPM_SOCCLK),
164 FEA_MAP(DPM_MP0CLK),
165 FEA_MAP(DPM_LINK),
166 FEA_MAP(DPM_DCEFCLK),
167 FEA_MAP(MEM_VDDCI_SCALING),
168 FEA_MAP(MEM_MVDD_SCALING),
169 FEA_MAP(DS_GFXCLK),
170 FEA_MAP(DS_SOCCLK),
171 FEA_MAP(DS_LCLK),
172 FEA_MAP(DS_DCEFCLK),
173 FEA_MAP(DS_UCLK),
174 FEA_MAP(GFX_ULV),
175 FEA_MAP(FW_DSTATE),
176 FEA_MAP(GFXOFF),
177 FEA_MAP(BACO),
178 FEA_MAP(VCN_PG),
179 FEA_MAP(JPEG_PG),
180 FEA_MAP(USB_PG),
181 FEA_MAP(RSMU_SMN_CG),
182 FEA_MAP(PPT),
183 FEA_MAP(TDC),
184 FEA_MAP(GFX_EDC),
185 FEA_MAP(APCC_PLUS),
186 FEA_MAP(GTHR),
187 FEA_MAP(ACDC),
188 FEA_MAP(VR0HOT),
189 FEA_MAP(VR1HOT),
190 FEA_MAP(FW_CTF),
191 FEA_MAP(FAN_CONTROL),
192 FEA_MAP(THERMAL),
193 FEA_MAP(GFX_DCS),
194 FEA_MAP(RM),
195 FEA_MAP(LED_DISPLAY),
196 FEA_MAP(GFX_SS),
197 FEA_MAP(OUT_OF_BAND_MONITOR),
198 FEA_MAP(TEMP_DEPENDENT_VMIN),
199 FEA_MAP(MMHUB_PG),
200 FEA_MAP(ATHUB_PG),
201 FEA_MAP(APCC_DFLL),
202};
203
204static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
205 TAB_MAP(PPTABLE),
206 TAB_MAP(WATERMARKS),
207 TAB_MAP(AVFS),
208 TAB_MAP(AVFS_PSM_DEBUG),
209 TAB_MAP(AVFS_FUSE_OVERRIDE),
210 TAB_MAP(PMSTATUSLOG),
211 TAB_MAP(SMU_METRICS),
212 TAB_MAP(DRIVER_SMU_CONFIG),
213 TAB_MAP(ACTIVITY_MONITOR_COEFF),
214 TAB_MAP(OVERDRIVE),
215 TAB_MAP(I2C_COMMANDS),
216 TAB_MAP(PACE),
217};
218
219static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
220 PWR_MAP(AC),
221 PWR_MAP(DC),
222};
223
224static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
225 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
226 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
227 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
228 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
229 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
230 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
232};
233
234static bool is_asic_secure(struct smu_context *smu)
235{
236 struct amdgpu_device *adev = smu->adev;
237 bool is_secure = true;
238 uint32_t mp0_fw_intf;
239
240 mp0_fw_intf = RREG32_PCIE(MP0_Public |
241 (smnMP0_FW_INTF & 0xffffffff));
242
243 if (!(mp0_fw_intf & (1 << 19)))
244 is_secure = false;
245
246 return is_secure;
247}
248
249static int
250navi10_get_allowed_feature_mask(struct smu_context *smu,
251 uint32_t *feature_mask, uint32_t num)
252{
253 struct amdgpu_device *adev = smu->adev;
254
255 if (num > 2)
256 return -EINVAL;
257
258 memset(feature_mask, 0, sizeof(uint32_t) * num);
259
260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
261 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
262 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
263 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
264 | FEATURE_MASK(FEATURE_PPT_BIT)
265 | FEATURE_MASK(FEATURE_TDC_BIT)
266 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
267 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
268 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
269 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
270 | FEATURE_MASK(FEATURE_THERMAL_BIT)
271 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
272 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
273 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
274 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
275 | FEATURE_MASK(FEATURE_BACO_BIT)
276 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
277 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
278 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
279 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
280
281 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
283
284 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
286
287 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
289
290 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
292
293 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
295 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
296 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
297
298 if (adev->pm.pp_feature & PP_ULV_MASK)
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
300
301 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
303
304 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
305 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
306
307 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
309
310 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
312
313 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
315
316 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
318
319 if (smu->dc_controlled_by_gpio)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
321
322
323 if (is_asic_secure(smu)) {
324
325 if ((adev->asic_type == CHIP_NAVI10) &&
326 (adev->rev_id == 0)) {
327 *(uint64_t *)feature_mask &=
328 ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
329 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
330 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
331 *(uint64_t *)feature_mask &=
332 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
333 }
334 }
335
336 return 0;
337}
338
339static int navi10_check_powerplay_table(struct smu_context *smu)
340{
341 struct smu_table_context *table_context = &smu->smu_table;
342 struct smu_11_0_powerplay_table *powerplay_table =
343 table_context->power_play_table;
344 struct smu_baco_context *smu_baco = &smu->smu_baco;
345
346 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
347 smu->dc_controlled_by_gpio = true;
348
349 mutex_lock(&smu_baco->mutex);
350 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
351 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
352 smu_baco->platform_support = true;
353 mutex_unlock(&smu_baco->mutex);
354
355 table_context->thermal_controller_type =
356 powerplay_table->thermal_controller_type;
357
358
359
360
361
362 smu->od_settings = &powerplay_table->overdrive_table;
363
364 return 0;
365}
366
367static int navi10_append_powerplay_table(struct smu_context *smu)
368{
369 struct amdgpu_device *adev = smu->adev;
370 struct smu_table_context *table_context = &smu->smu_table;
371 PPTable_t *smc_pptable = table_context->driver_pptable;
372 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
373 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
374 int index, ret;
375
376 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
377 smc_dpm_info);
378
379 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
380 (uint8_t **)&smc_dpm_table);
381 if (ret)
382 return ret;
383
384 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
385 smc_dpm_table->table_header.format_revision,
386 smc_dpm_table->table_header.content_revision);
387
388 if (smc_dpm_table->table_header.format_revision != 4) {
389 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
390 return -EINVAL;
391 }
392
393 switch (smc_dpm_table->table_header.content_revision) {
394 case 5:
395 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
396 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
397 break;
398 case 7:
399 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
400 (uint8_t **)&smc_dpm_table_v4_7);
401 if (ret)
402 return ret;
403 memcpy(smc_pptable->I2cControllers, smc_dpm_table_v4_7->I2cControllers,
404 sizeof(*smc_dpm_table_v4_7) - sizeof(smc_dpm_table_v4_7->table_header));
405 break;
406 default:
407 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
408 smc_dpm_table->table_header.content_revision);
409 return -EINVAL;
410 }
411
412 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
413
414 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
415 }
416
417 return 0;
418}
419
420static int navi10_store_powerplay_table(struct smu_context *smu)
421{
422 struct smu_table_context *table_context = &smu->smu_table;
423 struct smu_11_0_powerplay_table *powerplay_table =
424 table_context->power_play_table;
425
426 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
427 sizeof(PPTable_t));
428
429 return 0;
430}
431
432static int navi10_setup_pptable(struct smu_context *smu)
433{
434 int ret = 0;
435
436 ret = smu_v11_0_setup_pptable(smu);
437 if (ret)
438 return ret;
439
440 ret = navi10_store_powerplay_table(smu);
441 if (ret)
442 return ret;
443
444 ret = navi10_append_powerplay_table(smu);
445 if (ret)
446 return ret;
447
448 ret = navi10_check_powerplay_table(smu);
449 if (ret)
450 return ret;
451
452 return ret;
453}
454
455static int navi10_tables_init(struct smu_context *smu)
456{
457 struct smu_table_context *smu_table = &smu->smu_table;
458 struct smu_table *tables = smu_table->tables;
459
460 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
461 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
462 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
463 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
464 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
465 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
466 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
467 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
468 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
469 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
470 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
471 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
472 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
473 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
474 AMDGPU_GEM_DOMAIN_VRAM);
475
476 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
477 if (!smu_table->metrics_table)
478 return -ENOMEM;
479 smu_table->metrics_time = 0;
480
481 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
482 if (!smu_table->watermarks_table)
483 return -ENOMEM;
484
485 return 0;
486}
487
488static int navi10_get_smu_metrics_data(struct smu_context *smu,
489 MetricsMember_t member,
490 uint32_t *value)
491{
492 struct smu_table_context *smu_table= &smu->smu_table;
493 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
494 int ret = 0;
495
496 mutex_lock(&smu->metrics_lock);
497 if (!smu_table->metrics_time ||
498 time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
499 ret = smu_cmn_update_table(smu,
500 SMU_TABLE_SMU_METRICS,
501 0,
502 smu_table->metrics_table,
503 false);
504 if (ret) {
505 dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
506 mutex_unlock(&smu->metrics_lock);
507 return ret;
508 }
509 smu_table->metrics_time = jiffies;
510 }
511
512 switch (member) {
513 case METRICS_CURR_GFXCLK:
514 *value = metrics->CurrClock[PPCLK_GFXCLK];
515 break;
516 case METRICS_CURR_SOCCLK:
517 *value = metrics->CurrClock[PPCLK_SOCCLK];
518 break;
519 case METRICS_CURR_UCLK:
520 *value = metrics->CurrClock[PPCLK_UCLK];
521 break;
522 case METRICS_CURR_VCLK:
523 *value = metrics->CurrClock[PPCLK_VCLK];
524 break;
525 case METRICS_CURR_DCLK:
526 *value = metrics->CurrClock[PPCLK_DCLK];
527 break;
528 case METRICS_CURR_DCEFCLK:
529 *value = metrics->CurrClock[PPCLK_DCEFCLK];
530 break;
531 case METRICS_AVERAGE_GFXCLK:
532 *value = metrics->AverageGfxclkFrequency;
533 break;
534 case METRICS_AVERAGE_SOCCLK:
535 *value = metrics->AverageSocclkFrequency;
536 break;
537 case METRICS_AVERAGE_UCLK:
538 *value = metrics->AverageUclkFrequency;
539 break;
540 case METRICS_AVERAGE_GFXACTIVITY:
541 *value = metrics->AverageGfxActivity;
542 break;
543 case METRICS_AVERAGE_MEMACTIVITY:
544 *value = metrics->AverageUclkActivity;
545 break;
546 case METRICS_AVERAGE_SOCKETPOWER:
547 *value = metrics->AverageSocketPower << 8;
548 break;
549 case METRICS_TEMPERATURE_EDGE:
550 *value = metrics->TemperatureEdge *
551 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
552 break;
553 case METRICS_TEMPERATURE_HOTSPOT:
554 *value = metrics->TemperatureHotspot *
555 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
556 break;
557 case METRICS_TEMPERATURE_MEM:
558 *value = metrics->TemperatureMem *
559 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
560 break;
561 case METRICS_TEMPERATURE_VRGFX:
562 *value = metrics->TemperatureVrGfx *
563 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
564 break;
565 case METRICS_TEMPERATURE_VRSOC:
566 *value = metrics->TemperatureVrSoc *
567 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
568 break;
569 case METRICS_THROTTLER_STATUS:
570 *value = metrics->ThrottlerStatus;
571 break;
572 case METRICS_CURR_FANSPEED:
573 *value = metrics->CurrFanSpeed;
574 break;
575 default:
576 *value = UINT_MAX;
577 break;
578 }
579
580 mutex_unlock(&smu->metrics_lock);
581
582 return ret;
583}
584
585static int navi10_allocate_dpm_context(struct smu_context *smu)
586{
587 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
588
589 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
590 GFP_KERNEL);
591 if (!smu_dpm->dpm_context)
592 return -ENOMEM;
593
594 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
595
596 return 0;
597}
598
599static int navi10_init_smc_tables(struct smu_context *smu)
600{
601 int ret = 0;
602
603 ret = navi10_tables_init(smu);
604 if (ret)
605 return ret;
606
607 ret = navi10_allocate_dpm_context(smu);
608 if (ret)
609 return ret;
610
611 return smu_v11_0_init_smc_tables(smu);
612}
613
614static int navi10_set_default_dpm_table(struct smu_context *smu)
615{
616 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
617 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
618 struct smu_11_0_dpm_table *dpm_table;
619 int ret = 0;
620
621
622 dpm_table = &dpm_context->dpm_tables.soc_table;
623 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
624 ret = smu_v11_0_set_single_dpm_table(smu,
625 SMU_SOCCLK,
626 dpm_table);
627 if (ret)
628 return ret;
629 dpm_table->is_fine_grained =
630 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
631 } else {
632 dpm_table->count = 1;
633 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
634 dpm_table->dpm_levels[0].enabled = true;
635 dpm_table->min = dpm_table->dpm_levels[0].value;
636 dpm_table->max = dpm_table->dpm_levels[0].value;
637 }
638
639
640 dpm_table = &dpm_context->dpm_tables.gfx_table;
641 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
642 ret = smu_v11_0_set_single_dpm_table(smu,
643 SMU_GFXCLK,
644 dpm_table);
645 if (ret)
646 return ret;
647 dpm_table->is_fine_grained =
648 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
649 } else {
650 dpm_table->count = 1;
651 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
652 dpm_table->dpm_levels[0].enabled = true;
653 dpm_table->min = dpm_table->dpm_levels[0].value;
654 dpm_table->max = dpm_table->dpm_levels[0].value;
655 }
656
657
658 dpm_table = &dpm_context->dpm_tables.uclk_table;
659 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
660 ret = smu_v11_0_set_single_dpm_table(smu,
661 SMU_UCLK,
662 dpm_table);
663 if (ret)
664 return ret;
665 dpm_table->is_fine_grained =
666 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
667 } else {
668 dpm_table->count = 1;
669 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
670 dpm_table->dpm_levels[0].enabled = true;
671 dpm_table->min = dpm_table->dpm_levels[0].value;
672 dpm_table->max = dpm_table->dpm_levels[0].value;
673 }
674
675
676 dpm_table = &dpm_context->dpm_tables.vclk_table;
677 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
678 ret = smu_v11_0_set_single_dpm_table(smu,
679 SMU_VCLK,
680 dpm_table);
681 if (ret)
682 return ret;
683 dpm_table->is_fine_grained =
684 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
685 } else {
686 dpm_table->count = 1;
687 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
688 dpm_table->dpm_levels[0].enabled = true;
689 dpm_table->min = dpm_table->dpm_levels[0].value;
690 dpm_table->max = dpm_table->dpm_levels[0].value;
691 }
692
693
694 dpm_table = &dpm_context->dpm_tables.dclk_table;
695 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
696 ret = smu_v11_0_set_single_dpm_table(smu,
697 SMU_DCLK,
698 dpm_table);
699 if (ret)
700 return ret;
701 dpm_table->is_fine_grained =
702 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
703 } else {
704 dpm_table->count = 1;
705 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
706 dpm_table->dpm_levels[0].enabled = true;
707 dpm_table->min = dpm_table->dpm_levels[0].value;
708 dpm_table->max = dpm_table->dpm_levels[0].value;
709 }
710
711
712 dpm_table = &dpm_context->dpm_tables.dcef_table;
713 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
714 ret = smu_v11_0_set_single_dpm_table(smu,
715 SMU_DCEFCLK,
716 dpm_table);
717 if (ret)
718 return ret;
719 dpm_table->is_fine_grained =
720 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
721 } else {
722 dpm_table->count = 1;
723 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
724 dpm_table->dpm_levels[0].enabled = true;
725 dpm_table->min = dpm_table->dpm_levels[0].value;
726 dpm_table->max = dpm_table->dpm_levels[0].value;
727 }
728
729
730 dpm_table = &dpm_context->dpm_tables.pixel_table;
731 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
732 ret = smu_v11_0_set_single_dpm_table(smu,
733 SMU_PIXCLK,
734 dpm_table);
735 if (ret)
736 return ret;
737 dpm_table->is_fine_grained =
738 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
739 } else {
740 dpm_table->count = 1;
741 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
742 dpm_table->dpm_levels[0].enabled = true;
743 dpm_table->min = dpm_table->dpm_levels[0].value;
744 dpm_table->max = dpm_table->dpm_levels[0].value;
745 }
746
747
748 dpm_table = &dpm_context->dpm_tables.display_table;
749 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
750 ret = smu_v11_0_set_single_dpm_table(smu,
751 SMU_DISPCLK,
752 dpm_table);
753 if (ret)
754 return ret;
755 dpm_table->is_fine_grained =
756 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
757 } else {
758 dpm_table->count = 1;
759 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
760 dpm_table->dpm_levels[0].enabled = true;
761 dpm_table->min = dpm_table->dpm_levels[0].value;
762 dpm_table->max = dpm_table->dpm_levels[0].value;
763 }
764
765
766 dpm_table = &dpm_context->dpm_tables.phy_table;
767 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
768 ret = smu_v11_0_set_single_dpm_table(smu,
769 SMU_PHYCLK,
770 dpm_table);
771 if (ret)
772 return ret;
773 dpm_table->is_fine_grained =
774 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
775 } else {
776 dpm_table->count = 1;
777 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
778 dpm_table->dpm_levels[0].enabled = true;
779 dpm_table->min = dpm_table->dpm_levels[0].value;
780 dpm_table->max = dpm_table->dpm_levels[0].value;
781 }
782
783 return 0;
784}
785
786static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
787{
788 int ret = 0;
789
790 if (enable) {
791
792 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
793 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
794 if (ret)
795 return ret;
796 }
797 } else {
798 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
799 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
800 if (ret)
801 return ret;
802 }
803 }
804
805 return ret;
806}
807
808static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
809{
810 int ret = 0;
811
812 if (enable) {
813 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
814 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
815 if (ret)
816 return ret;
817 }
818 } else {
819 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
820 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
821 if (ret)
822 return ret;
823 }
824 }
825
826 return ret;
827}
828
829static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
830 enum smu_clk_type clk_type,
831 uint32_t *value)
832{
833 MetricsMember_t member_type;
834 int clk_id = 0;
835
836 clk_id = smu_cmn_to_asic_specific_index(smu,
837 CMN2ASIC_MAPPING_CLK,
838 clk_type);
839 if (clk_id < 0)
840 return clk_id;
841
842 switch (clk_id) {
843 case PPCLK_GFXCLK:
844 member_type = METRICS_CURR_GFXCLK;
845 break;
846 case PPCLK_UCLK:
847 member_type = METRICS_CURR_UCLK;
848 break;
849 case PPCLK_SOCCLK:
850 member_type = METRICS_CURR_SOCCLK;
851 break;
852 case PPCLK_VCLK:
853 member_type = METRICS_CURR_VCLK;
854 break;
855 case PPCLK_DCLK:
856 member_type = METRICS_CURR_DCLK;
857 break;
858 case PPCLK_DCEFCLK:
859 member_type = METRICS_CURR_DCEFCLK;
860 break;
861 default:
862 return -EINVAL;
863 }
864
865 return navi10_get_smu_metrics_data(smu,
866 member_type,
867 value);
868}
869
870static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
871{
872 PPTable_t *pptable = smu->smu_table.driver_pptable;
873 DpmDescriptor_t *dpm_desc = NULL;
874 uint32_t clk_index = 0;
875
876 clk_index = smu_cmn_to_asic_specific_index(smu,
877 CMN2ASIC_MAPPING_CLK,
878 clk_type);
879 dpm_desc = &pptable->DpmDescriptor[clk_index];
880
881
882 return dpm_desc->SnapToDiscrete == 0 ? true : false;
883}
884
885static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
886{
887 return od_table->cap[cap];
888}
889
890static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
891 enum SMU_11_0_ODSETTING_ID setting,
892 uint32_t *min, uint32_t *max)
893{
894 if (min)
895 *min = od_table->min[setting];
896 if (max)
897 *max = od_table->max[setting];
898}
899
900static int navi10_print_clk_levels(struct smu_context *smu,
901 enum smu_clk_type clk_type, char *buf)
902{
903 uint16_t *curve_settings;
904 int i, size = 0, ret = 0;
905 uint32_t cur_value = 0, value = 0, count = 0;
906 uint32_t freq_values[3] = {0};
907 uint32_t mark_index = 0;
908 struct smu_table_context *table_context = &smu->smu_table;
909 uint32_t gen_speed, lane_width;
910 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
911 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
912 struct amdgpu_device *adev = smu->adev;
913 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
914 OverDriveTable_t *od_table =
915 (OverDriveTable_t *)table_context->overdrive_table;
916 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
917 uint32_t min_value, max_value;
918
919 switch (clk_type) {
920 case SMU_GFXCLK:
921 case SMU_SCLK:
922 case SMU_SOCCLK:
923 case SMU_MCLK:
924 case SMU_UCLK:
925 case SMU_FCLK:
926 case SMU_DCEFCLK:
927 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
928 if (ret)
929 return size;
930
931 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
932 if (ret)
933 return size;
934
935 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
936 for (i = 0; i < count; i++) {
937 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
938 if (ret)
939 return size;
940
941 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
942 cur_value == value ? "*" : "");
943 }
944 } else {
945 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
946 if (ret)
947 return size;
948 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
949 if (ret)
950 return size;
951
952 freq_values[1] = cur_value;
953 mark_index = cur_value == freq_values[0] ? 0 :
954 cur_value == freq_values[2] ? 2 : 1;
955 if (mark_index != 1)
956 freq_values[1] = (freq_values[0] + freq_values[2]) / 2;
957
958 for (i = 0; i < 3; i++) {
959 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
960 i == mark_index ? "*" : "");
961 }
962
963 }
964 break;
965 case SMU_PCIE:
966 gen_speed = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
967 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
968 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
969 lane_width = (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
970 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
971 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
972 for (i = 0; i < NUM_LINK_LEVELS; i++)
973 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
974 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
975 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
976 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
977 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
978 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
979 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
980 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
981 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
982 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
983 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
984 pptable->LclkFreq[i],
985 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
986 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
987 "*" : "");
988 break;
989 case SMU_OD_SCLK:
990 if (!smu->od_enabled || !od_table || !od_settings)
991 break;
992 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
993 break;
994 size += sprintf(buf + size, "OD_SCLK:\n");
995 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
996 break;
997 case SMU_OD_MCLK:
998 if (!smu->od_enabled || !od_table || !od_settings)
999 break;
1000 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1001 break;
1002 size += sprintf(buf + size, "OD_MCLK:\n");
1003 size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
1004 break;
1005 case SMU_OD_VDDC_CURVE:
1006 if (!smu->od_enabled || !od_table || !od_settings)
1007 break;
1008 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1009 break;
1010 size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
1011 for (i = 0; i < 3; i++) {
1012 switch (i) {
1013 case 0:
1014 curve_settings = &od_table->GfxclkFreq1;
1015 break;
1016 case 1:
1017 curve_settings = &od_table->GfxclkFreq2;
1018 break;
1019 case 2:
1020 curve_settings = &od_table->GfxclkFreq3;
1021 break;
1022 default:
1023 break;
1024 }
1025 size += sprintf(buf + size, "%d: %uMHz %umV\n", i, curve_settings[0], curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1026 }
1027 break;
1028 case SMU_OD_RANGE:
1029 if (!smu->od_enabled || !od_table || !od_settings)
1030 break;
1031 size = sprintf(buf, "%s:\n", "OD_RANGE");
1032
1033 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1034 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1035 &min_value, NULL);
1036 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1037 NULL, &max_value);
1038 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1039 min_value, max_value);
1040 }
1041
1042 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1043 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1044 &min_value, &max_value);
1045 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1046 min_value, max_value);
1047 }
1048
1049 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1050 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1051 &min_value, &max_value);
1052 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1053 min_value, max_value);
1054 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1055 &min_value, &max_value);
1056 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1057 min_value, max_value);
1058 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1059 &min_value, &max_value);
1060 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1061 min_value, max_value);
1062 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1063 &min_value, &max_value);
1064 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1065 min_value, max_value);
1066 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1067 &min_value, &max_value);
1068 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1069 min_value, max_value);
1070 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1071 &min_value, &max_value);
1072 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1073 min_value, max_value);
1074 }
1075
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 return size;
1082}
1083
1084static int navi10_force_clk_levels(struct smu_context *smu,
1085 enum smu_clk_type clk_type, uint32_t mask)
1086{
1087
1088 int ret = 0, size = 0;
1089 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1090
1091 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1092 soft_max_level = mask ? (fls(mask) - 1) : 0;
1093
1094 switch (clk_type) {
1095 case SMU_GFXCLK:
1096 case SMU_SCLK:
1097 case SMU_SOCCLK:
1098 case SMU_MCLK:
1099 case SMU_UCLK:
1100 case SMU_DCEFCLK:
1101 case SMU_FCLK:
1102
1103 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
1104 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1105 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1106 }
1107
1108 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1109 if (ret)
1110 return size;
1111
1112 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1113 if (ret)
1114 return size;
1115
1116 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1117 if (ret)
1118 return size;
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 return size;
1125}
1126
1127static int navi10_populate_umd_state_clk(struct smu_context *smu)
1128{
1129 struct smu_11_0_dpm_context *dpm_context =
1130 smu->smu_dpm.dpm_context;
1131 struct smu_11_0_dpm_table *gfx_table =
1132 &dpm_context->dpm_tables.gfx_table;
1133 struct smu_11_0_dpm_table *mem_table =
1134 &dpm_context->dpm_tables.uclk_table;
1135 struct smu_11_0_dpm_table *soc_table =
1136 &dpm_context->dpm_tables.soc_table;
1137 struct smu_umd_pstate_table *pstate_table =
1138 &smu->pstate_table;
1139 struct amdgpu_device *adev = smu->adev;
1140 uint32_t sclk_freq;
1141
1142 pstate_table->gfxclk_pstate.min = gfx_table->min;
1143 switch (adev->asic_type) {
1144 case CHIP_NAVI10:
1145 switch (adev->pdev->revision) {
1146 case 0xf0:
1147 case 0xc0:
1148 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1149 break;
1150 case 0xf1:
1151 case 0xc1:
1152 sclk_freq = NAVI10_PEAK_SCLK_XT;
1153 break;
1154 default:
1155 sclk_freq = NAVI10_PEAK_SCLK_XL;
1156 break;
1157 }
1158 break;
1159 case CHIP_NAVI14:
1160 switch (adev->pdev->revision) {
1161 case 0xc7:
1162 case 0xf4:
1163 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1164 break;
1165 case 0xc1:
1166 case 0xf2:
1167 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1168 break;
1169 case 0xc3:
1170 case 0xf3:
1171 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1172 break;
1173 case 0xc5:
1174 case 0xf6:
1175 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1176 break;
1177 default:
1178 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1179 break;
1180 }
1181 break;
1182 case CHIP_NAVI12:
1183 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1184 break;
1185 default:
1186 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1187 break;
1188 }
1189 pstate_table->gfxclk_pstate.peak = sclk_freq;
1190
1191 pstate_table->uclk_pstate.min = mem_table->min;
1192 pstate_table->uclk_pstate.peak = mem_table->max;
1193
1194 pstate_table->socclk_pstate.min = soc_table->min;
1195 pstate_table->socclk_pstate.peak = soc_table->max;
1196
1197 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1198 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1199 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1200 pstate_table->gfxclk_pstate.standard =
1201 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1202 pstate_table->uclk_pstate.standard =
1203 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1204 pstate_table->socclk_pstate.standard =
1205 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1206 } else {
1207 pstate_table->gfxclk_pstate.standard =
1208 pstate_table->gfxclk_pstate.min;
1209 pstate_table->uclk_pstate.standard =
1210 pstate_table->uclk_pstate.min;
1211 pstate_table->socclk_pstate.standard =
1212 pstate_table->socclk_pstate.min;
1213 }
1214
1215 return 0;
1216}
1217
1218static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1219 enum smu_clk_type clk_type,
1220 struct pp_clock_levels_with_latency *clocks)
1221{
1222 int ret = 0, i = 0;
1223 uint32_t level_count = 0, freq = 0;
1224
1225 switch (clk_type) {
1226 case SMU_GFXCLK:
1227 case SMU_DCEFCLK:
1228 case SMU_SOCCLK:
1229 case SMU_MCLK:
1230 case SMU_UCLK:
1231 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1232 if (ret)
1233 return ret;
1234
1235 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1236 clocks->num_levels = level_count;
1237
1238 for (i = 0; i < level_count; i++) {
1239 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1240 if (ret)
1241 return ret;
1242
1243 clocks->data[i].clocks_in_khz = freq * 1000;
1244 clocks->data[i].latency_in_us = 0;
1245 }
1246 break;
1247 default:
1248 break;
1249 }
1250
1251 return ret;
1252}
1253
1254static int navi10_pre_display_config_changed(struct smu_context *smu)
1255{
1256 int ret = 0;
1257 uint32_t max_freq = 0;
1258
1259 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1260 if (ret)
1261 return ret;
1262
1263 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1264 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1265 if (ret)
1266 return ret;
1267 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1268 if (ret)
1269 return ret;
1270 }
1271
1272 return ret;
1273}
1274
1275static int navi10_display_config_changed(struct smu_context *smu)
1276{
1277 int ret = 0;
1278
1279 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1280 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1281 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1282 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1283 smu->display_config->num_display,
1284 NULL);
1285 if (ret)
1286 return ret;
1287 }
1288
1289 return ret;
1290}
1291
1292static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
1293{
1294 if (!value)
1295 return -EINVAL;
1296
1297 return navi10_get_smu_metrics_data(smu,
1298 METRICS_AVERAGE_SOCKETPOWER,
1299 value);
1300}
1301
1302static int navi10_get_current_activity_percent(struct smu_context *smu,
1303 enum amd_pp_sensors sensor,
1304 uint32_t *value)
1305{
1306 int ret = 0;
1307
1308 if (!value)
1309 return -EINVAL;
1310
1311 switch (sensor) {
1312 case AMDGPU_PP_SENSOR_GPU_LOAD:
1313 ret = navi10_get_smu_metrics_data(smu,
1314 METRICS_AVERAGE_GFXACTIVITY,
1315 value);
1316 break;
1317 case AMDGPU_PP_SENSOR_MEM_LOAD:
1318 ret = navi10_get_smu_metrics_data(smu,
1319 METRICS_AVERAGE_MEMACTIVITY,
1320 value);
1321 break;
1322 default:
1323 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1324 return -EINVAL;
1325 }
1326
1327 return ret;
1328}
1329
1330static bool navi10_is_dpm_running(struct smu_context *smu)
1331{
1332 int ret = 0;
1333 uint32_t feature_mask[2];
1334 uint64_t feature_enabled;
1335
1336 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1337 if (ret)
1338 return false;
1339
1340 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1341
1342 return !!(feature_enabled & SMC_DPM_FEATURE);
1343}
1344
1345static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1346 uint32_t *speed)
1347{
1348 if (!speed)
1349 return -EINVAL;
1350
1351 return navi10_get_smu_metrics_data(smu,
1352 METRICS_CURR_FANSPEED,
1353 speed);
1354}
1355
1356static int navi10_get_fan_speed_percent(struct smu_context *smu,
1357 uint32_t *speed)
1358{
1359 int ret = 0;
1360 uint32_t percent = 0;
1361 uint32_t current_rpm;
1362 PPTable_t *pptable = smu->smu_table.driver_pptable;
1363
1364 ret = navi10_get_fan_speed_rpm(smu, ¤t_rpm);
1365 if (ret)
1366 return ret;
1367
1368 percent = current_rpm * 100 / pptable->FanMaximumRpm;
1369 *speed = percent > 100 ? 100 : percent;
1370
1371 return ret;
1372}
1373
1374static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1375{
1376 DpmActivityMonitorCoeffInt_t activity_monitor;
1377 uint32_t i, size = 0;
1378 int16_t workload_type = 0;
1379 static const char *profile_name[] = {
1380 "BOOTUP_DEFAULT",
1381 "3D_FULL_SCREEN",
1382 "POWER_SAVING",
1383 "VIDEO",
1384 "VR",
1385 "COMPUTE",
1386 "CUSTOM"};
1387 static const char *title[] = {
1388 "PROFILE_INDEX(NAME)",
1389 "CLOCK_TYPE(NAME)",
1390 "FPS",
1391 "MinFreqType",
1392 "MinActiveFreqType",
1393 "MinActiveFreq",
1394 "BoosterFreqType",
1395 "BoosterFreq",
1396 "PD_Data_limit_c",
1397 "PD_Data_error_coeff",
1398 "PD_Data_error_rate_coeff"};
1399 int result = 0;
1400
1401 if (!buf)
1402 return -EINVAL;
1403
1404 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1405 title[0], title[1], title[2], title[3], title[4], title[5],
1406 title[6], title[7], title[8], title[9], title[10]);
1407
1408 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1409
1410 workload_type = smu_cmn_to_asic_specific_index(smu,
1411 CMN2ASIC_MAPPING_WORKLOAD,
1412 i);
1413 if (workload_type < 0)
1414 return -EINVAL;
1415
1416 result = smu_cmn_update_table(smu,
1417 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1418 (void *)(&activity_monitor), false);
1419 if (result) {
1420 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1421 return result;
1422 }
1423
1424 size += sprintf(buf + size, "%2d %14s%s:\n",
1425 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1426
1427 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1428 " ",
1429 0,
1430 "GFXCLK",
1431 activity_monitor.Gfx_FPS,
1432 activity_monitor.Gfx_MinFreqStep,
1433 activity_monitor.Gfx_MinActiveFreqType,
1434 activity_monitor.Gfx_MinActiveFreq,
1435 activity_monitor.Gfx_BoosterFreqType,
1436 activity_monitor.Gfx_BoosterFreq,
1437 activity_monitor.Gfx_PD_Data_limit_c,
1438 activity_monitor.Gfx_PD_Data_error_coeff,
1439 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1440
1441 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1442 " ",
1443 1,
1444 "SOCCLK",
1445 activity_monitor.Soc_FPS,
1446 activity_monitor.Soc_MinFreqStep,
1447 activity_monitor.Soc_MinActiveFreqType,
1448 activity_monitor.Soc_MinActiveFreq,
1449 activity_monitor.Soc_BoosterFreqType,
1450 activity_monitor.Soc_BoosterFreq,
1451 activity_monitor.Soc_PD_Data_limit_c,
1452 activity_monitor.Soc_PD_Data_error_coeff,
1453 activity_monitor.Soc_PD_Data_error_rate_coeff);
1454
1455 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1456 " ",
1457 2,
1458 "MEMLK",
1459 activity_monitor.Mem_FPS,
1460 activity_monitor.Mem_MinFreqStep,
1461 activity_monitor.Mem_MinActiveFreqType,
1462 activity_monitor.Mem_MinActiveFreq,
1463 activity_monitor.Mem_BoosterFreqType,
1464 activity_monitor.Mem_BoosterFreq,
1465 activity_monitor.Mem_PD_Data_limit_c,
1466 activity_monitor.Mem_PD_Data_error_coeff,
1467 activity_monitor.Mem_PD_Data_error_rate_coeff);
1468 }
1469
1470 return size;
1471}
1472
1473static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1474{
1475 DpmActivityMonitorCoeffInt_t activity_monitor;
1476 int workload_type, ret = 0;
1477
1478 smu->power_profile_mode = input[size];
1479
1480 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1481 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1482 return -EINVAL;
1483 }
1484
1485 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1486
1487 ret = smu_cmn_update_table(smu,
1488 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1489 (void *)(&activity_monitor), false);
1490 if (ret) {
1491 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1492 return ret;
1493 }
1494
1495 switch (input[0]) {
1496 case 0:
1497 activity_monitor.Gfx_FPS = input[1];
1498 activity_monitor.Gfx_MinFreqStep = input[2];
1499 activity_monitor.Gfx_MinActiveFreqType = input[3];
1500 activity_monitor.Gfx_MinActiveFreq = input[4];
1501 activity_monitor.Gfx_BoosterFreqType = input[5];
1502 activity_monitor.Gfx_BoosterFreq = input[6];
1503 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1504 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1505 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1506 break;
1507 case 1:
1508 activity_monitor.Soc_FPS = input[1];
1509 activity_monitor.Soc_MinFreqStep = input[2];
1510 activity_monitor.Soc_MinActiveFreqType = input[3];
1511 activity_monitor.Soc_MinActiveFreq = input[4];
1512 activity_monitor.Soc_BoosterFreqType = input[5];
1513 activity_monitor.Soc_BoosterFreq = input[6];
1514 activity_monitor.Soc_PD_Data_limit_c = input[7];
1515 activity_monitor.Soc_PD_Data_error_coeff = input[8];
1516 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
1517 break;
1518 case 2:
1519 activity_monitor.Mem_FPS = input[1];
1520 activity_monitor.Mem_MinFreqStep = input[2];
1521 activity_monitor.Mem_MinActiveFreqType = input[3];
1522 activity_monitor.Mem_MinActiveFreq = input[4];
1523 activity_monitor.Mem_BoosterFreqType = input[5];
1524 activity_monitor.Mem_BoosterFreq = input[6];
1525 activity_monitor.Mem_PD_Data_limit_c = input[7];
1526 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1527 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1528 break;
1529 }
1530
1531 ret = smu_cmn_update_table(smu,
1532 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1533 (void *)(&activity_monitor), true);
1534 if (ret) {
1535 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1536 return ret;
1537 }
1538 }
1539
1540
1541 workload_type = smu_cmn_to_asic_specific_index(smu,
1542 CMN2ASIC_MAPPING_WORKLOAD,
1543 smu->power_profile_mode);
1544 if (workload_type < 0)
1545 return -EINVAL;
1546 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1547 1 << workload_type, NULL);
1548
1549 return ret;
1550}
1551
1552static int navi10_notify_smc_display_config(struct smu_context *smu)
1553{
1554 struct smu_clocks min_clocks = {0};
1555 struct pp_display_clock_request clock_req;
1556 int ret = 0;
1557
1558 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1559 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1560 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1561
1562 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1563 clock_req.clock_type = amd_pp_dcef_clock;
1564 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1565
1566 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1567 if (!ret) {
1568 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1569 ret = smu_cmn_send_smc_msg_with_param(smu,
1570 SMU_MSG_SetMinDeepSleepDcefclk,
1571 min_clocks.dcef_clock_in_sr/100,
1572 NULL);
1573 if (ret) {
1574 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1575 return ret;
1576 }
1577 }
1578 } else {
1579 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1580 }
1581 }
1582
1583 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1584 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1585 if (ret) {
1586 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1587 return ret;
1588 }
1589 }
1590
1591 return 0;
1592}
1593
1594static int navi10_set_watermarks_table(struct smu_context *smu,
1595 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1596{
1597 Watermarks_t *table = smu->smu_table.watermarks_table;
1598 int ret = 0;
1599 int i;
1600
1601 if (clock_ranges) {
1602 if (clock_ranges->num_wm_dmif_sets > 4 ||
1603 clock_ranges->num_wm_mcif_sets > 4)
1604 return -EINVAL;
1605
1606 for (i = 0; i < clock_ranges->num_wm_dmif_sets; i++) {
1607 table->WatermarkRow[1][i].MinClock =
1608 cpu_to_le16((uint16_t)
1609 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
1610 1000));
1611 table->WatermarkRow[1][i].MaxClock =
1612 cpu_to_le16((uint16_t)
1613 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
1614 1000));
1615 table->WatermarkRow[1][i].MinUclk =
1616 cpu_to_le16((uint16_t)
1617 (clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1618 1000));
1619 table->WatermarkRow[1][i].MaxUclk =
1620 cpu_to_le16((uint16_t)
1621 (clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1622 1000));
1623 table->WatermarkRow[1][i].WmSetting = (uint8_t)
1624 clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id;
1625 }
1626
1627 for (i = 0; i < clock_ranges->num_wm_mcif_sets; i++) {
1628 table->WatermarkRow[0][i].MinClock =
1629 cpu_to_le16((uint16_t)
1630 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz /
1631 1000));
1632 table->WatermarkRow[0][i].MaxClock =
1633 cpu_to_le16((uint16_t)
1634 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz /
1635 1000));
1636 table->WatermarkRow[0][i].MinUclk =
1637 cpu_to_le16((uint16_t)
1638 (clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
1639 1000));
1640 table->WatermarkRow[0][i].MaxUclk =
1641 cpu_to_le16((uint16_t)
1642 (clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz /
1643 1000));
1644 table->WatermarkRow[0][i].WmSetting = (uint8_t)
1645 clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id;
1646 }
1647
1648 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1649 }
1650
1651
1652 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1653 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1654 ret = smu_cmn_write_watermarks_table(smu);
1655 if (ret) {
1656 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1657 return ret;
1658 }
1659 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1660 }
1661
1662 return 0;
1663}
1664
1665static int navi10_thermal_get_temperature(struct smu_context *smu,
1666 enum amd_pp_sensors sensor,
1667 uint32_t *value)
1668{
1669 int ret = 0;
1670
1671 if (!value)
1672 return -EINVAL;
1673
1674 switch (sensor) {
1675 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1676 ret = navi10_get_smu_metrics_data(smu,
1677 METRICS_TEMPERATURE_HOTSPOT,
1678 value);
1679 break;
1680 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1681 ret = navi10_get_smu_metrics_data(smu,
1682 METRICS_TEMPERATURE_EDGE,
1683 value);
1684 break;
1685 case AMDGPU_PP_SENSOR_MEM_TEMP:
1686 ret = navi10_get_smu_metrics_data(smu,
1687 METRICS_TEMPERATURE_MEM,
1688 value);
1689 break;
1690 default:
1691 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1692 return -EINVAL;
1693 }
1694
1695 return ret;
1696}
1697
1698static int navi10_read_sensor(struct smu_context *smu,
1699 enum amd_pp_sensors sensor,
1700 void *data, uint32_t *size)
1701{
1702 int ret = 0;
1703 struct smu_table_context *table_context = &smu->smu_table;
1704 PPTable_t *pptable = table_context->driver_pptable;
1705
1706 if(!data || !size)
1707 return -EINVAL;
1708
1709 mutex_lock(&smu->sensor_lock);
1710 switch (sensor) {
1711 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1712 *(uint32_t *)data = pptable->FanMaximumRpm;
1713 *size = 4;
1714 break;
1715 case AMDGPU_PP_SENSOR_MEM_LOAD:
1716 case AMDGPU_PP_SENSOR_GPU_LOAD:
1717 ret = navi10_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1718 *size = 4;
1719 break;
1720 case AMDGPU_PP_SENSOR_GPU_POWER:
1721 ret = navi10_get_gpu_power(smu, (uint32_t *)data);
1722 *size = 4;
1723 break;
1724 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1725 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1726 case AMDGPU_PP_SENSOR_MEM_TEMP:
1727 ret = navi10_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1728 *size = 4;
1729 break;
1730 case AMDGPU_PP_SENSOR_GFX_MCLK:
1731 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1732 *(uint32_t *)data *= 100;
1733 *size = 4;
1734 break;
1735 case AMDGPU_PP_SENSOR_GFX_SCLK:
1736 ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1737 *(uint32_t *)data *= 100;
1738 *size = 4;
1739 break;
1740 case AMDGPU_PP_SENSOR_VDDGFX:
1741 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1742 *size = 4;
1743 break;
1744 default:
1745 ret = -EOPNOTSUPP;
1746 break;
1747 }
1748 mutex_unlock(&smu->sensor_lock);
1749
1750 return ret;
1751}
1752
1753static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1754{
1755 uint32_t num_discrete_levels = 0;
1756 uint16_t *dpm_levels = NULL;
1757 uint16_t i = 0;
1758 struct smu_table_context *table_context = &smu->smu_table;
1759 PPTable_t *driver_ppt = NULL;
1760
1761 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1762 return -EINVAL;
1763
1764 driver_ppt = table_context->driver_pptable;
1765 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1766 dpm_levels = driver_ppt->FreqTableUclk;
1767
1768 if (num_discrete_levels == 0 || dpm_levels == NULL)
1769 return -EINVAL;
1770
1771 *num_states = num_discrete_levels;
1772 for (i = 0; i < num_discrete_levels; i++) {
1773
1774 *clocks_in_khz = (*dpm_levels) * 1000;
1775 clocks_in_khz++;
1776 dpm_levels++;
1777 }
1778
1779 return 0;
1780}
1781
1782static int navi10_get_thermal_temperature_range(struct smu_context *smu,
1783 struct smu_temperature_range *range)
1784{
1785 struct smu_table_context *table_context = &smu->smu_table;
1786 struct smu_11_0_powerplay_table *powerplay_table =
1787 table_context->power_play_table;
1788 PPTable_t *pptable = smu->smu_table.driver_pptable;
1789
1790 if (!range)
1791 return -EINVAL;
1792
1793 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1794
1795 range->max = pptable->TedgeLimit *
1796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1797 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1798 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1799 range->hotspot_crit_max = pptable->ThotspotLimit *
1800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1801 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1802 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1803 range->mem_crit_max = pptable->TmemLimit *
1804 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1805 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1806 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1807 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1808
1809 return 0;
1810}
1811
1812static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
1813 bool disable_memory_clock_switch)
1814{
1815 int ret = 0;
1816 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1817 (struct smu_11_0_max_sustainable_clocks *)
1818 smu->smu_table.max_sustainable_clocks;
1819 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1820 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1821
1822 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1823 return 0;
1824
1825 if(disable_memory_clock_switch)
1826 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1827 else
1828 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1829
1830 if(!ret)
1831 smu->disable_uclk_switch = disable_memory_clock_switch;
1832
1833 return ret;
1834}
1835
1836static int navi10_get_power_limit(struct smu_context *smu)
1837{
1838 struct smu_11_0_powerplay_table *powerplay_table =
1839 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1840 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1841 PPTable_t *pptable = smu->smu_table.driver_pptable;
1842 uint32_t power_limit, od_percent;
1843
1844 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1845
1846 if (!pptable) {
1847 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1848 return -EINVAL;
1849 }
1850 power_limit =
1851 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1852 }
1853 smu->current_power_limit = power_limit;
1854
1855 if (smu->od_enabled &&
1856 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
1857 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1858
1859 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1860
1861 power_limit *= (100 + od_percent);
1862 power_limit /= 100;
1863 }
1864 smu->max_power_limit = power_limit;
1865
1866 return 0;
1867}
1868
1869static int navi10_update_pcie_parameters(struct smu_context *smu,
1870 uint32_t pcie_gen_cap,
1871 uint32_t pcie_width_cap)
1872{
1873 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1874 PPTable_t *pptable = smu->smu_table.driver_pptable;
1875 uint32_t smu_pcie_arg;
1876 int ret, i;
1877
1878
1879 for (i = 0; i < MAX_PCIE_CONF; i++) {
1880 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1881 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1882 }
1883
1884 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1885 smu_pcie_arg = (i << 16) |
1886 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
1887 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1888 pptable->PcieLaneCount[i] : pcie_width_cap);
1889 ret = smu_cmn_send_smc_msg_with_param(smu,
1890 SMU_MSG_OverridePcieParameters,
1891 smu_pcie_arg,
1892 NULL);
1893
1894 if (ret)
1895 return ret;
1896
1897 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1898 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1899 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1900 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1901 }
1902
1903 return 0;
1904}
1905
1906static inline void navi10_dump_od_table(struct smu_context *smu,
1907 OverDriveTable_t *od_table)
1908{
1909 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1910 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
1911 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
1912 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
1913 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
1914 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
1915}
1916
1917static int navi10_od_setting_check_range(struct smu_context *smu,
1918 struct smu_11_0_overdrive_table *od_table,
1919 enum SMU_11_0_ODSETTING_ID setting,
1920 uint32_t value)
1921{
1922 if (value < od_table->min[setting]) {
1923 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
1924 return -EINVAL;
1925 }
1926 if (value > od_table->max[setting]) {
1927 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
1928 return -EINVAL;
1929 }
1930 return 0;
1931}
1932
1933static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
1934 uint16_t *voltage,
1935 uint32_t freq)
1936{
1937 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
1938 uint32_t value = 0;
1939 int ret;
1940
1941 ret = smu_cmn_send_smc_msg_with_param(smu,
1942 SMU_MSG_GetVoltageByDpm,
1943 param,
1944 &value);
1945 if (ret) {
1946 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
1947 return ret;
1948 }
1949
1950 *voltage = (uint16_t)value;
1951
1952 return 0;
1953}
1954
1955static bool navi10_is_baco_supported(struct smu_context *smu)
1956{
1957 struct amdgpu_device *adev = smu->adev;
1958 uint32_t val;
1959
1960 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1961 return false;
1962
1963 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
1964 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
1965}
1966
1967static int navi10_set_default_od_settings(struct smu_context *smu)
1968{
1969 OverDriveTable_t *od_table =
1970 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1971 OverDriveTable_t *boot_od_table =
1972 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1973 int ret = 0;
1974
1975 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, false);
1976 if (ret) {
1977 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1978 return ret;
1979 }
1980
1981 if (!od_table->GfxclkVolt1) {
1982 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1983 &od_table->GfxclkVolt1,
1984 od_table->GfxclkFreq1);
1985 if (ret)
1986 return ret;
1987 }
1988
1989 if (!od_table->GfxclkVolt2) {
1990 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1991 &od_table->GfxclkVolt2,
1992 od_table->GfxclkFreq2);
1993 if (ret)
1994 return ret;
1995 }
1996
1997 if (!od_table->GfxclkVolt3) {
1998 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
1999 &od_table->GfxclkVolt3,
2000 od_table->GfxclkFreq3);
2001 if (ret)
2002 return ret;
2003 }
2004
2005 memcpy(boot_od_table, od_table, sizeof(OverDriveTable_t));
2006
2007 navi10_dump_od_table(smu, od_table);
2008
2009 return 0;
2010}
2011
2012static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) {
2013 int i;
2014 int ret = 0;
2015 struct smu_table_context *table_context = &smu->smu_table;
2016 OverDriveTable_t *od_table;
2017 struct smu_11_0_overdrive_table *od_settings;
2018 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2019 uint16_t *freq_ptr, *voltage_ptr;
2020 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2021
2022 if (!smu->od_enabled) {
2023 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2024 return -EINVAL;
2025 }
2026
2027 if (!smu->od_settings) {
2028 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2029 return -ENOENT;
2030 }
2031
2032 od_settings = smu->od_settings;
2033
2034 switch (type) {
2035 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2036 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2037 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2038 return -ENOTSUPP;
2039 }
2040 if (!table_context->overdrive_table) {
2041 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2042 return -EINVAL;
2043 }
2044 for (i = 0; i < size; i += 2) {
2045 if (i + 2 > size) {
2046 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2047 return -EINVAL;
2048 }
2049 switch (input[i]) {
2050 case 0:
2051 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2052 freq_ptr = &od_table->GfxclkFmin;
2053 if (input[i + 1] > od_table->GfxclkFmax) {
2054 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2055 input[i + 1],
2056 od_table->GfxclkFmin);
2057 return -EINVAL;
2058 }
2059 break;
2060 case 1:
2061 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2062 freq_ptr = &od_table->GfxclkFmax;
2063 if (input[i + 1] < od_table->GfxclkFmin) {
2064 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2065 input[i + 1],
2066 od_table->GfxclkFmax);
2067 return -EINVAL;
2068 }
2069 break;
2070 default:
2071 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2072 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2073 return -EINVAL;
2074 }
2075 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2076 if (ret)
2077 return ret;
2078 *freq_ptr = input[i + 1];
2079 }
2080 break;
2081 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2082 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2083 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2084 return -ENOTSUPP;
2085 }
2086 if (size < 2) {
2087 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2088 return -EINVAL;
2089 }
2090 if (input[0] != 1) {
2091 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2092 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2093 return -EINVAL;
2094 }
2095 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2096 if (ret)
2097 return ret;
2098 od_table->UclkFmax = input[1];
2099 break;
2100 case PP_OD_RESTORE_DEFAULT_TABLE:
2101 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2102 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2103 return -EINVAL;
2104 }
2105 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2106 break;
2107 case PP_OD_COMMIT_DPM_TABLE:
2108 navi10_dump_od_table(smu, od_table);
2109 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2110 if (ret) {
2111 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2112 return ret;
2113 }
2114 break;
2115 case PP_OD_EDIT_VDDC_CURVE:
2116 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2117 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2118 return -ENOTSUPP;
2119 }
2120 if (size < 3) {
2121 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2122 return -EINVAL;
2123 }
2124 if (!od_table) {
2125 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2126 return -EINVAL;
2127 }
2128
2129 switch (input[0]) {
2130 case 0:
2131 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2132 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2133 freq_ptr = &od_table->GfxclkFreq1;
2134 voltage_ptr = &od_table->GfxclkVolt1;
2135 break;
2136 case 1:
2137 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2138 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2139 freq_ptr = &od_table->GfxclkFreq2;
2140 voltage_ptr = &od_table->GfxclkVolt2;
2141 break;
2142 case 2:
2143 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2144 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2145 freq_ptr = &od_table->GfxclkFreq3;
2146 voltage_ptr = &od_table->GfxclkVolt3;
2147 break;
2148 default:
2149 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2150 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2151 return -EINVAL;
2152 }
2153 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2154 if (ret)
2155 return ret;
2156
2157 if (input[2] != 0) {
2158 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2159 if (ret)
2160 return ret;
2161 *freq_ptr = input[1];
2162 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2163 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2164 } else {
2165
2166 od_table->GfxclkVolt1 = 0;
2167 od_table->GfxclkVolt2 = 0;
2168 od_table->GfxclkVolt3 = 0;
2169 }
2170 navi10_dump_od_table(smu, od_table);
2171 break;
2172 default:
2173 return -ENOSYS;
2174 }
2175 return ret;
2176}
2177
2178static int navi10_run_btc(struct smu_context *smu)
2179{
2180 int ret = 0;
2181
2182 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2183 if (ret)
2184 dev_err(smu->adev->dev, "RunBtc failed!\n");
2185
2186 return ret;
2187}
2188
2189static int navi10_dummy_pstate_control(struct smu_context *smu, bool enable)
2190{
2191 int result = 0;
2192
2193 if (!enable)
2194 result = smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE, NULL);
2195 else
2196 result = smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2197
2198 return result;
2199}
2200
2201static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
2202{
2203 if (adev->asic_type != CHIP_NAVI10)
2204 return false;
2205
2206 if (adev->pdev->device == 0x731f &&
2207 (adev->pdev->revision == 0xc2 ||
2208 adev->pdev->revision == 0xc3 ||
2209 adev->pdev->revision == 0xca ||
2210 adev->pdev->revision == 0xcb))
2211 return true;
2212 else
2213 return false;
2214}
2215
2216static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
2217{
2218 uint32_t uclk_count, uclk_min, uclk_max;
2219 uint32_t smu_version;
2220 int ret = 0;
2221
2222 if (!navi10_need_umc_cdr_12gbps_workaround(smu->adev))
2223 return 0;
2224
2225 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2226 if (ret)
2227 return ret;
2228
2229
2230 if (smu_version < 0x2A3200)
2231 return 0;
2232
2233 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2234 if (ret)
2235 return ret;
2236
2237 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2238 if (ret)
2239 return ret;
2240
2241 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2242 if (ret)
2243 return ret;
2244
2245
2246 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2247 if (ret)
2248 return ret;
2249
2250
2251 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2252 if (ret)
2253 return ret;
2254
2255
2256
2257
2258
2259 return navi10_dummy_pstate_control(smu, true);
2260}
2261
2262static void navi10_fill_i2c_req(SwI2cRequest_t *req, bool write,
2263 uint8_t address, uint32_t numbytes,
2264 uint8_t *data)
2265{
2266 int i;
2267
2268 req->I2CcontrollerPort = 0;
2269 req->I2CSpeed = 2;
2270 req->SlaveAddress = address;
2271 req->NumCmds = numbytes;
2272
2273 for (i = 0; i < numbytes; i++) {
2274 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2275
2276
2277 if (i < 2)
2278 cmd->Cmd = 1;
2279 else
2280 cmd->Cmd = write;
2281
2282
2283
2284 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2285
2286
2287 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2288
2289
2290 cmd->RegisterAddr = data[i];
2291 }
2292}
2293
2294static int navi10_i2c_read_data(struct i2c_adapter *control,
2295 uint8_t address,
2296 uint8_t *data,
2297 uint32_t numbytes)
2298{
2299 uint32_t i, ret = 0;
2300 SwI2cRequest_t req;
2301 struct amdgpu_device *adev = to_amdgpu_device(control);
2302 struct smu_table_context *smu_table = &adev->smu.smu_table;
2303 struct smu_table *table = &smu_table->driver_table;
2304
2305 if (numbytes > MAX_SW_I2C_COMMANDS) {
2306 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2307 numbytes, MAX_SW_I2C_COMMANDS);
2308 return -EINVAL;
2309 }
2310
2311 memset(&req, 0, sizeof(req));
2312 navi10_fill_i2c_req(&req, false, address, numbytes, data);
2313
2314 mutex_lock(&adev->smu.mutex);
2315
2316 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2317 true);
2318 mutex_unlock(&adev->smu.mutex);
2319
2320 if (!ret) {
2321 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2322
2323
2324 for (i = 0; i < numbytes; i++)
2325 data[i] = res->SwI2cCmds[i].Data;
2326
2327 dev_dbg(adev->dev, "navi10_i2c_read_data, address = %x, bytes = %d, data :",
2328 (uint16_t)address, numbytes);
2329
2330 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2331 8, 1, data, numbytes, false);
2332 } else
2333 dev_err(adev->dev, "navi10_i2c_read_data - error occurred :%x", ret);
2334
2335 return ret;
2336}
2337
2338static int navi10_i2c_write_data(struct i2c_adapter *control,
2339 uint8_t address,
2340 uint8_t *data,
2341 uint32_t numbytes)
2342{
2343 uint32_t ret;
2344 SwI2cRequest_t req;
2345 struct amdgpu_device *adev = to_amdgpu_device(control);
2346
2347 if (numbytes > MAX_SW_I2C_COMMANDS) {
2348 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2349 numbytes, MAX_SW_I2C_COMMANDS);
2350 return -EINVAL;
2351 }
2352
2353 memset(&req, 0, sizeof(req));
2354 navi10_fill_i2c_req(&req, true, address, numbytes, data);
2355
2356 mutex_lock(&adev->smu.mutex);
2357 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2358 mutex_unlock(&adev->smu.mutex);
2359
2360 if (!ret) {
2361 dev_dbg(adev->dev, "navi10_i2c_write(), address = %x, bytes = %d , data: ",
2362 (uint16_t)address, numbytes);
2363
2364 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2365 8, 1, data, numbytes, false);
2366
2367
2368
2369
2370
2371
2372 msleep(10);
2373
2374 } else
2375 dev_err(adev->dev, "navi10_i2c_write- error occurred :%x", ret);
2376
2377 return ret;
2378}
2379
2380static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2381 struct i2c_msg *msgs, int num)
2382{
2383 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2384 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2385
2386 for (i = 0; i < num; i++) {
2387
2388
2389
2390
2391
2392 data_size = msgs[i].len - 2;
2393 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2394 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2395 data_ptr = msgs[i].buf + 2;
2396
2397 for (j = 0; j < data_size / data_chunk_size; j++) {
2398
2399 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2400 data_chunk[1] = (next_eeprom_addr & 0xff);
2401
2402 if (msgs[i].flags & I2C_M_RD) {
2403 ret = navi10_i2c_read_data(i2c_adap,
2404 (uint8_t)msgs[i].addr,
2405 data_chunk, MAX_SW_I2C_COMMANDS);
2406
2407 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2408 } else {
2409
2410 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2411
2412 ret = navi10_i2c_write_data(i2c_adap,
2413 (uint8_t)msgs[i].addr,
2414 data_chunk, MAX_SW_I2C_COMMANDS);
2415 }
2416
2417 if (ret) {
2418 num = -EIO;
2419 goto fail;
2420 }
2421
2422 next_eeprom_addr += data_chunk_size;
2423 data_ptr += data_chunk_size;
2424 }
2425
2426 if (data_size % data_chunk_size) {
2427 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2428 data_chunk[1] = (next_eeprom_addr & 0xff);
2429
2430 if (msgs[i].flags & I2C_M_RD) {
2431 ret = navi10_i2c_read_data(i2c_adap,
2432 (uint8_t)msgs[i].addr,
2433 data_chunk, (data_size % data_chunk_size) + 2);
2434
2435 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2436 } else {
2437 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2438
2439 ret = navi10_i2c_write_data(i2c_adap,
2440 (uint8_t)msgs[i].addr,
2441 data_chunk, (data_size % data_chunk_size) + 2);
2442 }
2443
2444 if (ret) {
2445 num = -EIO;
2446 goto fail;
2447 }
2448 }
2449 }
2450
2451fail:
2452 return num;
2453}
2454
2455static u32 navi10_i2c_func(struct i2c_adapter *adap)
2456{
2457 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2458}
2459
2460
2461static const struct i2c_algorithm navi10_i2c_algo = {
2462 .master_xfer = navi10_i2c_xfer,
2463 .functionality = navi10_i2c_func,
2464};
2465
2466static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2467{
2468 struct amdgpu_device *adev = to_amdgpu_device(control);
2469 int res;
2470
2471 control->owner = THIS_MODULE;
2472 control->class = I2C_CLASS_SPD;
2473 control->dev.parent = &adev->pdev->dev;
2474 control->algo = &navi10_i2c_algo;
2475 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2476
2477 res = i2c_add_adapter(control);
2478 if (res)
2479 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2480
2481 return res;
2482}
2483
2484static void navi10_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2485{
2486 i2c_del_adapter(control);
2487}
2488
2489
2490static const struct pptable_funcs navi10_ppt_funcs = {
2491 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
2492 .set_default_dpm_table = navi10_set_default_dpm_table,
2493 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
2494 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
2495 .i2c_init = navi10_i2c_control_init,
2496 .i2c_fini = navi10_i2c_control_fini,
2497 .print_clk_levels = navi10_print_clk_levels,
2498 .force_clk_levels = navi10_force_clk_levels,
2499 .populate_umd_state_clk = navi10_populate_umd_state_clk,
2500 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
2501 .pre_display_config_changed = navi10_pre_display_config_changed,
2502 .display_config_changed = navi10_display_config_changed,
2503 .notify_smc_display_config = navi10_notify_smc_display_config,
2504 .is_dpm_running = navi10_is_dpm_running,
2505 .get_fan_speed_percent = navi10_get_fan_speed_percent,
2506 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
2507 .get_power_profile_mode = navi10_get_power_profile_mode,
2508 .set_power_profile_mode = navi10_set_power_profile_mode,
2509 .set_watermarks_table = navi10_set_watermarks_table,
2510 .read_sensor = navi10_read_sensor,
2511 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
2512 .set_performance_level = smu_v11_0_set_performance_level,
2513 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
2514 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
2515 .get_power_limit = navi10_get_power_limit,
2516 .update_pcie_parameters = navi10_update_pcie_parameters,
2517 .init_microcode = smu_v11_0_init_microcode,
2518 .load_microcode = smu_v11_0_load_microcode,
2519 .fini_microcode = smu_v11_0_fini_microcode,
2520 .init_smc_tables = navi10_init_smc_tables,
2521 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2522 .init_power = smu_v11_0_init_power,
2523 .fini_power = smu_v11_0_fini_power,
2524 .check_fw_status = smu_v11_0_check_fw_status,
2525 .setup_pptable = navi10_setup_pptable,
2526 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2527 .check_fw_version = smu_v11_0_check_fw_version,
2528 .write_pptable = smu_cmn_write_pptable,
2529 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2530 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2531 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2532 .system_features_control = smu_v11_0_system_features_control,
2533 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2534 .send_smc_msg = smu_cmn_send_smc_msg,
2535 .init_display_count = smu_v11_0_init_display_count,
2536 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2537 .get_enabled_mask = smu_cmn_get_enabled_mask,
2538 .feature_is_enabled = smu_cmn_feature_is_enabled,
2539 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2540 .notify_display_change = smu_v11_0_notify_display_change,
2541 .set_power_limit = smu_v11_0_set_power_limit,
2542 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2543 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2544 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2545 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
2546 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2547 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2548 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2549 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2550 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2551 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2552 .gfx_off_control = smu_v11_0_gfx_off_control,
2553 .register_irq_handler = smu_v11_0_register_irq_handler,
2554 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2555 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2556 .baco_is_support= navi10_is_baco_supported,
2557 .baco_get_state = smu_v11_0_baco_get_state,
2558 .baco_set_state = smu_v11_0_baco_set_state,
2559 .baco_enter = smu_v11_0_baco_enter,
2560 .baco_exit = smu_v11_0_baco_exit,
2561 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2562 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2563 .set_default_od_settings = navi10_set_default_od_settings,
2564 .od_edit_dpm_table = navi10_od_edit_dpm_table,
2565 .run_btc = navi10_run_btc,
2566 .disable_umc_cdr_12gbps_workaround = navi10_disable_umc_cdr_12gbps_workaround,
2567 .set_power_source = smu_v11_0_set_power_source,
2568 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2569 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2570};
2571
2572void navi10_set_ppt_funcs(struct smu_context *smu)
2573{
2574 smu->ppt_funcs = &navi10_ppt_funcs;
2575 smu->message_map = navi10_message_map;
2576 smu->clock_map = navi10_clk_map;
2577 smu->feature_map = navi10_feature_mask_map;
2578 smu->table_map = navi10_table_map;
2579 smu->pwr_src_map = navi10_pwr_src_map;
2580 smu->workload_map = navi10_workload_map;
2581}
2582
