LXR linux/drivers/gpu/drm/i915/display/intel

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright © 2019 Intel Corporation
   4 */
   5
   6#ifndef __INTEL_CDCLK_H__
   7#define __INTEL_CDCLK_H__
   8
   9#include <linux/types.h>
  10
  11#include "i915_drv.h"
  12#include "intel_display.h"
  13#include "intel_global_state.h"
  14
  15struct drm_i915_private;
  16struct intel_atomic_state;
  17struct intel_crtc_state;
  18
  19struct intel_cdclk_vals {
  20        u16 refclk;
  21        u32 cdclk;
  22        u8 divider;     /* CD2X divider * 2 */
  23        u8 ratio;
  24};
  25
  26struct intel_cdclk_state {
  27        struct intel_global_state base;
  28
  29        /*
  30         * Logical configuration of cdclk (used for all scaling,
  31         * watermark, etc. calculations and checks). This is
  32         * computed as if all enabled crtcs were active.
  33         */
  34        struct intel_cdclk_config logical;
  35
  36        /*
  37         * Actual configuration of cdclk, can be different from the
  38         * logical configuration only when all crtc's are DPMS off.
  39         */
  40        struct intel_cdclk_config actual;
  41
  42        /* minimum acceptable cdclk for each pipe */
  43        int min_cdclk[I915_MAX_PIPES];
  44        /* minimum acceptable voltage level for each pipe */
  45        u8 min_voltage_level[I915_MAX_PIPES];
  46
  47        /* pipe to which cd2x update is synchronized */
  48        enum pipe pipe;
  49
  50        /* forced minimum cdclk for glk+ audio w/a */
  51        int force_min_cdclk;
  52        bool force_min_cdclk_changed;
  53
  54        /* bitmask of active pipes */
  55        u8 active_pipes;
  56};
  57
  58int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
  59void intel_cdclk_init_hw(struct drm_i915_private *i915);
  60void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
  61void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
  62void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
  63void intel_update_cdclk(struct drm_i915_private *dev_priv);
  64u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
  65bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
  66                               const struct intel_cdclk_config *b);
  67void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
  68void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
  69void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
  70                             const char *context);
  71int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
  72
  73struct intel_cdclk_state *
  74intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
  75
  76#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
  77#define intel_atomic_get_old_cdclk_state(state) \
  78        to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
  79#define intel_atomic_get_new_cdclk_state(state) \
  80        to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
  81
  82int intel_cdclk_init(struct drm_i915_private *dev_priv);
  83
  84#endif /* __INTEL_CDCLK_H__ */
  85