LXR linux/drivers/gpu/drm/i915/display/intel_dp_link

   1/*
   2 * Copyright © 2008-2015 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 */
  23
  24#include "intel_display_types.h"
  25#include "intel_dp.h"
  26#include "intel_dp_link_training.h"
  27
  28static void
  29intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  30{
  31
  32        DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  33                      link_status[0], link_status[1], link_status[2],
  34                      link_status[3], link_status[4], link_status[5]);
  35}
  36
  37static u8 dp_voltage_max(u8 preemph)
  38{
  39        switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
  40        case DP_TRAIN_PRE_EMPH_LEVEL_0:
  41                return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
  42        case DP_TRAIN_PRE_EMPH_LEVEL_1:
  43                return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
  44        case DP_TRAIN_PRE_EMPH_LEVEL_2:
  45                return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
  46        case DP_TRAIN_PRE_EMPH_LEVEL_3:
  47        default:
  48                return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
  49        }
  50}
  51
  52void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
  53                               const u8 link_status[DP_LINK_STATUS_SIZE])
  54{
  55        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
  56        u8 v = 0;
  57        u8 p = 0;
  58        int lane;
  59        u8 voltage_max;
  60        u8 preemph_max;
  61
  62        for (lane = 0; lane < intel_dp->lane_count; lane++) {
  63                v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
  64                p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
  65        }
  66
  67        preemph_max = intel_dp->preemph_max(intel_dp);
  68        drm_WARN_ON_ONCE(&i915->drm,
  69                         preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
  70                         preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
  71
  72        if (p >= preemph_max)
  73                p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  74
  75        v = min(v, dp_voltage_max(p));
  76
  77        voltage_max = intel_dp->voltage_max(intel_dp);
  78        drm_WARN_ON_ONCE(&i915->drm,
  79                         voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
  80                         voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
  81
  82        if (v >= voltage_max)
  83                v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  84
  85        for (lane = 0; lane < 4; lane++)
  86                intel_dp->train_set[lane] = v | p;
  87}
  88
  89static bool
  90intel_dp_set_link_train(struct intel_dp *intel_dp,
  91                        u8 dp_train_pat)
  92{
  93        u8 buf[sizeof(intel_dp->train_set) + 1];
  94        int ret, len;
  95
  96        intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
  97
  98        buf[0] = dp_train_pat;
  99        if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
 100            DP_TRAINING_PATTERN_DISABLE) {
 101                /* don't write DP_TRAINING_LANEx_SET on disable */
 102                len = 1;
 103        } else {
 104                /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
 105                memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
 106                len = intel_dp->lane_count + 1;
 107        }
 108
 109        ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
 110                                buf, len);
 111
 112        return ret == len;
 113}
 114
 115static bool
 116intel_dp_reset_link_train(struct intel_dp *intel_dp,
 117                        u8 dp_train_pat)
 118{
 119        memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 120        intel_dp_set_signal_levels(intel_dp);
 121        return intel_dp_set_link_train(intel_dp, dp_train_pat);
 122}
 123
 124static bool
 125intel_dp_update_link_train(struct intel_dp *intel_dp)
 126{
 127        int ret;
 128
 129        intel_dp_set_signal_levels(intel_dp);
 130
 131        ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
 132                                intel_dp->train_set, intel_dp->lane_count);
 133
 134        return ret == intel_dp->lane_count;
 135}
 136
 137static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
 138{
 139        int lane;
 140
 141        for (lane = 0; lane < intel_dp->lane_count; lane++)
 142                if ((intel_dp->train_set[lane] &
 143                     DP_TRAIN_MAX_SWING_REACHED) == 0)
 144                        return false;
 145
 146        return true;
 147}
 148
 149/* Enable corresponding port and start training pattern 1 */
 150static bool
 151intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
 152{
 153        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 154        u8 voltage;
 155        int voltage_tries, cr_tries, max_cr_tries;
 156        bool max_vswing_reached = false;
 157        u8 link_config[2];
 158        u8 link_bw, rate_select;
 159
 160        if (intel_dp->prepare_link_retrain)
 161                intel_dp->prepare_link_retrain(intel_dp);
 162
 163        intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
 164                              &link_bw, &rate_select);
 165
 166        if (link_bw)
 167                drm_dbg_kms(&i915->drm,
 168                            "Using LINK_BW_SET value %02x\n", link_bw);
 169        else
 170                drm_dbg_kms(&i915->drm,
 171                            "Using LINK_RATE_SET value %02x\n", rate_select);
 172
 173        /* Write the link configuration data */
 174        link_config[0] = link_bw;
 175        link_config[1] = intel_dp->lane_count;
 176        if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 177                link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 178        drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 179
 180        /* eDP 1.4 rate select method. */
 181        if (!link_bw)
 182                drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 183                                  &rate_select, 1);
 184
 185        link_config[0] = 0;
 186        link_config[1] = DP_SET_ANSI_8B10B;
 187        drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 188
 189        intel_dp->DP |= DP_PORT_EN;
 190
 191        /* clock recovery */
 192        if (!intel_dp_reset_link_train(intel_dp,
 193                                       DP_TRAINING_PATTERN_1 |
 194                                       DP_LINK_SCRAMBLING_DISABLE)) {
 195                drm_err(&i915->drm, "failed to enable link training\n");
 196                return false;
 197        }
 198
 199        /*
 200         * The DP 1.4 spec defines the max clock recovery retries value
 201         * as 10 but for pre-DP 1.4 devices we set a very tolerant
 202         * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 203         * x 5 identical voltage retries). Since the previous specs didn't
 204         * define a limit and created the possibility of an infinite loop
 205         * we want to prevent any sync from triggering that corner case.
 206         */
 207        if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 208                max_cr_tries = 10;
 209        else
 210                max_cr_tries = 80;
 211
 212        voltage_tries = 1;
 213        for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 214                u8 link_status[DP_LINK_STATUS_SIZE];
 215
 216                drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 217
 218                if (!intel_dp_get_link_status(intel_dp, link_status)) {
 219                        drm_err(&i915->drm, "failed to get link status\n");
 220                        return false;
 221                }
 222
 223                if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
 224                        drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 225                        return true;
 226                }
 227
 228                if (voltage_tries == 5) {
 229                        drm_dbg_kms(&i915->drm,
 230                                    "Same voltage tried 5 times\n");
 231                        return false;
 232                }
 233
 234                if (max_vswing_reached) {
 235                        drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
 236                        return false;
 237                }
 238
 239                voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 240
 241                /* Update training set as requested by target */
 242                intel_dp_get_adjust_train(intel_dp, link_status);
 243                if (!intel_dp_update_link_train(intel_dp)) {
 244                        drm_err(&i915->drm,
 245                                "failed to update link training\n");
 246                        return false;
 247                }
 248
 249                if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 250                    voltage)
 251                        ++voltage_tries;
 252                else
 253                        voltage_tries = 1;
 254
 255                if (intel_dp_link_max_vswing_reached(intel_dp))
 256                        max_vswing_reached = true;
 257
 258        }
 259        drm_err(&i915->drm,
 260                "Failed clock recovery %d times, giving up!\n", max_cr_tries);
 261        return false;
 262}
 263
 264/*
 265 * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 266 * or for 1.4 devices that support it, training Pattern 3 for HBR2
 267 * or 1.2 devices that support it, Training Pattern 2 otherwise.
 268 */
 269static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
 270{
 271        bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 272
 273        /*
 274         * Intel platforms that support HBR3 also support TPS4. It is mandatory
 275         * for all downstream devices that support HBR3. There are no known eDP
 276         * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 277         * specification.
 278         */
 279        source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 280        sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
 281        if (source_tps4 && sink_tps4) {
 282                return DP_TRAINING_PATTERN_4;
 283        } else if (intel_dp->link_rate == 810000) {
 284                if (!source_tps4)
 285                        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 286                                    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
 287                if (!sink_tps4)
 288                        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 289                                    "8.1 Gbps link rate without sink TPS4 support\n");
 290        }
 291        /*
 292         * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 293         * also mandatory for downstream devices that support HBR2. However, not
 294         * all sinks follow the spec.
 295         */
 296        source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 297        sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
 298        if (source_tps3 && sink_tps3) {
 299                return  DP_TRAINING_PATTERN_3;
 300        } else if (intel_dp->link_rate >= 540000) {
 301                if (!source_tps3)
 302                        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 303                                    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 304                if (!sink_tps3)
 305                        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 306                                    ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 307        }
 308
 309        return DP_TRAINING_PATTERN_2;
 310}
 311
 312static bool
 313intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
 314{
 315        struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 316        int tries;
 317        u32 training_pattern;
 318        u8 link_status[DP_LINK_STATUS_SIZE];
 319        bool channel_eq = false;
 320
 321        training_pattern = intel_dp_training_pattern(intel_dp);
 322        /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 323        if (training_pattern != DP_TRAINING_PATTERN_4)
 324                training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 325
 326        /* channel equalization */
 327        if (!intel_dp_set_link_train(intel_dp,
 328                                     training_pattern)) {
 329                drm_err(&i915->drm, "failed to start channel equalization\n");
 330                return false;
 331        }
 332
 333        for (tries = 0; tries < 5; tries++) {
 334
 335                drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 336                if (!intel_dp_get_link_status(intel_dp, link_status)) {
 337                        drm_err(&i915->drm,
 338                                "failed to get link status\n");
 339                        break;
 340                }
 341
 342                /* Make sure clock is still ok */
 343                if (!drm_dp_clock_recovery_ok(link_status,
 344                                              intel_dp->lane_count)) {
 345                        intel_dp_dump_link_status(link_status);
 346                        drm_dbg_kms(&i915->drm,
 347                                    "Clock recovery check failed, cannot "
 348                                    "continue channel equalization\n");
 349                        break;
 350                }
 351
 352                if (drm_dp_channel_eq_ok(link_status,
 353                                         intel_dp->lane_count)) {
 354                        channel_eq = true;
 355                        drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 356                                    "successful\n");
 357                        break;
 358                }
 359
 360                /* Update training set as requested by target */
 361                intel_dp_get_adjust_train(intel_dp, link_status);
 362                if (!intel_dp_update_link_train(intel_dp)) {
 363                        drm_err(&i915->drm,
 364                                "failed to update link training\n");
 365                        break;
 366                }
 367        }
 368
 369        /* Try 5 times, else fail and try at lower BW */
 370        if (tries == 5) {
 371                intel_dp_dump_link_status(link_status);
 372                drm_dbg_kms(&i915->drm,
 373                            "Channel equalization failed 5 times\n");
 374        }
 375
 376        intel_dp_set_idle_link_train(intel_dp);
 377
 378        return channel_eq;
 379
 380}
 381
 382void intel_dp_stop_link_train(struct intel_dp *intel_dp)
 383{
 384        intel_dp->link_trained = true;
 385
 386        intel_dp_set_link_train(intel_dp,
 387                                DP_TRAINING_PATTERN_DISABLE);
 388}
 389
 390void
 391intel_dp_start_link_train(struct intel_dp *intel_dp)
 392{
 393        struct intel_connector *intel_connector = intel_dp->attached_connector;
 394
 395        if (!intel_dp_link_training_clock_recovery(intel_dp))
 396                goto failure_handling;
 397        if (!intel_dp_link_training_channel_equalization(intel_dp))
 398                goto failure_handling;
 399
 400        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 401                    "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
 402                    intel_connector->base.base.id,
 403                    intel_connector->base.name,
 404                    intel_dp->link_rate, intel_dp->lane_count);
 405        return;
 406
 407 failure_handling:
 408        drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 409                    "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
 410                    intel_connector->base.base.id,
 411                    intel_connector->base.name,
 412                    intel_dp->link_rate, intel_dp->lane_count);
 413        if (!intel_dp_get_link_train_fallback_values(intel_dp,
 414                                                     intel_dp->link_rate,
 415                                                     intel_dp->lane_count))
 416                /* Schedule a Hotplug Uevent to userspace to start modeset */
 417                schedule_work(&intel_connector->modeset_retry_work);
 418        return;
 419}
 420