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24#include "display/intel_dp.h"
25
26#include "intel_display_types.h"
27#include "intel_dpio_phy.h"
28#include "intel_sideband.h"
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123
124struct bxt_ddi_phy_info {
125
126
127
128 bool dual_channel;
129
130
131
132
133
134
135 enum dpio_phy rcomp_phy;
136
137
138
139
140
141 int reset_delay;
142
143
144
145
146
147 u32 pwron_mask;
148
149
150
151
152 struct {
153
154
155
156 enum port port;
157 } channel[2];
158};
159
160static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
161 [DPIO_PHY0] = {
162 .dual_channel = true,
163 .rcomp_phy = DPIO_PHY1,
164 .pwron_mask = BIT(0),
165
166 .channel = {
167 [DPIO_CH0] = { .port = PORT_B },
168 [DPIO_CH1] = { .port = PORT_C },
169 }
170 },
171 [DPIO_PHY1] = {
172 .dual_channel = false,
173 .rcomp_phy = -1,
174 .pwron_mask = BIT(1),
175
176 .channel = {
177 [DPIO_CH0] = { .port = PORT_A },
178 }
179 },
180};
181
182static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
183 [DPIO_PHY0] = {
184 .dual_channel = false,
185 .rcomp_phy = DPIO_PHY1,
186 .pwron_mask = BIT(0),
187 .reset_delay = 20,
188
189 .channel = {
190 [DPIO_CH0] = { .port = PORT_B },
191 }
192 },
193 [DPIO_PHY1] = {
194 .dual_channel = false,
195 .rcomp_phy = -1,
196 .pwron_mask = BIT(3),
197 .reset_delay = 20,
198
199 .channel = {
200 [DPIO_CH0] = { .port = PORT_A },
201 }
202 },
203 [DPIO_PHY2] = {
204 .dual_channel = false,
205 .rcomp_phy = DPIO_PHY1,
206 .pwron_mask = BIT(1),
207 .reset_delay = 20,
208
209 .channel = {
210 [DPIO_CH0] = { .port = PORT_C },
211 }
212 },
213};
214
215static const struct bxt_ddi_phy_info *
216bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
217{
218 if (IS_GEMINILAKE(dev_priv)) {
219 *count = ARRAY_SIZE(glk_ddi_phy_info);
220 return glk_ddi_phy_info;
221 } else {
222 *count = ARRAY_SIZE(bxt_ddi_phy_info);
223 return bxt_ddi_phy_info;
224 }
225}
226
227static const struct bxt_ddi_phy_info *
228bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
229{
230 int count;
231 const struct bxt_ddi_phy_info *phy_list =
232 bxt_get_phy_list(dev_priv, &count);
233
234 return &phy_list[phy];
235}
236
237void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
238 enum dpio_phy *phy, enum dpio_channel *ch)
239{
240 const struct bxt_ddi_phy_info *phy_info, *phys;
241 int i, count;
242
243 phys = bxt_get_phy_list(dev_priv, &count);
244
245 for (i = 0; i < count; i++) {
246 phy_info = &phys[i];
247
248 if (port == phy_info->channel[DPIO_CH0].port) {
249 *phy = i;
250 *ch = DPIO_CH0;
251 return;
252 }
253
254 if (phy_info->dual_channel &&
255 port == phy_info->channel[DPIO_CH1].port) {
256 *phy = i;
257 *ch = DPIO_CH1;
258 return;
259 }
260 }
261
262 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
263 port_name(port));
264 *phy = DPIO_PHY0;
265 *ch = DPIO_CH0;
266}
267
268void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
269 enum port port, u32 margin, u32 scale,
270 u32 enable, u32 deemphasis)
271{
272 u32 val;
273 enum dpio_phy phy;
274 enum dpio_channel ch;
275
276 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
277
278
279
280
281
282 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
283 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
284 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
285
286 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
287 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
288 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
289 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
290
291 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
292 val &= ~SCALE_DCOMP_METHOD;
293 if (enable)
294 val |= SCALE_DCOMP_METHOD;
295
296 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
297 drm_err(&dev_priv->drm,
298 "Disabled scaling while ouniqetrangenmethod was set");
299
300 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
301
302 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
303 val &= ~DE_EMPHASIS;
304 val |= deemphasis << DEEMPH_SHIFT;
305 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
306
307 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
308 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
309 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
310}
311
312bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
313 enum dpio_phy phy)
314{
315 const struct bxt_ddi_phy_info *phy_info;
316
317 phy_info = bxt_get_phy_info(dev_priv, phy);
318
319 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
320 return false;
321
322 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
323 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
324 drm_dbg(&dev_priv->drm,
325 "DDI PHY %d powered, but power hasn't settled\n", phy);
326
327 return false;
328 }
329
330 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
331 drm_dbg(&dev_priv->drm,
332 "DDI PHY %d powered, but still in reset\n", phy);
333
334 return false;
335 }
336
337 return true;
338}
339
340static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
341{
342 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
343
344 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
345}
346
347static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
348 enum dpio_phy phy)
349{
350 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
351 GRC_DONE, 10))
352 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
353 phy);
354}
355
356static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
357 enum dpio_phy phy)
358{
359 const struct bxt_ddi_phy_info *phy_info;
360 u32 val;
361
362 phy_info = bxt_get_phy_info(dev_priv, phy);
363
364 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
365
366 if (phy_info->rcomp_phy != -1)
367 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
368
369 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
370 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
371 "won't reprogram it\n", phy);
372 return;
373 }
374
375 drm_dbg(&dev_priv->drm,
376 "DDI PHY %d enabled with invalid state, "
377 "force reprogramming it\n", phy);
378 }
379
380 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
381 val |= phy_info->pwron_mask;
382 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
383
384
385
386
387
388
389
390
391
392 if (intel_wait_for_register_fw(&dev_priv->uncore,
393 BXT_PORT_CL1CM_DW0(phy),
394 PHY_RESERVED | PHY_POWER_GOOD,
395 PHY_POWER_GOOD,
396 1))
397 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
398 phy);
399
400
401 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy));
402 val &= ~IREF0RC_OFFSET_MASK;
403 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
404 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val);
405
406 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy));
407 val &= ~IREF1RC_OFFSET_MASK;
408 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
409 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val);
410
411
412 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy));
413 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
414 SUS_CLK_CONFIG;
415 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val);
416
417 if (phy_info->dual_channel) {
418 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy));
419 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
420 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val);
421 }
422
423 if (phy_info->rcomp_phy != -1) {
424 u32 grc_code;
425
426 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
427
428
429
430
431
432
433 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
434 phy_info->rcomp_phy);
435 grc_code = val << GRC_CODE_FAST_SHIFT |
436 val << GRC_CODE_SLOW_SHIFT |
437 val;
438 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
439
440 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy));
441 val |= GRC_DIS | GRC_RDY_OVRD;
442 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val);
443 }
444
445 if (phy_info->reset_delay)
446 udelay(phy_info->reset_delay);
447
448 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
449 val |= COMMON_RESET_DIS;
450 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
451}
452
453void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
454{
455 const struct bxt_ddi_phy_info *phy_info;
456 u32 val;
457
458 phy_info = bxt_get_phy_info(dev_priv, phy);
459
460 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
461 val &= ~COMMON_RESET_DIS;
462 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
463
464 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
465 val &= ~phy_info->pwron_mask;
466 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
467}
468
469void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
470{
471 const struct bxt_ddi_phy_info *phy_info =
472 bxt_get_phy_info(dev_priv, phy);
473 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
474 bool was_enabled;
475
476 lockdep_assert_held(&dev_priv->power_domains.lock);
477
478 was_enabled = true;
479 if (rcomp_phy != -1)
480 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
481
482
483
484
485
486 if (!was_enabled)
487 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
488
489 _bxt_ddi_phy_init(dev_priv, phy);
490
491 if (!was_enabled)
492 bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
493}
494
495static bool __printf(6, 7)
496__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
497 i915_reg_t reg, u32 mask, u32 expected,
498 const char *reg_fmt, ...)
499{
500 struct va_format vaf;
501 va_list args;
502 u32 val;
503
504 val = intel_de_read(dev_priv, reg);
505 if ((val & mask) == expected)
506 return true;
507
508 va_start(args, reg_fmt);
509 vaf.fmt = reg_fmt;
510 vaf.va = &args;
511
512 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
513 "current %08x, expected %08x (mask %08x)\n",
514 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
515 mask);
516
517 va_end(args);
518
519 return false;
520}
521
522bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
523 enum dpio_phy phy)
524{
525 const struct bxt_ddi_phy_info *phy_info;
526 u32 mask;
527 bool ok;
528
529 phy_info = bxt_get_phy_info(dev_priv, phy);
530
531#define _CHK(reg, mask, exp, fmt, ...) \
532 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
533 ## __VA_ARGS__)
534
535 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
536 return false;
537
538 ok = true;
539
540
541 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
542 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
543 "BXT_PORT_CL1CM_DW9(%d)", phy);
544 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
545 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
546 "BXT_PORT_CL1CM_DW10(%d)", phy);
547
548
549 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
550 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
551 "BXT_PORT_CL1CM_DW28(%d)", phy);
552
553 if (phy_info->dual_channel)
554 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
555 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
556 "BXT_PORT_CL2CM_DW6(%d)", phy);
557
558 if (phy_info->rcomp_phy != -1) {
559 u32 grc_code = dev_priv->bxt_phy_grc;
560
561 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
562 grc_code << GRC_CODE_SLOW_SHIFT |
563 grc_code;
564 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
565 GRC_CODE_NOM_MASK;
566 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
567 "BXT_PORT_REF_DW6(%d)", phy);
568
569 mask = GRC_DIS | GRC_RDY_OVRD;
570 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
571 "BXT_PORT_REF_DW8(%d)", phy);
572 }
573
574 return ok;
575#undef _CHK
576}
577
578u8
579bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
580{
581 switch (lane_count) {
582 case 1:
583 return 0;
584 case 2:
585 return BIT(2) | BIT(0);
586 case 4:
587 return BIT(3) | BIT(2) | BIT(0);
588 default:
589 MISSING_CASE(lane_count);
590
591 return 0;
592 }
593}
594
595void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
596 u8 lane_lat_optim_mask)
597{
598 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
599 enum port port = encoder->port;
600 enum dpio_phy phy;
601 enum dpio_channel ch;
602 int lane;
603
604 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
605
606 for (lane = 0; lane < 4; lane++) {
607 u32 val = intel_de_read(dev_priv,
608 BXT_PORT_TX_DW14_LN(phy, ch, lane));
609
610
611
612
613
614 val &= ~LATENCY_OPTIM;
615 if (lane_lat_optim_mask & BIT(lane))
616 val |= LATENCY_OPTIM;
617
618 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
619 val);
620 }
621}
622
623u8
624bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
625{
626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
627 enum port port = encoder->port;
628 enum dpio_phy phy;
629 enum dpio_channel ch;
630 int lane;
631 u8 mask;
632
633 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
634
635 mask = 0;
636 for (lane = 0; lane < 4; lane++) {
637 u32 val = intel_de_read(dev_priv,
638 BXT_PORT_TX_DW14_LN(phy, ch, lane));
639
640 if (val & LATENCY_OPTIM)
641 mask |= BIT(lane);
642 }
643
644 return mask;
645}
646
647
648void chv_set_phy_signal_level(struct intel_encoder *encoder,
649 u32 deemph_reg_value, u32 margin_reg_value,
650 bool uniq_trans_scale)
651{
652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
653 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
654 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
655 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
656 enum pipe pipe = intel_crtc->pipe;
657 u32 val;
658 int i;
659
660 vlv_dpio_get(dev_priv);
661
662
663 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
664 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
665 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
666 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
667 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
668
669 if (intel_crtc->config->lane_count > 2) {
670 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
671 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
672 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
673 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
674 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
675 }
676
677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
678 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
679 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
680 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
681
682 if (intel_crtc->config->lane_count > 2) {
683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
684 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
685 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
686 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
687 }
688
689
690 for (i = 0; i < intel_crtc->config->lane_count; i++) {
691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
692 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
693 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
694 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
695 }
696
697
698 for (i = 0; i < intel_crtc->config->lane_count; i++) {
699 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
700
701 val &= ~DPIO_SWING_MARGIN000_MASK;
702 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
703
704
705
706
707
708
709 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
710 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
711
712 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
713 }
714
715
716
717
718
719
720
721 for (i = 0; i < intel_crtc->config->lane_count; i++) {
722 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
723 if (uniq_trans_scale)
724 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
725 else
726 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
727 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
728 }
729
730
731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
732 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
733 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
734
735 if (intel_crtc->config->lane_count > 2) {
736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
737 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
739 }
740
741 vlv_dpio_put(dev_priv);
742}
743
744void chv_data_lane_soft_reset(struct intel_encoder *encoder,
745 const struct intel_crtc_state *crtc_state,
746 bool reset)
747{
748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
749 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
751 enum pipe pipe = crtc->pipe;
752 u32 val;
753
754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
755 if (reset)
756 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
757 else
758 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
759 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
760
761 if (crtc_state->lane_count > 2) {
762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
763 if (reset)
764 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
765 else
766 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
767 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
768 }
769
770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
771 val |= CHV_PCS_REQ_SOFTRESET_EN;
772 if (reset)
773 val &= ~DPIO_PCS_CLK_SOFT_RESET;
774 else
775 val |= DPIO_PCS_CLK_SOFT_RESET;
776 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
777
778 if (crtc_state->lane_count > 2) {
779 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
780 val |= CHV_PCS_REQ_SOFTRESET_EN;
781 if (reset)
782 val &= ~DPIO_PCS_CLK_SOFT_RESET;
783 else
784 val |= DPIO_PCS_CLK_SOFT_RESET;
785 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
786 }
787}
788
789void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
790 const struct intel_crtc_state *crtc_state)
791{
792 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
795 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
796 enum pipe pipe = crtc->pipe;
797 unsigned int lane_mask =
798 intel_dp_unused_lane_mask(crtc_state->lane_count);
799 u32 val;
800
801
802
803
804
805 if (ch == DPIO_CH0 && pipe == PIPE_B)
806 dig_port->release_cl2_override =
807 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
808
809 chv_phy_powergate_lanes(encoder, true, lane_mask);
810
811 vlv_dpio_get(dev_priv);
812
813
814 chv_data_lane_soft_reset(encoder, crtc_state, true);
815
816
817 if (pipe != PIPE_B) {
818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
819 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
820 if (ch == DPIO_CH0)
821 val |= CHV_BUFLEFTENA1_FORCE;
822 if (ch == DPIO_CH1)
823 val |= CHV_BUFRIGHTENA1_FORCE;
824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
825 } else {
826 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
827 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
828 if (ch == DPIO_CH0)
829 val |= CHV_BUFLEFTENA2_FORCE;
830 if (ch == DPIO_CH1)
831 val |= CHV_BUFRIGHTENA2_FORCE;
832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
833 }
834
835
836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
837 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
838 if (pipe != PIPE_B)
839 val &= ~CHV_PCS_USEDCLKCHANNEL;
840 else
841 val |= CHV_PCS_USEDCLKCHANNEL;
842 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
843
844 if (crtc_state->lane_count > 2) {
845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
846 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
847 if (pipe != PIPE_B)
848 val &= ~CHV_PCS_USEDCLKCHANNEL;
849 else
850 val |= CHV_PCS_USEDCLKCHANNEL;
851 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
852 }
853
854
855
856
857
858
859 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
860 if (pipe != PIPE_B)
861 val &= ~CHV_CMN_USEDCLKCHANNEL;
862 else
863 val |= CHV_CMN_USEDCLKCHANNEL;
864 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
865
866 vlv_dpio_put(dev_priv);
867}
868
869void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
870 const struct intel_crtc_state *crtc_state)
871{
872 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
873 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
876 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
877 enum pipe pipe = crtc->pipe;
878 int data, i, stagger;
879 u32 val;
880
881 vlv_dpio_get(dev_priv);
882
883
884 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
885 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
886 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
887
888 if (crtc_state->lane_count > 2) {
889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
890 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
891 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
892 }
893
894
895 for (i = 0; i < crtc_state->lane_count; i++) {
896
897 if (crtc_state->lane_count == 1)
898 data = 0x0;
899 else
900 data = (i == 1) ? 0x0 : 0x1;
901 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
902 data << DPIO_UPAR_SHIFT);
903 }
904
905
906 if (crtc_state->port_clock > 270000)
907 stagger = 0x18;
908 else if (crtc_state->port_clock > 135000)
909 stagger = 0xd;
910 else if (crtc_state->port_clock > 67500)
911 stagger = 0x7;
912 else if (crtc_state->port_clock > 33750)
913 stagger = 0x4;
914 else
915 stagger = 0x2;
916
917 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
918 val |= DPIO_TX2_STAGGER_MASK(0x1f);
919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
920
921 if (crtc_state->lane_count > 2) {
922 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
923 val |= DPIO_TX2_STAGGER_MASK(0x1f);
924 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
925 }
926
927 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
928 DPIO_LANESTAGGER_STRAP(stagger) |
929 DPIO_LANESTAGGER_STRAP_OVRD |
930 DPIO_TX1_STAGGER_MASK(0x1f) |
931 DPIO_TX1_STAGGER_MULT(6) |
932 DPIO_TX2_STAGGER_MULT(0));
933
934 if (crtc_state->lane_count > 2) {
935 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
936 DPIO_LANESTAGGER_STRAP(stagger) |
937 DPIO_LANESTAGGER_STRAP_OVRD |
938 DPIO_TX1_STAGGER_MASK(0x1f) |
939 DPIO_TX1_STAGGER_MULT(7) |
940 DPIO_TX2_STAGGER_MULT(5));
941 }
942
943
944 chv_data_lane_soft_reset(encoder, crtc_state, false);
945
946 vlv_dpio_put(dev_priv);
947}
948
949void chv_phy_release_cl2_override(struct intel_encoder *encoder)
950{
951 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
952 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
953
954 if (dig_port->release_cl2_override) {
955 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
956 dig_port->release_cl2_override = false;
957 }
958}
959
960void chv_phy_post_pll_disable(struct intel_encoder *encoder,
961 const struct intel_crtc_state *old_crtc_state)
962{
963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
964 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
965 u32 val;
966
967 vlv_dpio_get(dev_priv);
968
969
970 if (pipe != PIPE_B) {
971 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
972 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
973 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
974 } else {
975 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
976 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
977 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
978 }
979
980 vlv_dpio_put(dev_priv);
981
982
983
984
985
986
987
988
989
990
991 chv_phy_powergate_lanes(encoder, false, 0x0);
992}
993
994void vlv_set_phy_signal_level(struct intel_encoder *encoder,
995 u32 demph_reg_value, u32 preemph_reg_value,
996 u32 uniqtranscale_reg_value, u32 tx3_demph)
997{
998 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
999 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1000 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1001 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1002 enum pipe pipe = intel_crtc->pipe;
1003
1004 vlv_dpio_get(dev_priv);
1005
1006 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1007 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1009 uniqtranscale_reg_value);
1010 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1011
1012 if (tx3_demph)
1013 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1014
1015 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1016 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1018
1019 vlv_dpio_put(dev_priv);
1020}
1021
1022void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1023 const struct intel_crtc_state *crtc_state)
1024{
1025 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1027 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1028 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1029 enum pipe pipe = crtc->pipe;
1030
1031
1032 vlv_dpio_get(dev_priv);
1033
1034 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1035 DPIO_PCS_TX_LANE2_RESET |
1036 DPIO_PCS_TX_LANE1_RESET);
1037 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1038 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1039 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1040 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1041 DPIO_PCS_CLK_SOFT_RESET);
1042
1043
1044 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1045 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1046 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1047
1048 vlv_dpio_put(dev_priv);
1049}
1050
1051void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1052 const struct intel_crtc_state *crtc_state)
1053{
1054 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1055 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1057 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1058 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1059 enum pipe pipe = crtc->pipe;
1060 u32 val;
1061
1062 vlv_dpio_get(dev_priv);
1063
1064
1065 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1066 val = 0;
1067 if (pipe)
1068 val |= (1<<21);
1069 else
1070 val &= ~(1<<21);
1071 val |= 0x001000c4;
1072 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1073
1074
1075 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1076 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1077
1078 vlv_dpio_put(dev_priv);
1079}
1080
1081void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1082 const struct intel_crtc_state *old_crtc_state)
1083{
1084 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1085 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1086 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1087 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1088 enum pipe pipe = crtc->pipe;
1089
1090 vlv_dpio_get(dev_priv);
1091 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1093 vlv_dpio_put(dev_priv);
1094}
1095