linux/drivers/gpu/drm/i915/display/intel_lvds.c
<<
>>
Prefs
   1/*
   2 * Copyright © 2006-2007 Intel Corporation
   3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors:
  25 *      Eric Anholt <eric@anholt.net>
  26 *      Dave Airlie <airlied@linux.ie>
  27 *      Jesse Barnes <jesse.barnes@intel.com>
  28 */
  29
  30#include <acpi/button.h>
  31#include <linux/acpi.h>
  32#include <linux/dmi.h>
  33#include <linux/i2c.h>
  34#include <linux/slab.h>
  35#include <linux/vga_switcheroo.h>
  36
  37#include <drm/drm_atomic_helper.h>
  38#include <drm/drm_crtc.h>
  39#include <drm/drm_edid.h>
  40
  41#include "i915_drv.h"
  42#include "intel_atomic.h"
  43#include "intel_connector.h"
  44#include "intel_display_types.h"
  45#include "intel_gmbus.h"
  46#include "intel_lvds.h"
  47#include "intel_panel.h"
  48
  49/* Private structure for the integrated LVDS support */
  50struct intel_lvds_pps {
  51        /* 100us units */
  52        int t1_t2;
  53        int t3;
  54        int t4;
  55        int t5;
  56        int tx;
  57
  58        int divider;
  59
  60        int port;
  61        bool powerdown_on_reset;
  62};
  63
  64struct intel_lvds_encoder {
  65        struct intel_encoder base;
  66
  67        bool is_dual_link;
  68        i915_reg_t reg;
  69        u32 a3_power;
  70
  71        struct intel_lvds_pps init_pps;
  72        u32 init_lvds_val;
  73
  74        struct intel_connector *attached_connector;
  75};
  76
  77static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  78{
  79        return container_of(encoder, struct intel_lvds_encoder, base.base);
  80}
  81
  82bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
  83                             i915_reg_t lvds_reg, enum pipe *pipe)
  84{
  85        u32 val;
  86
  87        val = intel_de_read(dev_priv, lvds_reg);
  88
  89        /* asserts want to know the pipe even if the port is disabled */
  90        if (HAS_PCH_CPT(dev_priv))
  91                *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
  92        else
  93                *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
  94
  95        return val & LVDS_PORT_EN;
  96}
  97
  98static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  99                                    enum pipe *pipe)
 100{
 101        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 102        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 103        intel_wakeref_t wakeref;
 104        bool ret;
 105
 106        wakeref = intel_display_power_get_if_enabled(dev_priv,
 107                                                     encoder->power_domain);
 108        if (!wakeref)
 109                return false;
 110
 111        ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
 112
 113        intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 114
 115        return ret;
 116}
 117
 118static void intel_lvds_get_config(struct intel_encoder *encoder,
 119                                  struct intel_crtc_state *pipe_config)
 120{
 121        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 122        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 123        u32 tmp, flags = 0;
 124
 125        pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 126
 127        tmp = intel_de_read(dev_priv, lvds_encoder->reg);
 128        if (tmp & LVDS_HSYNC_POLARITY)
 129                flags |= DRM_MODE_FLAG_NHSYNC;
 130        else
 131                flags |= DRM_MODE_FLAG_PHSYNC;
 132        if (tmp & LVDS_VSYNC_POLARITY)
 133                flags |= DRM_MODE_FLAG_NVSYNC;
 134        else
 135                flags |= DRM_MODE_FLAG_PVSYNC;
 136
 137        pipe_config->hw.adjusted_mode.flags |= flags;
 138
 139        if (INTEL_GEN(dev_priv) < 5)
 140                pipe_config->gmch_pfit.lvds_border_bits =
 141                        tmp & LVDS_BORDER_ENABLE;
 142
 143        /* gen2/3 store dither state in pfit control, needs to match */
 144        if (INTEL_GEN(dev_priv) < 4) {
 145                tmp = intel_de_read(dev_priv, PFIT_CONTROL);
 146
 147                pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 148        }
 149
 150        pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 151}
 152
 153static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 154                                        struct intel_lvds_pps *pps)
 155{
 156        u32 val;
 157
 158        pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET;
 159
 160        val = intel_de_read(dev_priv, PP_ON_DELAYS(0));
 161        pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
 162        pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
 163        pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
 164
 165        val = intel_de_read(dev_priv, PP_OFF_DELAYS(0));
 166        pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
 167        pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
 168
 169        val = intel_de_read(dev_priv, PP_DIVISOR(0));
 170        pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
 171        val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
 172        /*
 173         * Remove the BSpec specified +1 (100ms) offset that accounts for a
 174         * too short power-cycle delay due to the asynchronous programming of
 175         * the register.
 176         */
 177        if (val)
 178                val--;
 179        /* Convert from 100ms to 100us units */
 180        pps->t4 = val * 1000;
 181
 182        if (INTEL_GEN(dev_priv) <= 4 &&
 183            pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 184                drm_dbg_kms(&dev_priv->drm,
 185                            "Panel power timings uninitialized, "
 186                            "setting defaults\n");
 187                /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 188                pps->t1_t2 = 40 * 10;
 189                pps->t5 = 200 * 10;
 190                /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 191                pps->t3 = 35 * 10;
 192                pps->tx = 200 * 10;
 193        }
 194
 195        drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 196                "divider %d port %d powerdown_on_reset %d\n",
 197                pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 198                pps->divider, pps->port, pps->powerdown_on_reset);
 199}
 200
 201static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 202                                   struct intel_lvds_pps *pps)
 203{
 204        u32 val;
 205
 206        val = intel_de_read(dev_priv, PP_CONTROL(0));
 207        drm_WARN_ON(&dev_priv->drm,
 208                    (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 209        if (pps->powerdown_on_reset)
 210                val |= PANEL_POWER_RESET;
 211        intel_de_write(dev_priv, PP_CONTROL(0), val);
 212
 213        intel_de_write(dev_priv, PP_ON_DELAYS(0),
 214                       REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
 215
 216        intel_de_write(dev_priv, PP_OFF_DELAYS(0),
 217                       REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
 218
 219        intel_de_write(dev_priv, PP_DIVISOR(0),
 220                       REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
 221}
 222
 223static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 224                                  struct intel_encoder *encoder,
 225                                  const struct intel_crtc_state *pipe_config,
 226                                  const struct drm_connector_state *conn_state)
 227{
 228        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 229        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 230        struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 231        const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 232        enum pipe pipe = crtc->pipe;
 233        u32 temp;
 234
 235        if (HAS_PCH_SPLIT(dev_priv)) {
 236                assert_fdi_rx_pll_disabled(dev_priv, pipe);
 237                assert_shared_dpll_disabled(dev_priv,
 238                                            pipe_config->shared_dpll);
 239        } else {
 240                assert_pll_disabled(dev_priv, pipe);
 241        }
 242
 243        intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 244
 245        temp = lvds_encoder->init_lvds_val;
 246        temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 247
 248        if (HAS_PCH_CPT(dev_priv)) {
 249                temp &= ~LVDS_PIPE_SEL_MASK_CPT;
 250                temp |= LVDS_PIPE_SEL_CPT(pipe);
 251        } else {
 252                temp &= ~LVDS_PIPE_SEL_MASK;
 253                temp |= LVDS_PIPE_SEL(pipe);
 254        }
 255
 256        /* set the corresponsding LVDS_BORDER bit */
 257        temp &= ~LVDS_BORDER_ENABLE;
 258        temp |= pipe_config->gmch_pfit.lvds_border_bits;
 259
 260        /*
 261         * Set the B0-B3 data pairs corresponding to whether we're going to
 262         * set the DPLLs for dual-channel mode or not.
 263         */
 264        if (lvds_encoder->is_dual_link)
 265                temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 266        else
 267                temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 268
 269        /*
 270         * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 271         * appropriately here, but we need to look more thoroughly into how
 272         * panels behave in the two modes. For now, let's just maintain the
 273         * value we got from the BIOS.
 274         */
 275        temp &= ~LVDS_A3_POWER_MASK;
 276        temp |= lvds_encoder->a3_power;
 277
 278        /*
 279         * Set the dithering flag on LVDS as needed, note that there is no
 280         * special lvds dither control bit on pch-split platforms, dithering is
 281         * only controlled through the PIPECONF reg.
 282         */
 283        if (IS_GEN(dev_priv, 4)) {
 284                /*
 285                 * Bspec wording suggests that LVDS port dithering only exists
 286                 * for 18bpp panels.
 287                 */
 288                if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 289                        temp |= LVDS_ENABLE_DITHER;
 290                else
 291                        temp &= ~LVDS_ENABLE_DITHER;
 292        }
 293        temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 294        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 295                temp |= LVDS_HSYNC_POLARITY;
 296        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 297                temp |= LVDS_VSYNC_POLARITY;
 298
 299        intel_de_write(dev_priv, lvds_encoder->reg, temp);
 300}
 301
 302/*
 303 * Sets the power state for the panel.
 304 */
 305static void intel_enable_lvds(struct intel_atomic_state *state,
 306                              struct intel_encoder *encoder,
 307                              const struct intel_crtc_state *pipe_config,
 308                              const struct drm_connector_state *conn_state)
 309{
 310        struct drm_device *dev = encoder->base.dev;
 311        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 312        struct drm_i915_private *dev_priv = to_i915(dev);
 313
 314        intel_de_write(dev_priv, lvds_encoder->reg,
 315                       intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN);
 316
 317        intel_de_write(dev_priv, PP_CONTROL(0),
 318                       intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON);
 319        intel_de_posting_read(dev_priv, lvds_encoder->reg);
 320
 321        if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
 322                drm_err(&dev_priv->drm,
 323                        "timed out waiting for panel to power on\n");
 324
 325        intel_panel_enable_backlight(pipe_config, conn_state);
 326}
 327
 328static void intel_disable_lvds(struct intel_atomic_state *state,
 329                               struct intel_encoder *encoder,
 330                               const struct intel_crtc_state *old_crtc_state,
 331                               const struct drm_connector_state *old_conn_state)
 332{
 333        struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 334        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 335
 336        intel_de_write(dev_priv, PP_CONTROL(0),
 337                       intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON);
 338        if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
 339                drm_err(&dev_priv->drm,
 340                        "timed out waiting for panel to power off\n");
 341
 342        intel_de_write(dev_priv, lvds_encoder->reg,
 343                       intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN);
 344        intel_de_posting_read(dev_priv, lvds_encoder->reg);
 345}
 346
 347static void gmch_disable_lvds(struct intel_atomic_state *state,
 348                              struct intel_encoder *encoder,
 349                              const struct intel_crtc_state *old_crtc_state,
 350                              const struct drm_connector_state *old_conn_state)
 351
 352{
 353        intel_panel_disable_backlight(old_conn_state);
 354
 355        intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 356}
 357
 358static void pch_disable_lvds(struct intel_atomic_state *state,
 359                             struct intel_encoder *encoder,
 360                             const struct intel_crtc_state *old_crtc_state,
 361                             const struct drm_connector_state *old_conn_state)
 362{
 363        intel_panel_disable_backlight(old_conn_state);
 364}
 365
 366static void pch_post_disable_lvds(struct intel_atomic_state *state,
 367                                  struct intel_encoder *encoder,
 368                                  const struct intel_crtc_state *old_crtc_state,
 369                                  const struct drm_connector_state *old_conn_state)
 370{
 371        intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
 372}
 373
 374static enum drm_mode_status
 375intel_lvds_mode_valid(struct drm_connector *connector,
 376                      struct drm_display_mode *mode)
 377{
 378        struct intel_connector *intel_connector = to_intel_connector(connector);
 379        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 380        int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 381
 382        if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 383                return MODE_NO_DBLESCAN;
 384        if (mode->hdisplay > fixed_mode->hdisplay)
 385                return MODE_PANEL;
 386        if (mode->vdisplay > fixed_mode->vdisplay)
 387                return MODE_PANEL;
 388        if (fixed_mode->clock > max_pixclk)
 389                return MODE_CLOCK_HIGH;
 390
 391        return MODE_OK;
 392}
 393
 394static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 395                                     struct intel_crtc_state *pipe_config,
 396                                     struct drm_connector_state *conn_state)
 397{
 398        struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 399        struct intel_lvds_encoder *lvds_encoder =
 400                to_lvds_encoder(&intel_encoder->base);
 401        struct intel_connector *intel_connector =
 402                lvds_encoder->attached_connector;
 403        struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 404        struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
 405        unsigned int lvds_bpp;
 406        int ret;
 407
 408        /* Should never happen!! */
 409        if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 410                drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n");
 411                return -EINVAL;
 412        }
 413
 414        if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 415                lvds_bpp = 8*3;
 416        else
 417                lvds_bpp = 6*3;
 418
 419        if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 420                drm_dbg_kms(&dev_priv->drm,
 421                            "forcing display bpp (was %d) to LVDS (%d)\n",
 422                            pipe_config->pipe_bpp, lvds_bpp);
 423                pipe_config->pipe_bpp = lvds_bpp;
 424        }
 425
 426        pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 427
 428        /*
 429         * We have timings from the BIOS for the panel, put them in
 430         * to the adjusted mode.  The CRTC will be set up for this mode,
 431         * with the panel scaling set up to source from the H/VDisplay
 432         * of the original mode.
 433         */
 434        intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 435                               adjusted_mode);
 436
 437        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 438                return -EINVAL;
 439
 440        if (HAS_PCH_SPLIT(dev_priv))
 441                pipe_config->has_pch_encoder = true;
 442
 443        if (HAS_GMCH(dev_priv))
 444                ret = intel_gmch_panel_fitting(pipe_config, conn_state);
 445        else
 446                ret = intel_pch_panel_fitting(pipe_config, conn_state);
 447        if (ret)
 448                return ret;
 449
 450        /*
 451         * XXX: It would be nice to support lower refresh rates on the
 452         * panels to reduce power consumption, and perhaps match the
 453         * user's requested refresh rate.
 454         */
 455
 456        return 0;
 457}
 458
 459static enum drm_connector_status
 460intel_lvds_detect(struct drm_connector *connector, bool force)
 461{
 462        return connector_status_connected;
 463}
 464
 465/*
 466 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 467 */
 468static int intel_lvds_get_modes(struct drm_connector *connector)
 469{
 470        struct intel_connector *intel_connector = to_intel_connector(connector);
 471        struct drm_device *dev = connector->dev;
 472        struct drm_display_mode *mode;
 473
 474        /* use cached edid if we have one */
 475        if (!IS_ERR_OR_NULL(intel_connector->edid))
 476                return drm_add_edid_modes(connector, intel_connector->edid);
 477
 478        mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
 479        if (mode == NULL)
 480                return 0;
 481
 482        drm_mode_probed_add(connector, mode);
 483        return 1;
 484}
 485
 486static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 487        .get_modes = intel_lvds_get_modes,
 488        .mode_valid = intel_lvds_mode_valid,
 489        .atomic_check = intel_digital_connector_atomic_check,
 490};
 491
 492static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 493        .detect = intel_lvds_detect,
 494        .fill_modes = drm_helper_probe_single_connector_modes,
 495        .atomic_get_property = intel_digital_connector_atomic_get_property,
 496        .atomic_set_property = intel_digital_connector_atomic_set_property,
 497        .late_register = intel_connector_register,
 498        .early_unregister = intel_connector_unregister,
 499        .destroy = intel_connector_destroy,
 500        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 501        .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 502};
 503
 504static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 505        .destroy = intel_encoder_destroy,
 506};
 507
 508static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 509{
 510        DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 511        return 1;
 512}
 513
 514/* These systems claim to have LVDS, but really don't */
 515static const struct dmi_system_id intel_no_lvds[] = {
 516        {
 517                .callback = intel_no_lvds_dmi_callback,
 518                .ident = "Apple Mac Mini (Core series)",
 519                .matches = {
 520                        DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 521                        DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 522                },
 523        },
 524        {
 525                .callback = intel_no_lvds_dmi_callback,
 526                .ident = "Apple Mac Mini (Core 2 series)",
 527                .matches = {
 528                        DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 529                        DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 530                },
 531        },
 532        {
 533                .callback = intel_no_lvds_dmi_callback,
 534                .ident = "MSI IM-945GSE-A",
 535                .matches = {
 536                        DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 537                        DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 538                },
 539        },
 540        {
 541                .callback = intel_no_lvds_dmi_callback,
 542                .ident = "Dell Studio Hybrid",
 543                .matches = {
 544                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 545                        DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 546                },
 547        },
 548        {
 549                .callback = intel_no_lvds_dmi_callback,
 550                .ident = "Dell OptiPlex FX170",
 551                .matches = {
 552                        DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 553                        DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 554                },
 555        },
 556        {
 557                .callback = intel_no_lvds_dmi_callback,
 558                .ident = "AOpen Mini PC",
 559                .matches = {
 560                        DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 561                        DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 562                },
 563        },
 564        {
 565                .callback = intel_no_lvds_dmi_callback,
 566                .ident = "AOpen Mini PC MP915",
 567                .matches = {
 568                        DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 569                        DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 570                },
 571        },
 572        {
 573                .callback = intel_no_lvds_dmi_callback,
 574                .ident = "AOpen i915GMm-HFS",
 575                .matches = {
 576                        DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 577                        DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 578                },
 579        },
 580        {
 581                .callback = intel_no_lvds_dmi_callback,
 582                .ident = "AOpen i45GMx-I",
 583                .matches = {
 584                        DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 585                        DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 586                },
 587        },
 588        {
 589                .callback = intel_no_lvds_dmi_callback,
 590                .ident = "Aopen i945GTt-VFA",
 591                .matches = {
 592                        DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 593                },
 594        },
 595        {
 596                .callback = intel_no_lvds_dmi_callback,
 597                .ident = "Clientron U800",
 598                .matches = {
 599                        DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 600                        DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 601                },
 602        },
 603        {
 604                .callback = intel_no_lvds_dmi_callback,
 605                .ident = "Clientron E830",
 606                .matches = {
 607                        DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 608                        DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 609                },
 610        },
 611        {
 612                .callback = intel_no_lvds_dmi_callback,
 613                .ident = "Asus EeeBox PC EB1007",
 614                .matches = {
 615                        DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 616                        DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 617                },
 618        },
 619        {
 620                .callback = intel_no_lvds_dmi_callback,
 621                .ident = "Asus AT5NM10T-I",
 622                .matches = {
 623                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 624                        DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 625                },
 626        },
 627        {
 628                .callback = intel_no_lvds_dmi_callback,
 629                .ident = "Hewlett-Packard HP t5740",
 630                .matches = {
 631                        DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 632                        DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 633                },
 634        },
 635        {
 636                .callback = intel_no_lvds_dmi_callback,
 637                .ident = "Hewlett-Packard t5745",
 638                .matches = {
 639                        DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 640                        DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 641                },
 642        },
 643        {
 644                .callback = intel_no_lvds_dmi_callback,
 645                .ident = "Hewlett-Packard st5747",
 646                .matches = {
 647                        DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 648                        DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 649                },
 650        },
 651        {
 652                .callback = intel_no_lvds_dmi_callback,
 653                .ident = "MSI Wind Box DC500",
 654                .matches = {
 655                        DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 656                        DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 657                },
 658        },
 659        {
 660                .callback = intel_no_lvds_dmi_callback,
 661                .ident = "Gigabyte GA-D525TUD",
 662                .matches = {
 663                        DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 664                        DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 665                },
 666        },
 667        {
 668                .callback = intel_no_lvds_dmi_callback,
 669                .ident = "Supermicro X7SPA-H",
 670                .matches = {
 671                        DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 672                        DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 673                },
 674        },
 675        {
 676                .callback = intel_no_lvds_dmi_callback,
 677                .ident = "Fujitsu Esprimo Q900",
 678                .matches = {
 679                        DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 680                        DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 681                },
 682        },
 683        {
 684                .callback = intel_no_lvds_dmi_callback,
 685                .ident = "Intel D410PT",
 686                .matches = {
 687                        DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 688                        DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 689                },
 690        },
 691        {
 692                .callback = intel_no_lvds_dmi_callback,
 693                .ident = "Intel D425KT",
 694                .matches = {
 695                        DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 696                        DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 697                },
 698        },
 699        {
 700                .callback = intel_no_lvds_dmi_callback,
 701                .ident = "Intel D510MO",
 702                .matches = {
 703                        DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 704                        DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 705                },
 706        },
 707        {
 708                .callback = intel_no_lvds_dmi_callback,
 709                .ident = "Intel D525MW",
 710                .matches = {
 711                        DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 712                        DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 713                },
 714        },
 715        {
 716                .callback = intel_no_lvds_dmi_callback,
 717                .ident = "Radiant P845",
 718                .matches = {
 719                        DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
 720                        DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
 721                },
 722        },
 723
 724        { }     /* terminating entry */
 725};
 726
 727static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 728{
 729        DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 730        return 1;
 731}
 732
 733static const struct dmi_system_id intel_dual_link_lvds[] = {
 734        {
 735                .callback = intel_dual_link_lvds_callback,
 736                .ident = "Apple MacBook Pro 15\" (2010)",
 737                .matches = {
 738                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 739                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 740                },
 741        },
 742        {
 743                .callback = intel_dual_link_lvds_callback,
 744                .ident = "Apple MacBook Pro 15\" (2011)",
 745                .matches = {
 746                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 747                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 748                },
 749        },
 750        {
 751                .callback = intel_dual_link_lvds_callback,
 752                .ident = "Apple MacBook Pro 15\" (2012)",
 753                .matches = {
 754                        DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 755                        DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 756                },
 757        },
 758        { }     /* terminating entry */
 759};
 760
 761struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
 762{
 763        struct intel_encoder *encoder;
 764
 765        for_each_intel_encoder(&dev_priv->drm, encoder) {
 766                if (encoder->type == INTEL_OUTPUT_LVDS)
 767                        return encoder;
 768        }
 769
 770        return NULL;
 771}
 772
 773bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
 774{
 775        struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
 776
 777        return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 778}
 779
 780static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 781{
 782        struct drm_device *dev = lvds_encoder->base.base.dev;
 783        unsigned int val;
 784        struct drm_i915_private *dev_priv = to_i915(dev);
 785
 786        /* use the module option value if specified */
 787        if (dev_priv->params.lvds_channel_mode > 0)
 788                return dev_priv->params.lvds_channel_mode == 2;
 789
 790        /* single channel LVDS is limited to 112 MHz */
 791        if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
 792                return true;
 793
 794        if (dmi_check_system(intel_dual_link_lvds))
 795                return true;
 796
 797        /*
 798         * BIOS should set the proper LVDS register value at boot, but
 799         * in reality, it doesn't set the value when the lid is closed;
 800         * we need to check "the value to be set" in VBT when LVDS
 801         * register is uninitialized.
 802         */
 803        val = intel_de_read(dev_priv, lvds_encoder->reg);
 804        if (HAS_PCH_CPT(dev_priv))
 805                val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
 806        else
 807                val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
 808        if (val == 0)
 809                val = dev_priv->vbt.bios_lvds_val;
 810
 811        return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 812}
 813
 814/**
 815 * intel_lvds_init - setup LVDS connectors on this device
 816 * @dev_priv: i915 device
 817 *
 818 * Create the connector, register the LVDS DDC bus, and try to figure out what
 819 * modes we can display on the LVDS panel (if present).
 820 */
 821void intel_lvds_init(struct drm_i915_private *dev_priv)
 822{
 823        struct drm_device *dev = &dev_priv->drm;
 824        struct intel_lvds_encoder *lvds_encoder;
 825        struct intel_encoder *intel_encoder;
 826        struct intel_connector *intel_connector;
 827        struct drm_connector *connector;
 828        struct drm_encoder *encoder;
 829        struct drm_display_mode *fixed_mode = NULL;
 830        struct drm_display_mode *downclock_mode = NULL;
 831        struct edid *edid;
 832        i915_reg_t lvds_reg;
 833        u32 lvds;
 834        u8 pin;
 835        u32 allowed_scalers;
 836
 837        /* Skip init on machines we know falsely report LVDS */
 838        if (dmi_check_system(intel_no_lvds)) {
 839                drm_WARN(dev, !dev_priv->vbt.int_lvds_support,
 840                         "Useless DMI match. Internal LVDS support disabled by VBT\n");
 841                return;
 842        }
 843
 844        if (!dev_priv->vbt.int_lvds_support) {
 845                drm_dbg_kms(&dev_priv->drm,
 846                            "Internal LVDS support disabled by VBT\n");
 847                return;
 848        }
 849
 850        if (HAS_PCH_SPLIT(dev_priv))
 851                lvds_reg = PCH_LVDS;
 852        else
 853                lvds_reg = LVDS;
 854
 855        lvds = intel_de_read(dev_priv, lvds_reg);
 856
 857        if (HAS_PCH_SPLIT(dev_priv)) {
 858                if ((lvds & LVDS_DETECTED) == 0)
 859                        return;
 860        }
 861
 862        pin = GMBUS_PIN_PANEL;
 863        if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 864                if ((lvds & LVDS_PORT_EN) == 0) {
 865                        drm_dbg_kms(&dev_priv->drm,
 866                                    "LVDS is not present in VBT\n");
 867                        return;
 868                }
 869                drm_dbg_kms(&dev_priv->drm,
 870                            "LVDS is not present in VBT, but enabled anyway\n");
 871        }
 872
 873        lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 874        if (!lvds_encoder)
 875                return;
 876
 877        intel_connector = intel_connector_alloc();
 878        if (!intel_connector) {
 879                kfree(lvds_encoder);
 880                return;
 881        }
 882
 883        lvds_encoder->attached_connector = intel_connector;
 884
 885        intel_encoder = &lvds_encoder->base;
 886        encoder = &intel_encoder->base;
 887        connector = &intel_connector->base;
 888        drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
 889                           DRM_MODE_CONNECTOR_LVDS);
 890
 891        drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
 892                         DRM_MODE_ENCODER_LVDS, "LVDS");
 893
 894        intel_encoder->enable = intel_enable_lvds;
 895        intel_encoder->pre_enable = intel_pre_enable_lvds;
 896        intel_encoder->compute_config = intel_lvds_compute_config;
 897        if (HAS_PCH_SPLIT(dev_priv)) {
 898                intel_encoder->disable = pch_disable_lvds;
 899                intel_encoder->post_disable = pch_post_disable_lvds;
 900        } else {
 901                intel_encoder->disable = gmch_disable_lvds;
 902        }
 903        intel_encoder->get_hw_state = intel_lvds_get_hw_state;
 904        intel_encoder->get_config = intel_lvds_get_config;
 905        intel_encoder->update_pipe = intel_panel_update_backlight;
 906        intel_connector->get_hw_state = intel_connector_get_hw_state;
 907
 908        intel_connector_attach_encoder(intel_connector, intel_encoder);
 909
 910        intel_encoder->type = INTEL_OUTPUT_LVDS;
 911        intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
 912        intel_encoder->port = PORT_NONE;
 913        intel_encoder->cloneable = 0;
 914        if (INTEL_GEN(dev_priv) < 4)
 915                intel_encoder->pipe_mask = BIT(PIPE_B);
 916        else
 917                intel_encoder->pipe_mask = ~0;
 918
 919        drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
 920        connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 921        connector->interlace_allowed = false;
 922        connector->doublescan_allowed = false;
 923
 924        lvds_encoder->reg = lvds_reg;
 925
 926        /* create the scaling mode property */
 927        allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
 928        allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
 929        allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
 930        drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
 931        connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
 932
 933        intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
 934        lvds_encoder->init_lvds_val = lvds;
 935
 936        /*
 937         * LVDS discovery:
 938         * 1) check for EDID on DDC
 939         * 2) check for VBT data
 940         * 3) check to see if LVDS is already on
 941         *    if none of the above, no panel
 942         */
 943
 944        /*
 945         * Attempt to get the fixed panel mode from DDC.  Assume that the
 946         * preferred mode is the right one.
 947         */
 948        mutex_lock(&dev->mode_config.mutex);
 949        if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
 950                edid = drm_get_edid_switcheroo(connector,
 951                                    intel_gmbus_get_adapter(dev_priv, pin));
 952        else
 953                edid = drm_get_edid(connector,
 954                                    intel_gmbus_get_adapter(dev_priv, pin));
 955        if (edid) {
 956                if (drm_add_edid_modes(connector, edid)) {
 957                        drm_connector_update_edid_property(connector,
 958                                                                edid);
 959                } else {
 960                        kfree(edid);
 961                        edid = ERR_PTR(-EINVAL);
 962                }
 963        } else {
 964                edid = ERR_PTR(-ENOENT);
 965        }
 966        intel_connector->edid = edid;
 967
 968        fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
 969        if (fixed_mode)
 970                goto out;
 971
 972        /* Failed to get EDID, what about VBT? */
 973        fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
 974        if (fixed_mode)
 975                goto out;
 976
 977        /*
 978         * If we didn't get EDID, try checking if the panel is already turned
 979         * on.  If so, assume that whatever is currently programmed is the
 980         * correct mode.
 981         */
 982        fixed_mode = intel_encoder_current_mode(intel_encoder);
 983        if (fixed_mode) {
 984                drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: ");
 985                drm_mode_debug_printmodeline(fixed_mode);
 986                fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 987        }
 988
 989        /* If we still don't have a mode after all that, give up. */
 990        if (!fixed_mode)
 991                goto failed;
 992
 993out:
 994        mutex_unlock(&dev->mode_config.mutex);
 995
 996        intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
 997        intel_panel_setup_backlight(connector, INVALID_PIPE);
 998
 999        lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1000        drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n",
1001                    lvds_encoder->is_dual_link ? "dual" : "single");
1002
1003        lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1004
1005        return;
1006
1007failed:
1008        mutex_unlock(&dev->mode_config.mutex);
1009
1010        drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n");
1011        drm_connector_cleanup(connector);
1012        drm_encoder_cleanup(encoder);
1013        kfree(lvds_encoder);
1014        intel_connector_free(intel_connector);
1015        return;
1016}
1017