LXR linux/drivers/gpu/drm/i915/gt/intel_rps

   1/*
   2 * SPDX-License-Identifier: MIT
   3 *
   4 * Copyright © 2019 Intel Corporation
   5 */
   6
   7#ifndef INTEL_RPS_TYPES_H
   8#define INTEL_RPS_TYPES_H
   9
  10#include <linux/atomic.h>
  11#include <linux/ktime.h>
  12#include <linux/mutex.h>
  13#include <linux/types.h>
  14#include <linux/workqueue.h>
  15
  16struct intel_ips {
  17        u64 last_count1;
  18        unsigned long last_time1;
  19        unsigned long chipset_power;
  20        u64 last_count2;
  21        u64 last_time2;
  22        unsigned long gfx_power;
  23        u8 corr;
  24
  25        int c, m;
  26};
  27
  28struct intel_rps_ei {
  29        ktime_t ktime;
  30        u32 render_c0;
  31        u32 media_c0;
  32};
  33
  34enum {
  35        INTEL_RPS_ENABLED = 0,
  36        INTEL_RPS_ACTIVE,
  37        INTEL_RPS_INTERRUPTS,
  38        INTEL_RPS_TIMER,
  39};
  40
  41struct intel_rps {
  42        struct mutex lock; /* protects enabling and the worker */
  43
  44        /*
  45         * work, interrupts_enabled and pm_iir are protected by
  46         * dev_priv->irq_lock
  47         */
  48        struct timer_list timer;
  49        struct work_struct work;
  50        unsigned long flags;
  51
  52        ktime_t pm_timestamp;
  53        u32 pm_interval;
  54        u32 pm_iir;
  55
  56        /* PM interrupt bits that should never be masked */
  57        u32 pm_intrmsk_mbz;
  58        u32 pm_events;
  59
  60        /* Frequencies are stored in potentially platform dependent multiples.
  61         * In other words, *_freq needs to be multiplied by X to be interesting.
  62         * Soft limits are those which are used for the dynamic reclocking done
  63         * by the driver (raise frequencies under heavy loads, and lower for
  64         * lighter loads). Hard limits are those imposed by the hardware.
  65         *
  66         * A distinction is made for overclocking, which is never enabled by
  67         * default, and is considered to be above the hard limit if it's
  68         * possible at all.
  69         */
  70        u8 cur_freq;            /* Current frequency (cached, may not == HW) */
  71        u8 last_freq;           /* Last SWREQ frequency */
  72        u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
  73        u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
  74        u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
  75        u8 min_freq;            /* AKA RPn. Minimum frequency */
  76        u8 boost_freq;          /* Frequency to request when wait boosting */
  77        u8 idle_freq;           /* Frequency to request when we are idle */
  78        u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
  79        u8 rp1_freq;            /* "less than" RP0 power/freqency */
  80        u8 rp0_freq;            /* Non-overclocked max frequency. */
  81        u16 gpll_ref_freq;      /* vlv/chv GPLL reference frequency */
  82
  83        int last_adj;
  84
  85        struct {
  86                struct mutex mutex;
  87
  88                enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
  89                unsigned int interactive;
  90
  91                u8 up_threshold; /* Current %busy required to uplock */
  92                u8 down_threshold; /* Current %busy required to downclock */
  93        } power;
  94
  95        atomic_t num_waiters;
  96        atomic_t boosts;
  97
  98        /* manual wa residency calculations */
  99        struct intel_rps_ei ei;
 100        struct intel_ips ips;
 101};
 102
 103#endif /* INTEL_RPS_TYPES_H */
 104