1
2
3
4#ifndef _A6XX_GMU_H_
5#define _A6XX_GMU_H_
6
7#include <linux/iopoll.h>
8#include <linux/interrupt.h>
9#include "msm_drv.h"
10#include "a6xx_hfi.h"
11
12struct a6xx_gmu_bo {
13 struct drm_gem_object *obj;
14 void *virt;
15 size_t size;
16 u64 iova;
17};
18
19
20
21
22
23
24
25#define GMU_WARM_BOOT 0
26
27
28#define GMU_COLD_BOOT 1
29
30
31
32
33
34
35
36#define GMU_IDLE_STATE_ACTIVE 0
37
38
39#define GMU_IDLE_STATE_SPTP 2
40
41
42#define GMU_IDLE_STATE_IFPC 3
43
44struct a6xx_gmu {
45 struct device *dev;
46
47 struct msm_gem_address_space *aspace;
48
49 void * __iomem mmio;
50 void * __iomem rscc;
51
52 int hfi_irq;
53 int gmu_irq;
54
55 struct device *gxpd;
56
57 int idle_level;
58
59 struct a6xx_gmu_bo hfi;
60 struct a6xx_gmu_bo debug;
61 struct a6xx_gmu_bo icache;
62 struct a6xx_gmu_bo dcache;
63 struct a6xx_gmu_bo dummy;
64 struct a6xx_gmu_bo log;
65
66 int nr_clocks;
67 struct clk_bulk_data *clocks;
68 struct clk *core_clk;
69
70
71 int current_perf_index;
72
73 int nr_gpu_freqs;
74 unsigned long gpu_freqs[16];
75 u32 gx_arc_votes[16];
76
77 int nr_gmu_freqs;
78 unsigned long gmu_freqs[4];
79 u32 cx_arc_votes[4];
80
81 unsigned long freq;
82
83 struct a6xx_hfi_queue queues[2];
84
85 bool initialized;
86 bool hung;
87 bool legacy;
88};
89
90static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
91{
92 return msm_readl(gmu->mmio + (offset << 2));
93}
94
95static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
96{
97 return msm_writel(value, gmu->mmio + (offset << 2));
98}
99
100static inline void
101gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size)
102{
103 memcpy_toio(gmu->mmio + (offset << 2), data, size);
104 wmb();
105}
106
107static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or)
108{
109 u32 val = gmu_read(gmu, reg);
110
111 val &= ~mask;
112
113 gmu_write(gmu, reg, val | or);
114}
115
116static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
117{
118 u64 val;
119
120 val = (u64) msm_readl(gmu->mmio + (lo << 2));
121 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
122
123 return val;
124}
125
126#define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \
127 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
128 interval, timeout)
129
130static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
131{
132 return msm_readl(gmu->rscc + (offset << 2));
133}
134
135static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
136{
137 return msm_writel(value, gmu->rscc + (offset << 2));
138}
139
140#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
141 readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
142 interval, timeout)
143
144
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151
152
153
154
155enum a6xx_gmu_oob_state {
156 GMU_OOB_BOOT_SLUMBER = 0,
157 GMU_OOB_GPU_SET,
158 GMU_OOB_DCVS_SET,
159};
160
161
162
163
164
165
166
167
168
169
170#define GMU_OOB_BOOT_SLUMBER_REQUEST 22
171#define GMU_OOB_BOOT_SLUMBER_ACK 30
172#define GMU_OOB_BOOT_SLUMBER_CLEAR 30
173
174
175
176
177#define GMU_OOB_DCVS_REQUEST 23
178#define GMU_OOB_DCVS_ACK 31
179#define GMU_OOB_DCVS_CLEAR 31
180
181
182
183
184
185#define GMU_OOB_GPU_SET_REQUEST 16
186#define GMU_OOB_GPU_SET_ACK 24
187#define GMU_OOB_GPU_SET_CLEAR 24
188
189#define GMU_OOB_GPU_SET_REQUEST_NEW 30
190#define GMU_OOB_GPU_SET_ACK_NEW 31
191#define GMU_OOB_GPU_SET_CLEAR_NEW 31
192
193
194void a6xx_hfi_init(struct a6xx_gmu *gmu);
195int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
196void a6xx_hfi_stop(struct a6xx_gmu *gmu);
197int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
198int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index);
199
200bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
201bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
202
203#endif
204