1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */ 3/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */ 4/* 5 * Register definitions based on mali_midg_regmap.h 6 * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved. 7 */ 8#ifndef __PANFROST_REGS_H__ 9#define __PANFROST_REGS_H__ 10 11#define GPU_ID 0x00 12#define GPU_L2_FEATURES 0x004 /* (RO) Level 2 cache features */ 13#define GPU_CORE_FEATURES 0x008 /* (RO) Shader Core Features */ 14#define GPU_TILER_FEATURES 0x00C /* (RO) Tiler Features */ 15#define GPU_MEM_FEATURES 0x010 /* (RO) Memory system features */ 16#define GROUPS_L2_COHERENT BIT(0) /* Cores groups are l2 coherent */ 17 18#define GPU_MMU_FEATURES 0x014 /* (RO) MMU features */ 19#define GPU_AS_PRESENT 0x018 /* (RO) Address space slots present */ 20#define GPU_JS_PRESENT 0x01C /* (RO) Job slots present */ 21 22#define GPU_INT_RAWSTAT 0x20 23#define GPU_INT_CLEAR 0x24 24#define GPU_INT_MASK 0x28 25#define GPU_INT_STAT 0x2c 26#define GPU_IRQ_FAULT BIT(0) 27#define GPU_IRQ_MULTIPLE_FAULT BIT(7) 28#define GPU_IRQ_RESET_COMPLETED BIT(8) 29#define GPU_IRQ_POWER_CHANGED BIT(9) 30#define GPU_IRQ_POWER_CHANGED_ALL BIT(10) 31#define GPU_IRQ_PERFCNT_SAMPLE_COMPLETED BIT(16) 32#define GPU_IRQ_CLEAN_CACHES_COMPLETED BIT(17) 33#define GPU_IRQ_MASK_ALL \ 34 (GPU_IRQ_FAULT |\ 35 GPU_IRQ_MULTIPLE_FAULT |\ 36 GPU_IRQ_RESET_COMPLETED |\ 37 GPU_IRQ_POWER_CHANGED |\ 38 GPU_IRQ_POWER_CHANGED_ALL |\ 39 GPU_IRQ_PERFCNT_SAMPLE_COMPLETED |\ 40 GPU_IRQ_CLEAN_CACHES_COMPLETED) 41#define GPU_IRQ_MASK_ERROR \ 42 ( \ 43 GPU_IRQ_FAULT |\ 44 GPU_IRQ_MULTIPLE_FAULT) 45#define GPU_CMD 0x30 46#define GPU_CMD_SOFT_RESET 0x01 47#define GPU_CMD_PERFCNT_CLEAR 0x03 48#define GPU_CMD_PERFCNT_SAMPLE 0x04 49#define GPU_CMD_CLEAN_CACHES 0x07 50#define GPU_CMD_CLEAN_INV_CACHES 0x08 51#define GPU_STATUS 0x34 52#define GPU_STATUS_PRFCNT_ACTIVE BIT(2) 53#define GPU_LATEST_FLUSH_ID 0x38 54#define GPU_FAULT_STATUS 0x3C 55#define GPU_FAULT_ADDRESS_LO 0x40 56#define GPU_FAULT_ADDRESS_HI 0x44 57 58#define GPU_PERFCNT_BASE_LO 0x60 59#define GPU_PERFCNT_BASE_HI 0x64 60#define GPU_PERFCNT_CFG 0x68 61#define GPU_PERFCNT_CFG_MODE(x) (x) 62#define GPU_PERFCNT_CFG_MODE_OFF 0 63#define GPU_PERFCNT_CFG_MODE_MANUAL 1 64#define GPU_PERFCNT_CFG_MODE_TILE 2 65#define GPU_PERFCNT_CFG_AS(x) ((x) << 4) 66#define GPU_PERFCNT_CFG_SETSEL(x) ((x) << 8) 67#define GPU_PRFCNT_JM_EN 0x6c 68#define GPU_PRFCNT_SHADER_EN 0x70 69#define GPU_PRFCNT_TILER_EN 0x74 70#define GPU_PRFCNT_MMU_L2_EN 0x7c 71 72#define GPU_THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */ 73#define GPU_THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */ 74#define GPU_THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */ 75#define GPU_THREAD_FEATURES 0x0AC /* (RO) Thread features */ 76#define GPU_THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that 77 * TLS must be allocated for */ 78 79#define GPU_TEXTURE_FEATURES(n) (0x0B0 + ((n) * 4)) 80#define GPU_JS_FEATURES(n) (0x0C0 + ((n) * 4)) 81 82#define GPU_SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */ 83#define GPU_SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */ 84#define GPU_TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */ 85#define GPU_TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */ 86 87#define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */ 88#define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */ 89 90#define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */ 91#define COHERENCY_ACE_LITE BIT(0) 92#define COHERENCY_ACE BIT(1) 93 94#define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */ 95#define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */ 96 97#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 98#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 99 100#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 101#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 102 103#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 104#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 105 106#define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */ 107#define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */ 108 109 110#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 111#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 112 113#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 114#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 115 116#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 117#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 118 119#define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */ 120#define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */ 121 122 123#define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */ 124#define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */ 125 126#define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */ 127#define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */ 128 129#define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */ 130#define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */ 131 132#define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */ 133#define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */ 134 135 136#define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */ 137#define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */ 138 139#define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */ 140#define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */ 141 142#define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */ 143#define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */ 144 145#define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */ 146#define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */ 147 148 149#define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */ 150#define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */ 151 152#define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */ 153#define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */ 154 155#define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */ 156#define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */ 157 158#define GPU_JM_CONFIG 0xF00 /* (RW) Job Manager configuration register (Implementation specific register) */ 159#define GPU_SHADER_CONFIG 0xF04 /* (RW) Shader core configuration settings (Implementation specific register) */ 160#define GPU_TILER_CONFIG 0xF08 /* (RW) Tiler core configuration settings (Implementation specific register) */ 161#define GPU_L2_MMU_CONFIG 0xF0C /* (RW) Configuration of the L2 cache and MMU (Implementation specific register) */ 162 163/* L2_MMU_CONFIG register */ 164#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT 23 165#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT) 166#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT 24 167#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 168#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 169#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 170#define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 171 172#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT 26 173#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 174#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_OCTANT (0x1 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 175#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_QUARTER (0x2 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 176#define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 177 178#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS_SHIFT 12 179#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_READS (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT) 180 181#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES_SHIFT 15 182#define L2_MMU_CONFIG_3BIT_LIMIT_EXTERNAL_WRITES (0x7 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT) 183 184/* SHADER_CONFIG register */ 185#define SC_ALT_COUNTERS BIT(3) 186#define SC_OVERRIDE_FWD_PIXEL_KILL BIT(4) 187#define SC_SDC_DISABLE_OQ_DISCARD BIT(6) 188#define SC_LS_ALLOW_ATTR_TYPES BIT(16) 189#define SC_LS_PAUSEBUFFER_DISABLE BIT(16) 190#define SC_TLS_HASH_ENABLE BIT(17) 191#define SC_LS_ATTR_CHECK_DISABLE BIT(18) 192#define SC_ENABLE_TEXGRD_FLAGS BIT(25) 193/* End SHADER_CONFIG register */ 194 195/* TILER_CONFIG register */ 196#define TC_CLOCK_GATE_OVERRIDE BIT(0) 197 198/* JM_CONFIG register */ 199#define JM_TIMESTAMP_OVERRIDE BIT(0) 200#define JM_CLOCK_GATE_OVERRIDE BIT(1) 201#define JM_JOB_THROTTLE_ENABLE BIT(2) 202#define JM_JOB_THROTTLE_LIMIT_SHIFT 3 203#define JM_MAX_JOB_THROTTLE_LIMIT 0x3F 204#define JM_FORCE_COHERENCY_FEATURES_SHIFT 2 205#define JM_IDVS_GROUP_SIZE_SHIFT 16 206#define JM_MAX_IDVS_GROUP_SIZE 0x3F 207 208 209/* Job Control regs */ 210#define JOB_INT_RAWSTAT 0x1000 211#define JOB_INT_CLEAR 0x1004 212#define JOB_INT_MASK 0x1008 213#define JOB_INT_STAT 0x100c 214#define JOB_INT_JS_STATE 0x1010 215#define JOB_INT_THROTTLE 0x1014 216 217#define MK_JS_MASK(j) (0x10001 << (j)) 218#define JOB_INT_MASK_ERR(j) BIT((j) + 16) 219#define JOB_INT_MASK_DONE(j) BIT(j) 220 221#define JS_BASE 0x1800 222#define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00) 223#define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04) 224#define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08) 225#define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c) 226#define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10) 227#define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14) 228#define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18) 229#define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c) 230#define JS_COMMAND(n) (JS_BASE + ((n) * 0x80) + 0x20) 231#define JS_STATUS(n) (JS_BASE + ((n) * 0x80) + 0x24) 232#define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x40) 233#define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x44) 234#define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x50) 235#define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x54) 236#define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x58) 237#define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x60) 238#define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x70) 239 240/* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */ 241#define JS_CONFIG_START_FLUSH_CLEAN BIT(8) 242#define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 243#define JS_CONFIG_START_MMU BIT(10) 244#define JS_CONFIG_JOB_CHAIN_FLAG BIT(11) 245#define JS_CONFIG_END_FLUSH_CLEAN BIT(12) 246#define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 247#define JS_CONFIG_ENABLE_FLUSH_REDUCTION BIT(14) 248#define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK BIT(15) 249#define JS_CONFIG_THREAD_PRI(n) ((n) << 16) 250 251#define JS_COMMAND_NOP 0x00 252#define JS_COMMAND_START 0x01 253#define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 254#define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 255#define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 256#define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 257#define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 258#define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 259 260#define JS_STATUS_EVENT_ACTIVE 0x08 261 262 263/* MMU regs */ 264#define MMU_INT_RAWSTAT 0x2000 265#define MMU_INT_CLEAR 0x2004 266#define MMU_INT_MASK 0x2008 267#define MMU_INT_STAT 0x200c 268 269/* AS_COMMAND register commands */ 270#define AS_COMMAND_NOP 0x00 /* NOP Operation */ 271#define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */ 272#define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */ 273#define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */ 274#define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs 275 (deprecated - only for use with T60x) */ 276#define AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */ 277#define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then 278 flush all L2 caches then issue a flush region command to all MMUs */ 279 280#define MMU_AS(as) (0x2400 + ((as) << 6)) 281 282#define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */ 283#define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */ 284#define AS_MEMATTR_LO(as) (MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low word. */ 285#define AS_MEMATTR_HI(as) (MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high word. */ 286#define AS_LOCKADDR_LO(as) (MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */ 287#define AS_LOCKADDR_HI(as) (MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */ 288#define AS_COMMAND(as) (MMU_AS(as) + 0x18) /* (WO) MMU command register for address space n */ 289#define AS_FAULTSTATUS(as) (MMU_AS(as) + 0x1C) /* (RO) MMU fault status register for address space n */ 290#define AS_FAULTADDRESS_LO(as) (MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low word */ 291#define AS_FAULTADDRESS_HI(as) (MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high word */ 292#define AS_STATUS(as) (MMU_AS(as) + 0x28) /* (RO) Status flags for address space n */ 293/* Additional Bifrost AS regsiters */ 294#define AS_TRANSCFG_LO(as) (MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */ 295#define AS_TRANSCFG_HI(as) (MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */ 296#define AS_FAULTEXTRA_LO(as) (MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */ 297#define AS_FAULTEXTRA_HI(as) (MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */ 298 299/* 300 * Begin LPAE MMU TRANSTAB register values 301 */ 302#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000 303#define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2 304#define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3 305#define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3 306#define AS_TRANSTAB_LPAE_READ_INNER BIT(2) 307#define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) 308 309#define AS_STATUS_AS_ACTIVE 0x01 310 311#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << 8) 312#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0 << 8) 313#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1 << 8) 314#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2 << 8) 315#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3 << 8) 316 317#define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) 318#define gpu_read(dev, reg) readl(dev->iomem + reg) 319 320#endif 321