LXR linux/drivers/gpu/drm/radeon/atombios

   1/*
   2 * Copyright 2007-11 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26
  27#include <linux/backlight.h>
  28#include <linux/dmi.h>
  29#include <linux/pci.h>
  30
  31#include <drm/drm_crtc_helper.h>
  32#include <drm/drm_file.h>
  33#include <drm/radeon_drm.h>
  34
  35#include "atom.h"
  36#include "radeon.h"
  37#include "radeon_asic.h"
  38#include "radeon_audio.h"
  39
  40extern int atom_debug;
  41
  42static u8
  43radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  44{
  45        u8 backlight_level;
  46        u32 bios_2_scratch;
  47
  48        if (rdev->family >= CHIP_R600)
  49                bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  50        else
  51                bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  52
  53        backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  54                           ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  55
  56        return backlight_level;
  57}
  58
  59static void
  60radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  61                                       u8 backlight_level)
  62{
  63        u32 bios_2_scratch;
  64
  65        if (rdev->family >= CHIP_R600)
  66                bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  67        else
  68                bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  69
  70        bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  71        bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  72                           ATOM_S2_CURRENT_BL_LEVEL_MASK);
  73
  74        if (rdev->family >= CHIP_R600)
  75                WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  76        else
  77                WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  78}
  79
  80u8
  81atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  82{
  83        struct drm_device *dev = radeon_encoder->base.dev;
  84        struct radeon_device *rdev = dev->dev_private;
  85
  86        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  87                return 0;
  88
  89        return radeon_atom_get_backlight_level_from_reg(rdev);
  90}
  91
  92void
  93atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  94{
  95        struct drm_encoder *encoder = &radeon_encoder->base;
  96        struct drm_device *dev = radeon_encoder->base.dev;
  97        struct radeon_device *rdev = dev->dev_private;
  98        struct radeon_encoder_atom_dig *dig;
  99        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 100        int index;
 101
 102        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 103                return;
 104
 105        if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 106            radeon_encoder->enc_priv) {
 107                dig = radeon_encoder->enc_priv;
 108                dig->backlight_level = level;
 109                radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 110
 111                switch (radeon_encoder->encoder_id) {
 112                case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 113                case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 114                        index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 115                        if (dig->backlight_level == 0) {
 116                                args.ucAction = ATOM_LCD_BLOFF;
 117                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 118                        } else {
 119                                args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 120                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 121                                args.ucAction = ATOM_LCD_BLON;
 122                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 123                        }
 124                        break;
 125                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 126                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 127                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 128                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 129                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 130                        if (dig->backlight_level == 0)
 131                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 132                        else {
 133                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 134                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 135                        }
 136                        break;
 137                default:
 138                        break;
 139                }
 140        }
 141}
 142
 143#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 144
 145static u8 radeon_atom_bl_level(struct backlight_device *bd)
 146{
 147        u8 level;
 148
 149        /* Convert brightness to hardware level */
 150        if (bd->props.brightness < 0)
 151                level = 0;
 152        else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 153                level = RADEON_MAX_BL_LEVEL;
 154        else
 155                level = bd->props.brightness;
 156
 157        return level;
 158}
 159
 160static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 161{
 162        struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 163        struct radeon_encoder *radeon_encoder = pdata->encoder;
 164
 165        atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 166
 167        return 0;
 168}
 169
 170static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 171{
 172        struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 173        struct radeon_encoder *radeon_encoder = pdata->encoder;
 174        struct drm_device *dev = radeon_encoder->base.dev;
 175        struct radeon_device *rdev = dev->dev_private;
 176
 177        return radeon_atom_get_backlight_level_from_reg(rdev);
 178}
 179
 180static const struct backlight_ops radeon_atom_backlight_ops = {
 181        .get_brightness = radeon_atom_backlight_get_brightness,
 182        .update_status  = radeon_atom_backlight_update_status,
 183};
 184
 185void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 186                                struct drm_connector *drm_connector)
 187{
 188        struct drm_device *dev = radeon_encoder->base.dev;
 189        struct radeon_device *rdev = dev->dev_private;
 190        struct backlight_device *bd;
 191        struct backlight_properties props;
 192        struct radeon_backlight_privdata *pdata;
 193        struct radeon_encoder_atom_dig *dig;
 194        char bl_name[16];
 195
 196        /* Mac laptops with multiple GPUs use the gmux driver for backlight
 197         * so don't register a backlight device
 198         */
 199        if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 200            (rdev->pdev->device == 0x6741))
 201                return;
 202
 203        if (!radeon_encoder->enc_priv)
 204                return;
 205
 206        if (!rdev->is_atom_bios)
 207                return;
 208
 209        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 210                return;
 211
 212        pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 213        if (!pdata) {
 214                DRM_ERROR("Memory allocation failed\n");
 215                goto error;
 216        }
 217
 218        memset(&props, 0, sizeof(props));
 219        props.max_brightness = RADEON_MAX_BL_LEVEL;
 220        props.type = BACKLIGHT_RAW;
 221        snprintf(bl_name, sizeof(bl_name),
 222                 "radeon_bl%d", dev->primary->index);
 223        bd = backlight_device_register(bl_name, drm_connector->kdev,
 224                                       pdata, &radeon_atom_backlight_ops, &props);
 225        if (IS_ERR(bd)) {
 226                DRM_ERROR("Backlight registration failed\n");
 227                goto error;
 228        }
 229
 230        pdata->encoder = radeon_encoder;
 231
 232        dig = radeon_encoder->enc_priv;
 233        dig->bl_dev = bd;
 234
 235        bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 236        /* Set a reasonable default here if the level is 0 otherwise
 237         * fbdev will attempt to turn the backlight on after console
 238         * unblanking and it will try and restore 0 which turns the backlight
 239         * off again.
 240         */
 241        if (bd->props.brightness == 0)
 242                bd->props.brightness = RADEON_MAX_BL_LEVEL;
 243        bd->props.power = FB_BLANK_UNBLANK;
 244        backlight_update_status(bd);
 245
 246        DRM_INFO("radeon atom DIG backlight initialized\n");
 247        rdev->mode_info.bl_encoder = radeon_encoder;
 248
 249        return;
 250
 251error:
 252        kfree(pdata);
 253        return;
 254}
 255
 256static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 257{
 258        struct drm_device *dev = radeon_encoder->base.dev;
 259        struct radeon_device *rdev = dev->dev_private;
 260        struct backlight_device *bd = NULL;
 261        struct radeon_encoder_atom_dig *dig;
 262
 263        if (!radeon_encoder->enc_priv)
 264                return;
 265
 266        if (!rdev->is_atom_bios)
 267                return;
 268
 269        if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 270                return;
 271
 272        dig = radeon_encoder->enc_priv;
 273        bd = dig->bl_dev;
 274        dig->bl_dev = NULL;
 275
 276        if (bd) {
 277                struct radeon_legacy_backlight_privdata *pdata;
 278
 279                pdata = bl_get_data(bd);
 280                backlight_device_unregister(bd);
 281                kfree(pdata);
 282
 283                DRM_INFO("radeon atom LVDS backlight unloaded\n");
 284        }
 285}
 286
 287#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 288
 289void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 290{
 291}
 292
 293static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 294{
 295}
 296
 297#endif
 298
 299/* evil but including atombios.h is much worse */
 300bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 301                                struct drm_display_mode *mode);
 302
 303static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 304                                   const struct drm_display_mode *mode,
 305                                   struct drm_display_mode *adjusted_mode)
 306{
 307        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 308        struct drm_device *dev = encoder->dev;
 309        struct radeon_device *rdev = dev->dev_private;
 310
 311        /* set the active encoder to connector routing */
 312        radeon_encoder_set_active_device(encoder);
 313        drm_mode_set_crtcinfo(adjusted_mode, 0);
 314
 315        /* hw bug */
 316        if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 317            && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 318                adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 319
 320        /* vertical FP must be at least 1 */
 321        if (mode->crtc_vsync_start == mode->crtc_vdisplay)
 322                adjusted_mode->crtc_vsync_start++;
 323
 324        /* get the native mode for scaling */
 325        if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 326                radeon_panel_mode_fixup(encoder, adjusted_mode);
 327        } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 328                struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 329                if (tv_dac) {
 330                        if (tv_dac->tv_std == TV_STD_NTSC ||
 331                            tv_dac->tv_std == TV_STD_NTSC_J ||
 332                            tv_dac->tv_std == TV_STD_PAL_M)
 333                                radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 334                        else
 335                                radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 336                }
 337        } else if (radeon_encoder->rmx_type != RMX_OFF) {
 338                radeon_panel_mode_fixup(encoder, adjusted_mode);
 339        }
 340
 341        if (ASIC_IS_DCE3(rdev) &&
 342            ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 343             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 344                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 345                radeon_dp_set_link_config(connector, adjusted_mode);
 346        }
 347
 348        return true;
 349}
 350
 351static void
 352atombios_dac_setup(struct drm_encoder *encoder, int action)
 353{
 354        struct drm_device *dev = encoder->dev;
 355        struct radeon_device *rdev = dev->dev_private;
 356        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 357        DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 358        int index = 0;
 359        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 360
 361        memset(&args, 0, sizeof(args));
 362
 363        switch (radeon_encoder->encoder_id) {
 364        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 365        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 366                index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 367                break;
 368        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 369        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 370                index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 371                break;
 372        }
 373
 374        args.ucAction = action;
 375
 376        if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 377                args.ucDacStandard = ATOM_DAC1_PS2;
 378        else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 379                args.ucDacStandard = ATOM_DAC1_CV;
 380        else {
 381                switch (dac_info->tv_std) {
 382                case TV_STD_PAL:
 383                case TV_STD_PAL_M:
 384                case TV_STD_SCART_PAL:
 385                case TV_STD_SECAM:
 386                case TV_STD_PAL_CN:
 387                        args.ucDacStandard = ATOM_DAC1_PAL;
 388                        break;
 389                case TV_STD_NTSC:
 390                case TV_STD_NTSC_J:
 391                case TV_STD_PAL_60:
 392                default:
 393                        args.ucDacStandard = ATOM_DAC1_NTSC;
 394                        break;
 395                }
 396        }
 397        args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 398
 399        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 400
 401}
 402
 403static void
 404atombios_tv_setup(struct drm_encoder *encoder, int action)
 405{
 406        struct drm_device *dev = encoder->dev;
 407        struct radeon_device *rdev = dev->dev_private;
 408        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 409        TV_ENCODER_CONTROL_PS_ALLOCATION args;
 410        int index = 0;
 411        struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 412
 413        memset(&args, 0, sizeof(args));
 414
 415        index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 416
 417        args.sTVEncoder.ucAction = action;
 418
 419        if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 420                args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 421        else {
 422                switch (dac_info->tv_std) {
 423                case TV_STD_NTSC:
 424                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 425                        break;
 426                case TV_STD_PAL:
 427                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 428                        break;
 429                case TV_STD_PAL_M:
 430                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 431                        break;
 432                case TV_STD_PAL_60:
 433                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 434                        break;
 435                case TV_STD_NTSC_J:
 436                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 437                        break;
 438                case TV_STD_SCART_PAL:
 439                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 440                        break;
 441                case TV_STD_SECAM:
 442                        args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 443                        break;
 444                case TV_STD_PAL_CN:
 445                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 446                        break;
 447                default:
 448                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 449                        break;
 450                }
 451        }
 452
 453        args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 454
 455        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 456
 457}
 458
 459static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 460{
 461        int bpc = 8;
 462
 463        if (encoder->crtc) {
 464                struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 465                bpc = radeon_crtc->bpc;
 466        }
 467
 468        switch (bpc) {
 469        case 0:
 470                return PANEL_BPC_UNDEFINE;
 471        case 6:
 472                return PANEL_6BIT_PER_COLOR;
 473        case 8:
 474        default:
 475                return PANEL_8BIT_PER_COLOR;
 476        case 10:
 477                return PANEL_10BIT_PER_COLOR;
 478        case 12:
 479                return PANEL_12BIT_PER_COLOR;
 480        case 16:
 481                return PANEL_16BIT_PER_COLOR;
 482        }
 483}
 484
 485union dvo_encoder_control {
 486        ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 487        DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 488        DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 489        DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 490};
 491
 492void
 493atombios_dvo_setup(struct drm_encoder *encoder, int action)
 494{
 495        struct drm_device *dev = encoder->dev;
 496        struct radeon_device *rdev = dev->dev_private;
 497        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 498        union dvo_encoder_control args;
 499        int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 500        uint8_t frev, crev;
 501
 502        memset(&args, 0, sizeof(args));
 503
 504        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 505                return;
 506
 507        /* some R4xx chips have the wrong frev */
 508        if (rdev->family <= CHIP_RV410)
 509                frev = 1;
 510
 511        switch (frev) {
 512        case 1:
 513                switch (crev) {
 514                case 1:
 515                        /* R4xx, R5xx */
 516                        args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 517
 518                        if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 519                                args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 520
 521                        args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 522                        break;
 523                case 2:
 524                        /* RS600/690/740 */
 525                        args.dvo.sDVOEncoder.ucAction = action;
 526                        args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 527                        /* DFP1, CRT1, TV1 depending on the type of port */
 528                        args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 529
 530                        if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 531                                args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 532                        break;
 533                case 3:
 534                        /* R6xx */
 535                        args.dvo_v3.ucAction = action;
 536                        args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 537                        args.dvo_v3.ucDVOConfig = 0; /* XXX */
 538                        break;
 539                case 4:
 540                        /* DCE8 */
 541                        args.dvo_v4.ucAction = action;
 542                        args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 543                        args.dvo_v4.ucDVOConfig = 0; /* XXX */
 544                        args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 545                        break;
 546                default:
 547                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 548                        break;
 549                }
 550                break;
 551        default:
 552                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 553                break;
 554        }
 555
 556        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 557}
 558
 559union lvds_encoder_control {
 560        LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 561        LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 562};
 563
 564void
 565atombios_digital_setup(struct drm_encoder *encoder, int action)
 566{
 567        struct drm_device *dev = encoder->dev;
 568        struct radeon_device *rdev = dev->dev_private;
 569        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 570        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 571        union lvds_encoder_control args;
 572        int index = 0;
 573        int hdmi_detected = 0;
 574        uint8_t frev, crev;
 575
 576        if (!dig)
 577                return;
 578
 579        if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 580                hdmi_detected = 1;
 581
 582        memset(&args, 0, sizeof(args));
 583
 584        switch (radeon_encoder->encoder_id) {
 585        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 586                index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 587                break;
 588        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 589        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 590                index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 591                break;
 592        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 593                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 594                        index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 595                else
 596                        index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 597                break;
 598        }
 599
 600        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 601                return;
 602
 603        switch (frev) {
 604        case 1:
 605        case 2:
 606                switch (crev) {
 607                case 1:
 608                        args.v1.ucMisc = 0;
 609                        args.v1.ucAction = action;
 610                        if (hdmi_detected)
 611                                args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 612                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 613                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 614                                if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 615                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 616                                if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 617                                        args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 618                        } else {
 619                                if (dig->linkb)
 620                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 621                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 622                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 623                                /*if (pScrn->rgbBits == 8) */
 624                                args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 625                        }
 626                        break;
 627                case 2:
 628                case 3:
 629                        args.v2.ucMisc = 0;
 630                        args.v2.ucAction = action;
 631                        if (crev == 3) {
 632                                if (dig->coherent_mode)
 633                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 634                        }
 635                        if (hdmi_detected)
 636                                args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 637                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 638                        args.v2.ucTruncate = 0;
 639                        args.v2.ucSpatial = 0;
 640                        args.v2.ucTemporal = 0;
 641                        args.v2.ucFRC = 0;
 642                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 643                                if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 644                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 645                                if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 646                                        args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 647                                        if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 648                                                args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 649                                }
 650                                if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 651                                        args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 652                                        if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 653                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 654                                        if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 655                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 656                                }
 657                        } else {
 658                                if (dig->linkb)
 659                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 660                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 661                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 662                        }
 663                        break;
 664                default:
 665                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 666                        break;
 667                }
 668                break;
 669        default:
 670                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 671                break;
 672        }
 673
 674        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 675}
 676
 677int
 678atombios_get_encoder_mode(struct drm_encoder *encoder)
 679{
 680        struct drm_device *dev = encoder->dev;
 681        struct radeon_device *rdev = dev->dev_private;
 682        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 683        struct drm_connector *connector;
 684        struct radeon_connector *radeon_connector;
 685        struct radeon_connector_atom_dig *dig_connector;
 686        struct radeon_encoder_atom_dig *dig_enc;
 687
 688        if (radeon_encoder_is_digital(encoder)) {
 689                dig_enc = radeon_encoder->enc_priv;
 690                if (dig_enc->active_mst_links)
 691                        return ATOM_ENCODER_MODE_DP_MST;
 692        }
 693        if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 694                return ATOM_ENCODER_MODE_DP_MST;
 695        /* dp bridges are always DP */
 696        if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 697                return ATOM_ENCODER_MODE_DP;
 698
 699        /* DVO is always DVO */
 700        if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 701            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 702                return ATOM_ENCODER_MODE_DVO;
 703
 704        connector = radeon_get_connector_for_encoder(encoder);
 705        /* if we don't have an active device yet, just use one of
 706         * the connectors tied to the encoder.
 707         */
 708        if (!connector)
 709                connector = radeon_get_connector_for_encoder_init(encoder);
 710        radeon_connector = to_radeon_connector(connector);
 711
 712        switch (connector->connector_type) {
 713        case DRM_MODE_CONNECTOR_DVII:
 714        case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 715                if (radeon_audio != 0) {
 716                        if (radeon_connector->use_digital &&
 717                            (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 718                                return ATOM_ENCODER_MODE_HDMI;
 719                        else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 720                                 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 721                                return ATOM_ENCODER_MODE_HDMI;
 722                        else if (radeon_connector->use_digital)
 723                                return ATOM_ENCODER_MODE_DVI;
 724                        else
 725                                return ATOM_ENCODER_MODE_CRT;
 726                } else if (radeon_connector->use_digital) {
 727                        return ATOM_ENCODER_MODE_DVI;
 728                } else {
 729                        return ATOM_ENCODER_MODE_CRT;
 730                }
 731                break;
 732        case DRM_MODE_CONNECTOR_DVID:
 733        case DRM_MODE_CONNECTOR_HDMIA:
 734        default:
 735                if (radeon_audio != 0) {
 736                        if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 737                                return ATOM_ENCODER_MODE_HDMI;
 738                        else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 739                                 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 740                                return ATOM_ENCODER_MODE_HDMI;
 741                        else
 742                                return ATOM_ENCODER_MODE_DVI;
 743                } else {
 744                        return ATOM_ENCODER_MODE_DVI;
 745                }
 746                break;
 747        case DRM_MODE_CONNECTOR_LVDS:
 748                return ATOM_ENCODER_MODE_LVDS;
 749                break;
 750        case DRM_MODE_CONNECTOR_DisplayPort:
 751                dig_connector = radeon_connector->con_priv;
 752                if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 753                    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 754                        if (radeon_audio != 0 &&
 755                            drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 756                            ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 757                                return ATOM_ENCODER_MODE_DP_AUDIO;
 758                        return ATOM_ENCODER_MODE_DP;
 759                } else if (radeon_audio != 0) {
 760                        if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 761                                return ATOM_ENCODER_MODE_HDMI;
 762                        else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 763                                 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 764                                return ATOM_ENCODER_MODE_HDMI;
 765                        else
 766                                return ATOM_ENCODER_MODE_DVI;
 767                } else {
 768                        return ATOM_ENCODER_MODE_DVI;
 769                }
 770                break;
 771        case DRM_MODE_CONNECTOR_eDP:
 772                if (radeon_audio != 0 &&
 773                    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 774                    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 775                        return ATOM_ENCODER_MODE_DP_AUDIO;
 776                return ATOM_ENCODER_MODE_DP;
 777        case DRM_MODE_CONNECTOR_DVIA:
 778        case DRM_MODE_CONNECTOR_VGA:
 779                return ATOM_ENCODER_MODE_CRT;
 780                break;
 781        case DRM_MODE_CONNECTOR_Composite:
 782        case DRM_MODE_CONNECTOR_SVIDEO:
 783        case DRM_MODE_CONNECTOR_9PinDIN:
 784                /* fix me */
 785                return ATOM_ENCODER_MODE_TV;
 786                /*return ATOM_ENCODER_MODE_CV;*/
 787                break;
 788        }
 789}
 790
 791/*
 792 * DIG Encoder/Transmitter Setup
 793 *
 794 * DCE 3.0/3.1
 795 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 796 * Supports up to 3 digital outputs
 797 * - 2 DIG encoder blocks.
 798 * DIG1 can drive UNIPHY link A or link B
 799 * DIG2 can drive UNIPHY link B or LVTMA
 800 *
 801 * DCE 3.2
 802 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 803 * Supports up to 5 digital outputs
 804 * - 2 DIG encoder blocks.
 805 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 806 *
 807 * DCE 4.0/5.0/6.0
 808 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 809 * Supports up to 6 digital outputs
 810 * - 6 DIG encoder blocks.
 811 * - DIG to PHY mapping is hardcoded
 812 * DIG1 drives UNIPHY0 link A, A+B
 813 * DIG2 drives UNIPHY0 link B
 814 * DIG3 drives UNIPHY1 link A, A+B
 815 * DIG4 drives UNIPHY1 link B
 816 * DIG5 drives UNIPHY2 link A, A+B
 817 * DIG6 drives UNIPHY2 link B
 818 *
 819 * DCE 4.1
 820 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 821 * Supports up to 6 digital outputs
 822 * - 2 DIG encoder blocks.
 823 * llano
 824 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 825 * ontario
 826 * DIG1 drives UNIPHY0/1/2 link A
 827 * DIG2 drives UNIPHY0/1/2 link B
 828 *
 829 * Routing
 830 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 831 * Examples:
 832 * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 833 * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 834 * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 835 * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 836 */
 837
 838union dig_encoder_control {
 839        DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 840        DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 841        DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 842        DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 843};
 844
 845void
 846atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 847{
 848        struct drm_device *dev = encoder->dev;
 849        struct radeon_device *rdev = dev->dev_private;
 850        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 851        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 852        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 853        union dig_encoder_control args;
 854        int index = 0;
 855        uint8_t frev, crev;
 856        int dp_clock = 0;
 857        int dp_lane_count = 0;
 858        int hpd_id = RADEON_HPD_NONE;
 859
 860        if (connector) {
 861                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 862                struct radeon_connector_atom_dig *dig_connector =
 863                        radeon_connector->con_priv;
 864
 865                dp_clock = dig_connector->dp_clock;
 866                dp_lane_count = dig_connector->dp_lane_count;
 867                hpd_id = radeon_connector->hpd.hpd;
 868        }
 869
 870        /* no dig encoder assigned */
 871        if (dig->dig_encoder == -1)
 872                return;
 873
 874        memset(&args, 0, sizeof(args));
 875
 876        if (ASIC_IS_DCE4(rdev))
 877                index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 878        else {
 879                if (dig->dig_encoder)
 880                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 881                else
 882                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 883        }
 884
 885        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 886                return;
 887
 888        switch (frev) {
 889        case 1:
 890                switch (crev) {
 891                case 1:
 892                        args.v1.ucAction = action;
 893                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 894                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 895                                args.v3.ucPanelMode = panel_mode;
 896                        else
 897                                args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 898
 899                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 900                                args.v1.ucLaneNum = dp_lane_count;
 901                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 902                                args.v1.ucLaneNum = 8;
 903                        else
 904                                args.v1.ucLaneNum = 4;
 905
 906                        switch (radeon_encoder->encoder_id) {
 907                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 908                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 909                                break;
 910                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 911                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 912                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 913                                break;
 914                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 915                                args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 916                                break;
 917                        }
 918                        if (dig->linkb)
 919                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 920                        else
 921                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 922
 923                        if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 924                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 925
 926                        break;
 927                case 2:
 928                case 3:
 929                        args.v3.ucAction = action;
 930                        args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 931                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 932                                args.v3.ucPanelMode = panel_mode;
 933                        else
 934                                args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 935
 936                        if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 937                                args.v3.ucLaneNum = dp_lane_count;
 938                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 939                                args.v3.ucLaneNum = 8;
 940                        else
 941                                args.v3.ucLaneNum = 4;
 942
 943                        if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 944                                args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 945                        if (enc_override != -1)
 946                                args.v3.acConfig.ucDigSel = enc_override;
 947                        else
 948                                args.v3.acConfig.ucDigSel = dig->dig_encoder;
 949                        args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 950                        break;
 951                case 4:
 952                        args.v4.ucAction = action;
 953                        args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 954                        if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 955                                args.v4.ucPanelMode = panel_mode;
 956                        else
 957                                args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 958
 959                        if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 960                                args.v4.ucLaneNum = dp_lane_count;
 961                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 962                                args.v4.ucLaneNum = 8;
 963                        else
 964                                args.v4.ucLaneNum = 4;
 965
 966                        if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 967                                if (dp_clock == 540000)
 968                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 969                                else if (dp_clock == 324000)
 970                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 971                                else if (dp_clock == 270000)
 972                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 973                                else
 974                                        args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 975                        }
 976
 977                        if (enc_override != -1)
 978                                args.v4.acConfig.ucDigSel = enc_override;
 979                        else
 980                                args.v4.acConfig.ucDigSel = dig->dig_encoder;
 981                        args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 982                        if (hpd_id == RADEON_HPD_NONE)
 983                                args.v4.ucHPD_ID = 0;
 984                        else
 985                                args.v4.ucHPD_ID = hpd_id + 1;
 986                        break;
 987                default:
 988                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 989                        break;
 990                }
 991                break;
 992        default:
 993                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 994                break;
 995        }
 996
 997        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 998
 999}
1000

1001void
1002atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
1003{
1004        atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1005}
1006
1007union dig_transmitter_control {
1008        DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1009        DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1010        DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1011        DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1012        DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1013};
1014
1015void
1016atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1017{
1018        struct drm_device *dev = encoder->dev;
1019        struct radeon_device *rdev = dev->dev_private;
1020        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1021        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1022        struct drm_connector *connector;
1023        union dig_transmitter_control args;
1024        int index = 0;
1025        uint8_t frev, crev;
1026        bool is_dp = false;
1027        int pll_id = 0;
1028        int dp_clock = 0;
1029        int dp_lane_count = 0;
1030        int connector_object_id = 0;
1031        int igp_lane_info = 0;
1032        int dig_encoder = dig->dig_encoder;
1033        int hpd_id = RADEON_HPD_NONE;
1034
1035        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1036                connector = radeon_get_connector_for_encoder_init(encoder);
1037                /* just needed to avoid bailing in the encoder check.  the encoder
1038                 * isn't used for init
1039                 */
1040                dig_encoder = 0;
1041        } else
1042                connector = radeon_get_connector_for_encoder(encoder);
1043
1044        if (connector) {
1045                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1046                struct radeon_connector_atom_dig *dig_connector =
1047                        radeon_connector->con_priv;
1048
1049                hpd_id = radeon_connector->hpd.hpd;
1050                dp_clock = dig_connector->dp_clock;
1051                dp_lane_count = dig_connector->dp_lane_count;
1052                connector_object_id =
1053                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1054                igp_lane_info = dig_connector->igp_lane_info;
1055        }
1056
1057        if (encoder->crtc) {
1058                struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1059                pll_id = radeon_crtc->pll_id;
1060        }
1061
1062        /* no dig encoder assigned */
1063        if (dig_encoder == -1)
1064                return;
1065
1066        if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1067                is_dp = true;
1068
1069        memset(&args, 0, sizeof(args));
1070
1071        switch (radeon_encoder->encoder_id) {
1072        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1073                index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1074                break;
1075        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1076        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1077        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1078        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1079                index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1080                break;
1081        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1082                index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1083                break;
1084        }
1085
1086        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1087                return;
1088
1089        switch (frev) {
1090        case 1:
1091                switch (crev) {
1092                case 1:
1093                        args.v1.ucAction = action;
1094                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1095                                args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1096                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1097                                args.v1.asMode.ucLaneSel = lane_num;
1098                                args.v1.asMode.ucLaneSet = lane_set;
1099                        } else {
1100                                if (is_dp)
1101                                        args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1102                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1103                                        args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1104                                else
1105                                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1106                        }
1107
1108                        args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1109
1110                        if (dig_encoder)
1111                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1112                        else
1113                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1114
1115                        if ((rdev->flags & RADEON_IS_IGP) &&
1116                            (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1117                                if (is_dp ||
1118                                    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1119                                        if (igp_lane_info & 0x1)
1120                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1121                                        else if (igp_lane_info & 0x2)
1122                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1123                                        else if (igp_lane_info & 0x4)
1124                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1125                                        else if (igp_lane_info & 0x8)
1126                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1127                                } else {
1128                                        if (igp_lane_info & 0x3)
1129                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1130                                        else if (igp_lane_info & 0xc)
1131                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1132                                }
1133                        }
1134
1135                        if (dig->linkb)
1136                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1137                        else
1138                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1139
1140                        if (is_dp)
1141                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1142                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1143                                if (dig->coherent_mode)
1144                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1145                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1146                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1147                        }
1148                        break;
1149                case 2:
1150                        args.v2.ucAction = action;
1151                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1152                                args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1153                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1154                                args.v2.asMode.ucLaneSel = lane_num;
1155                                args.v2.asMode.ucLaneSet = lane_set;
1156                        } else {
1157                                if (is_dp)
1158                                        args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1159                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1160                                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1161                                else
1162                                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1163                        }
1164
1165                        args.v2.acConfig.ucEncoderSel = dig_encoder;
1166                        if (dig->linkb)
1167                                args.v2.acConfig.ucLinkSel = 1;
1168
1169                        switch (radeon_encoder->encoder_id) {
1170                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1171                                args.v2.acConfig.ucTransmitterSel = 0;
1172                                break;
1173                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1174                                args.v2.acConfig.ucTransmitterSel = 1;
1175                                break;
1176                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1177                                args.v2.acConfig.ucTransmitterSel = 2;
1178                                break;
1179                        }
1180
1181                        if (is_dp) {
1182                                args.v2.acConfig.fCoherentMode = 1;
1183                                args.v2.acConfig.fDPConnector = 1;
1184                        } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1185                                if (dig->coherent_mode)
1186                                        args.v2.acConfig.fCoherentMode = 1;
1187                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1188                                        args.v2.acConfig.fDualLinkConnector = 1;
1189                        }
1190                        break;
1191                case 3:
1192                        args.v3.ucAction = action;
1193                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1194                                args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1195                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1196                                args.v3.asMode.ucLaneSel = lane_num;
1197                                args.v3.asMode.ucLaneSet = lane_set;
1198                        } else {
1199                                if (is_dp)
1200                                        args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1201                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1202                                        args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1203                                else
1204                                        args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1205                        }
1206
1207                        if (is_dp)
1208                                args.v3.ucLaneNum = dp_lane_count;
1209                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1210                                args.v3.ucLaneNum = 8;
1211                        else
1212                                args.v3.ucLaneNum = 4;
1213
1214                        if (dig->linkb)
1215                                args.v3.acConfig.ucLinkSel = 1;
1216                        if (dig_encoder & 1)
1217                                args.v3.acConfig.ucEncoderSel = 1;
1218
1219                        /* Select the PLL for the PHY
1220                         * DP PHY should be clocked from external src if there is
1221                         * one.
1222                         */
1223                        /* On DCE4, if there is an external clock, it generates the DP ref clock */
1224                        if (is_dp && rdev->clock.dp_extclk)
1225                                args.v3.acConfig.ucRefClkSource = 2; /* external src */
1226                        else
1227                                args.v3.acConfig.ucRefClkSource = pll_id;
1228
1229                        switch (radeon_encoder->encoder_id) {
1230                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1231                                args.v3.acConfig.ucTransmitterSel = 0;
1232                                break;
1233                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1234                                args.v3.acConfig.ucTransmitterSel = 1;
1235                                break;
1236                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1237                                args.v3.acConfig.ucTransmitterSel = 2;
1238                                break;
1239                        }
1240
1241                        if (is_dp)
1242                                args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1243                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1244                                if (dig->coherent_mode)
1245                                        args.v3.acConfig.fCoherentMode = 1;
1246                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1247                                        args.v3.acConfig.fDualLinkConnector = 1;
1248                        }
1249                        break;
1250                case 4:
1251                        args.v4.ucAction = action;
1252                        if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1253                                args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1254                        } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1255                                args.v4.asMode.ucLaneSel = lane_num;
1256                                args.v4.asMode.ucLaneSet = lane_set;
1257                        } else {
1258                                if (is_dp)
1259                                        args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1260                                else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1261                                        args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1262                                else
1263                                        args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1264                        }
1265
1266                        if (is_dp)
1267                                args.v4.ucLaneNum = dp_lane_count;
1268                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1269                                args.v4.ucLaneNum = 8;
1270                        else
1271                                args.v4.ucLaneNum = 4;
1272
1273                        if (dig->linkb)
1274                                args.v4.acConfig.ucLinkSel = 1;
1275                        if (dig_encoder & 1)
1276                                args.v4.acConfig.ucEncoderSel = 1;
1277
1278                        /* Select the PLL for the PHY
1279                         * DP PHY should be clocked from external src if there is
1280                         * one.
1281                         */
1282                        /* On DCE5 DCPLL usually generates the DP ref clock */
1283                        if (is_dp) {
1284                                if (rdev->clock.dp_extclk)
1285                                        args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1286                                else
1287                                        args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1288                        } else
1289                                args.v4.acConfig.ucRefClkSource = pll_id;
1290
1291                        switch (radeon_encoder->encoder_id) {
1292                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1293                                args.v4.acConfig.ucTransmitterSel = 0;
1294                                break;
1295                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1296                                args.v4.acConfig.ucTransmitterSel = 1;
1297                                break;
1298                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1299                                args.v4.acConfig.ucTransmitterSel = 2;
1300                                break;
1301                        }
1302
1303                        if (is_dp)
1304                                args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1305                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1306                                if (dig->coherent_mode)
1307                                        args.v4.acConfig.fCoherentMode = 1;
1308                                if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1309                                        args.v4.acConfig.fDualLinkConnector = 1;
1310                        }
1311                        break;
1312                case 5:
1313                        args.v5.ucAction = action;
1314                        if (is_dp)
1315                                args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1316                        else
1317                                args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1318
1319                        switch (radeon_encoder->encoder_id) {
1320                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1321                                if (dig->linkb)
1322                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1323                                else
1324                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1325                                break;
1326                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1327                                if (dig->linkb)
1328                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1329                                else
1330                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1331                                break;
1332                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1333                                if (dig->linkb)
1334                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1335                                else
1336                                        args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1337                                break;
1338                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1339                                args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1340                                break;
1341                        }
1342                        if (is_dp)
1343                                args.v5.ucLaneNum = dp_lane_count;
1344                        else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1345                                args.v5.ucLaneNum = 8;
1346                        else
1347                                args.v5.ucLaneNum = 4;
1348                        args.v5.ucConnObjId = connector_object_id;
1349                        args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1350
1351                        if (is_dp && rdev->clock.dp_extclk)
1352                                args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1353                        else
1354                                args.v5.asConfig.ucPhyClkSrcId = pll_id;
1355
1356                        if (is_dp)
1357                                args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1358                        else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1359                                if (dig->coherent_mode)
1360                                        args.v5.asConfig.ucCoherentMode = 1;
1361                        }
1362                        if (hpd_id == RADEON_HPD_NONE)
1363                                args.v5.asConfig.ucHPDSel = 0;
1364                        else
1365                                args.v5.asConfig.ucHPDSel = hpd_id + 1;
1366                        args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1367                        args.v5.ucDPLaneSet = lane_set;
1368                        break;
1369                default:
1370                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1371                        break;
1372                }
1373                break;
1374        default:
1375                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1376                break;
1377        }
1378
1379        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1380}
1381
1382void
1383atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1384{
1385        atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1386}
1387
1388bool
1389atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1390{
1391        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1392        struct drm_device *dev = radeon_connector->base.dev;
1393        struct radeon_device *rdev = dev->dev_private;
1394        union dig_transmitter_control args;
1395        int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1396        uint8_t frev, crev;
1397
1398        if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1399                goto done;
1400
1401        if (!ASIC_IS_DCE4(rdev))
1402                goto done;
1403
1404        if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1405            (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1406                goto done;
1407
1408        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1409                goto done;
1410
1411        memset(&args, 0, sizeof(args));
1412
1413        args.v1.ucAction = action;
1414
1415        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1416
1417        /* wait for the panel to power up */
1418        if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1419                int i;
1420
1421                for (i = 0; i < 300; i++) {
1422                        if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1423                                return true;
1424                        mdelay(1);
1425                }
1426                return false;
1427        }
1428done:
1429        return true;
1430}
1431
1432union external_encoder_control {
1433        EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1434        EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1435};
1436
1437static void
1438atombios_external_encoder_setup(struct drm_encoder *encoder,
1439                                struct drm_encoder *ext_encoder,
1440                                int action)
1441{
1442        struct drm_device *dev = encoder->dev;
1443        struct radeon_device *rdev = dev->dev_private;
1444        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1445        struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1446        union external_encoder_control args;
1447        struct drm_connector *connector;
1448        int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1449        u8 frev, crev;
1450        int dp_clock = 0;
1451        int dp_lane_count = 0;
1452        int connector_object_id = 0;
1453        u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1454
1455        if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1456                connector = radeon_get_connector_for_encoder_init(encoder);
1457        else
1458                connector = radeon_get_connector_for_encoder(encoder);
1459
1460        if (connector) {
1461                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1462                struct radeon_connector_atom_dig *dig_connector =
1463                        radeon_connector->con_priv;
1464
1465                dp_clock = dig_connector->dp_clock;
1466                dp_lane_count = dig_connector->dp_lane_count;
1467                connector_object_id =
1468                        (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1469        }
1470
1471        memset(&args, 0, sizeof(args));
1472
1473        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1474                return;
1475
1476        switch (frev) {
1477        case 1:
1478                /* no params on frev 1 */
1479                break;
1480        case 2:
1481                switch (crev) {
1482                case 1:
1483                case 2:
1484                        args.v1.sDigEncoder.ucAction = action;
1485                        args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1486                        args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1487
1488                        if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1489                                if (dp_clock == 270000)
1490                                        args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1491                                args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1492                        } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1493                                args.v1.sDigEncoder.ucLaneNum = 8;
1494                        else
1495                                args.v1.sDigEncoder.ucLaneNum = 4;
1496                        break;
1497                case 3:
1498                        args.v3.sExtEncoder.ucAction = action;
1499                        if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1500                                args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1501                        else
1502                                args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1503                        args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1504
1505                        if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1506                                if (dp_clock == 270000)
1507                                        args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1508                                else if (dp_clock == 540000)
1509                                        args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1510                                args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1511                        } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1512                                args.v3.sExtEncoder.ucLaneNum = 8;
1513                        else
1514                                args.v3.sExtEncoder.ucLaneNum = 4;
1515                        switch (ext_enum) {
1516                        case GRAPH_OBJECT_ENUM_ID1:
1517                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1518                                break;
1519                        case GRAPH_OBJECT_ENUM_ID2:
1520                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1521                                break;
1522                        case GRAPH_OBJECT_ENUM_ID3:
1523                                args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1524                                break;
1525                        }
1526                        args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1527                        break;
1528                default:
1529                        DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1530                        return;
1531                }
1532                break;
1533        default:
1534                DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1535                return;
1536        }
1537        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1538}
1539
1540static void
1541atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1542{
1543        struct drm_device *dev = encoder->dev;
1544        struct radeon_device *rdev = dev->dev_private;
1545        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1546        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1547        ENABLE_YUV_PS_ALLOCATION args;
1548        int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1549        uint32_t temp, reg;
1550
1551        memset(&args, 0, sizeof(args));
1552
1553        if (rdev->family >= CHIP_R600)
1554                reg = R600_BIOS_3_SCRATCH;
1555        else
1556                reg = RADEON_BIOS_3_SCRATCH;
1557
1558        /* XXX: fix up scratch reg handling */
1559        temp = RREG32(reg);
1560        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1561                WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1562                             (radeon_crtc->crtc_id << 18)));
1563        else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1564                WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1565        else
1566                WREG32(reg, 0);
1567
1568        if (enable)
1569                args.ucEnable = ATOM_ENABLE;
1570        args.ucCRTC = radeon_crtc->crtc_id;
1571
1572        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1573
1574        WREG32(reg, temp);
1575}
1576
1577static void
1578radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1579{
1580        struct drm_device *dev = encoder->dev;
1581        struct radeon_device *rdev = dev->dev_private;
1582        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1583        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1584        int index = 0;
1585
1586        memset(&args, 0, sizeof(args));
1587
1588        switch (radeon_encoder->encoder_id) {
1589        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1590        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1591                index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1592                break;
1593        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1594        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1595        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1596                index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1597                break;
1598        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1599                index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1600                break;
1601        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1602                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1603                        index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1604                else
1605                        index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1606                break;
1607        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1608        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1609                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1610                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1611                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1612                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1613                else
1614                        index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1615                break;
1616        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1617        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1618                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1619                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1620                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1621                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1622                else
1623                        index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1624                break;
1625        default:
1626                return;
1627        }
1628
1629        switch (mode) {
1630        case DRM_MODE_DPMS_ON:
1631                args.ucAction = ATOM_ENABLE;
1632                /* workaround for DVOOutputControl on some RS690 systems */
1633                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1634                        u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1635                        WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1636                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1637                        WREG32(RADEON_BIOS_3_SCRATCH, reg);
1638                } else
1639                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1640                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1641                        if (rdev->mode_info.bl_encoder) {
1642                                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1643
1644                                atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1645                        } else {
1646                                args.ucAction = ATOM_LCD_BLON;
1647                                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1648                        }
1649                }
1650                break;
1651        case DRM_MODE_DPMS_STANDBY:
1652        case DRM_MODE_DPMS_SUSPEND:
1653        case DRM_MODE_DPMS_OFF:
1654                args.ucAction = ATOM_DISABLE;
1655                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1656                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1657                        args.ucAction = ATOM_LCD_BLOFF;
1658                        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1659                }
1660                break;
1661        }
1662}
1663
1664static void
1665radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1666{
1667        struct drm_device *dev = encoder->dev;
1668        struct radeon_device *rdev = dev->dev_private;
1669        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1670        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1671        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1672        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1673        struct radeon_connector *radeon_connector = NULL;
1674        struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1675        bool travis_quirk = false;
1676
1677        if (connector) {
1678                radeon_connector = to_radeon_connector(connector);
1679                radeon_dig_connector = radeon_connector->con_priv;
1680                if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1681                     ENCODER_OBJECT_ID_TRAVIS) &&
1682                    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1683                    !ASIC_IS_DCE5(rdev))
1684                        travis_quirk = true;
1685        }
1686
1687        switch (mode) {
1688        case DRM_MODE_DPMS_ON:
1689                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1690                        if (!connector)
1691                                dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1692                        else
1693                                dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1694
1695                        /* setup and enable the encoder */
1696                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1697                        atombios_dig_encoder_setup(encoder,
1698                                                   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1699                                                   dig->panel_mode);
1700                        if (ext_encoder) {
1701                                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1702                                        atombios_external_encoder_setup(encoder, ext_encoder,
1703                                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1704                        }
1705                } else if (ASIC_IS_DCE4(rdev)) {
1706                        /* setup and enable the encoder */
1707                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1708                } else {
1709                        /* setup and enable the encoder and transmitter */
1710                        atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1711                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1712                }
1713                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1714                        if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1715                                atombios_set_edp_panel_power(connector,
1716                                                             ATOM_TRANSMITTER_ACTION_POWER_ON);
1717                                radeon_dig_connector->edp_on = true;
1718                        }
1719                }
1720                /* enable the transmitter */
1721                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1722                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1723                        /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1724                        radeon_dp_link_train(encoder, connector);
1725                        if (ASIC_IS_DCE4(rdev))
1726                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1727                }
1728                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1729                        if (rdev->mode_info.bl_encoder)
1730                                atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1731                        else
1732                                atombios_dig_transmitter_setup(encoder,
1733                                                               ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1734                }
1735                if (ext_encoder)
1736                        atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1737                break;
1738        case DRM_MODE_DPMS_STANDBY:
1739        case DRM_MODE_DPMS_SUSPEND:
1740        case DRM_MODE_DPMS_OFF:
1741
1742                /* don't power off encoders with active MST links */
1743                if (dig->active_mst_links)
1744                        return;
1745
1746                if (ASIC_IS_DCE4(rdev)) {
1747                        if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1748                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1749                }
1750                if (ext_encoder)
1751                        atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1752                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1753                        atombios_dig_transmitter_setup(encoder,
1754                                                       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1755
1756                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1757                    connector && !travis_quirk)
1758                        radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1759                if (ASIC_IS_DCE4(rdev)) {
1760                        /* disable the transmitter */
1761                        atombios_dig_transmitter_setup(encoder,
1762                                                       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1763                } else {
1764                        /* disable the encoder and transmitter */
1765                        atombios_dig_transmitter_setup(encoder,
1766                                                       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1767                        atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1768                }
1769                if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1770                        if (travis_quirk)
1771                                radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1772                        if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1773                                atombios_set_edp_panel_power(connector,
1774                                                             ATOM_TRANSMITTER_ACTION_POWER_OFF);
1775                                radeon_dig_connector->edp_on = false;
1776                        }
1777                }
1778                break;
1779        }
1780}
1781
1782static void
1783radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1784{
1785        struct drm_device *dev = encoder->dev;
1786        struct radeon_device *rdev = dev->dev_private;
1787        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1788        int encoder_mode = atombios_get_encoder_mode(encoder);
1789
1790        DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1791                  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1792                  radeon_encoder->active_device);
1793
1794        if ((radeon_audio != 0) &&
1795            ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1796             ENCODER_MODE_IS_DP(encoder_mode)))
1797                radeon_audio_dpms(encoder, mode);
1798
1799        switch (radeon_encoder->encoder_id) {
1800        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1801        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1802        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1803        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1804        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1805        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1806        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1807        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1808                radeon_atom_encoder_dpms_avivo(encoder, mode);
1809                break;
1810        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1811        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1812        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1813        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1814        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1815                radeon_atom_encoder_dpms_dig(encoder, mode);
1816                break;
1817        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1818                if (ASIC_IS_DCE5(rdev)) {
1819                        switch (mode) {
1820                        case DRM_MODE_DPMS_ON:
1821                                atombios_dvo_setup(encoder, ATOM_ENABLE);
1822                                break;
1823                        case DRM_MODE_DPMS_STANDBY:
1824                        case DRM_MODE_DPMS_SUSPEND:
1825                        case DRM_MODE_DPMS_OFF:
1826                                atombios_dvo_setup(encoder, ATOM_DISABLE);
1827                                break;
1828                        }
1829                } else if (ASIC_IS_DCE3(rdev))
1830                        radeon_atom_encoder_dpms_dig(encoder, mode);
1831                else
1832                        radeon_atom_encoder_dpms_avivo(encoder, mode);
1833                break;
1834        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1835        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1836                if (ASIC_IS_DCE5(rdev)) {
1837                        switch (mode) {
1838                        case DRM_MODE_DPMS_ON:
1839                                atombios_dac_setup(encoder, ATOM_ENABLE);
1840                                break;
1841                        case DRM_MODE_DPMS_STANDBY:
1842                        case DRM_MODE_DPMS_SUSPEND:
1843                        case DRM_MODE_DPMS_OFF:
1844                                atombios_dac_setup(encoder, ATOM_DISABLE);
1845                                break;
1846                        }
1847                } else
1848                        radeon_atom_encoder_dpms_avivo(encoder, mode);
1849                break;
1850        default:
1851                return;
1852        }
1853
1854        radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1855
1856}
1857
1858union crtc_source_param {
1859        SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1860        SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1861};
1862
1863static void
1864atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1865{
1866        struct drm_device *dev = encoder->dev;
1867        struct radeon_device *rdev = dev->dev_private;
1868        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1869        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1870        union crtc_source_param args;
1871        int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1872        uint8_t frev, crev;
1873        struct radeon_encoder_atom_dig *dig;
1874
1875        memset(&args, 0, sizeof(args));
1876
1877        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1878                return;
1879
1880        switch (frev) {
1881        case 1:
1882                switch (crev) {
1883                case 1:
1884                default:
1885                        if (ASIC_IS_AVIVO(rdev))
1886                                args.v1.ucCRTC = radeon_crtc->crtc_id;
1887                        else {
1888                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1889                                        args.v1.ucCRTC = radeon_crtc->crtc_id;
1890                                else
1891                                        args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1892                        }
1893                        switch (radeon_encoder->encoder_id) {
1894                        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1895                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1896                                args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1897                                break;
1898                        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1899                        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1900                                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1901                                        args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1902                                else
1903                                        args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1904                                break;
1905                        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1906                        case ENCODER_OBJECT_ID_INTERNAL_DDI:
1907                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1908                                args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1909                                break;
1910                        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1911                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1912                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1913                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1914                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1915                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1916                                else
1917                                        args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1918                                break;
1919                        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1920                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1921                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1922                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1923                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1924                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1925                                else
1926                                        args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1927                                break;
1928                        }
1929                        break;
1930                case 2:
1931                        args.v2.ucCRTC = radeon_crtc->crtc_id;
1932                        if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1933                                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1934
1935                                if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1936                                        args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1937                                else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1938                                        args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1939                                else
1940                                        args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1941                        } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1942                                args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1943                        } else {
1944                                args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1945                        }
1946                        switch (radeon_encoder->encoder_id) {
1947                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1948                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1949                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1950                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1951                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1952                                dig = radeon_encoder->enc_priv;
1953                                switch (dig->dig_encoder) {
1954                                case 0:
1955                                        args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1956                                        break;
1957                                case 1:
1958                                        args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1959                                        break;
1960                                case 2:
1961                                        args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1962                                        break;
1963                                case 3:
1964                                        args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1965                                        break;
1966                                case 4:
1967                                        args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1968                                        break;
1969                                case 5:
1970                                        args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1971                                        break;
1972                                case 6:
1973                                        args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1974                                        break;
1975                                }
1976                                break;
1977                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1978                                args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1979                                break;
1980                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1981                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1982                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1983                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1984                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1985                                else
1986                                        args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1987                                break;
1988                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1989                                if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1990                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1991                                else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1992                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1993                                else
1994                                        args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1995                                break;
1996                        }
1997                        break;
1998                }
1999                break;
2000        default:

2001                DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
2002                return;
2003        }
2004
2005        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2006
2007        /* update scratch regs with new routing */
2008        radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2009}
2010
2011void
2012atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2013{
2014        struct drm_device *dev = encoder->dev;
2015        struct radeon_device *rdev = dev->dev_private;
2016        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2017        int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2018        uint8_t frev, crev;
2019        union crtc_source_param args;
2020
2021        memset(&args, 0, sizeof(args));
2022
2023        if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2024                return;
2025
2026        if (frev != 1 && crev != 2)
2027                DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2028
2029        args.v2.ucCRTC = radeon_crtc->crtc_id;
2030        args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2031
2032        switch (fe) {
2033        case 0:
2034                args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2035                break;
2036        case 1:
2037                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2038                break;
2039        case 2:
2040                args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2041                break;
2042        case 3:
2043                args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2044                break;
2045        case 4:
2046                args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2047                break;
2048        case 5:
2049                args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2050                break;
2051        case 6:
2052                args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2053                break;
2054        }
2055        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2056}
2057
2058static void
2059atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2060                              struct drm_display_mode *mode)
2061{
2062        struct drm_device *dev = encoder->dev;
2063        struct radeon_device *rdev = dev->dev_private;
2064        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2065        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2066
2067        /* Funky macbooks */
2068        if ((dev->pdev->device == 0x71C5) &&
2069            (dev->pdev->subsystem_vendor == 0x106b) &&
2070            (dev->pdev->subsystem_device == 0x0080)) {
2071                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2072                        uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2073
2074                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2075                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2076
2077                        WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2078                }
2079        }
2080
2081        /* set scaler clears this on some chips */
2082        if (ASIC_IS_AVIVO(rdev) &&
2083            (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2084                if (ASIC_IS_DCE8(rdev)) {
2085                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2086                                WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2087                                       CIK_INTERLEAVE_EN);
2088                        else
2089                                WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2090                } else if (ASIC_IS_DCE4(rdev)) {
2091                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2092                                WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2093                                       EVERGREEN_INTERLEAVE_EN);
2094                        else
2095                                WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2096                } else {
2097                        if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2098                                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2099                                       AVIVO_D1MODE_INTERLEAVE_EN);
2100                        else
2101                                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2102                }
2103        }
2104}
2105
2106void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2107{
2108        if (enc_idx < 0)
2109                return;
2110        rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2111}
2112
2113int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2114{
2115        struct drm_device *dev = encoder->dev;
2116        struct radeon_device *rdev = dev->dev_private;
2117        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2118        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2119        struct drm_encoder *test_encoder;
2120        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2121        uint32_t dig_enc_in_use = 0;
2122        int enc_idx = -1;
2123
2124        if (fe_idx >= 0) {
2125                enc_idx = fe_idx;
2126                goto assigned;
2127        }
2128        if (ASIC_IS_DCE6(rdev)) {
2129                /* DCE6 */
2130                switch (radeon_encoder->encoder_id) {
2131                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2132                        if (dig->linkb)
2133                                enc_idx = 1;
2134                        else
2135                                enc_idx = 0;
2136                        break;
2137                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2138                        if (dig->linkb)
2139                                enc_idx = 3;
2140                        else
2141                                enc_idx = 2;
2142                        break;
2143                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2144                        if (dig->linkb)
2145                                enc_idx = 5;
2146                        else
2147                                enc_idx = 4;
2148                        break;
2149                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2150                        enc_idx = 6;
2151                        break;
2152                }
2153                goto assigned;
2154        } else if (ASIC_IS_DCE4(rdev)) {
2155                /* DCE4/5 */
2156                if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2157                        /* ontario follows DCE4 */
2158                        if (rdev->family == CHIP_PALM) {
2159                                if (dig->linkb)
2160                                        enc_idx = 1;
2161                                else
2162                                        enc_idx = 0;
2163                        } else
2164                                /* llano follows DCE3.2 */
2165                                enc_idx = radeon_crtc->crtc_id;
2166                } else {
2167                        switch (radeon_encoder->encoder_id) {
2168                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2169                                if (dig->linkb)
2170                                        enc_idx = 1;
2171                                else
2172                                        enc_idx = 0;
2173                                break;
2174                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2175                                if (dig->linkb)
2176                                        enc_idx = 3;
2177                                else
2178                                        enc_idx = 2;
2179                                break;
2180                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2181                                if (dig->linkb)
2182                                        enc_idx = 5;
2183                                else
2184                                        enc_idx = 4;
2185                                break;
2186                        }
2187                }
2188                goto assigned;
2189        }
2190
2191        /*
2192         * On DCE32 any encoder can drive any block so usually just use crtc id,
2193         * but Apple thinks different at least on iMac10,1, so there use linkb,
2194         * otherwise the internal eDP panel will stay dark.
2195         */
2196        if (ASIC_IS_DCE32(rdev)) {
2197                if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2198                        enc_idx = (dig->linkb) ? 1 : 0;
2199                else
2200                        enc_idx = radeon_crtc->crtc_id;
2201
2202                goto assigned;
2203        }
2204
2205        /* on DCE3 - LVTMA can only be driven by DIGB */
2206        list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2207                struct radeon_encoder *radeon_test_encoder;
2208
2209                if (encoder == test_encoder)
2210                        continue;
2211
2212                if (!radeon_encoder_is_digital(test_encoder))
2213                        continue;
2214
2215                radeon_test_encoder = to_radeon_encoder(test_encoder);
2216                dig = radeon_test_encoder->enc_priv;
2217
2218                if (dig->dig_encoder >= 0)
2219                        dig_enc_in_use |= (1 << dig->dig_encoder);
2220        }
2221
2222        if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2223                if (dig_enc_in_use & 0x2)
2224                        DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2225                return 1;
2226        }
2227        if (!(dig_enc_in_use & 1))
2228                return 0;
2229        return 1;
2230
2231assigned:
2232        if (enc_idx == -1) {
2233                DRM_ERROR("Got encoder index incorrect - returning 0\n");
2234                return 0;
2235        }
2236        if (rdev->mode_info.active_encoders & (1 << enc_idx))
2237                DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2238
2239        rdev->mode_info.active_encoders |= (1 << enc_idx);
2240        return enc_idx;
2241}
2242
2243/* This only needs to be called once at startup */
2244void
2245radeon_atom_encoder_init(struct radeon_device *rdev)
2246{
2247        struct drm_device *dev = rdev->ddev;
2248        struct drm_encoder *encoder;
2249
2250        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2251                struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2252                struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2253
2254                switch (radeon_encoder->encoder_id) {
2255                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2256                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2257                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2258                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2259                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2260                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2261                        break;
2262                default:
2263                        break;
2264                }
2265
2266                if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2267                        atombios_external_encoder_setup(encoder, ext_encoder,
2268                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2269        }
2270}
2271
2272static void
2273radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2274                             struct drm_display_mode *mode,
2275                             struct drm_display_mode *adjusted_mode)
2276{
2277        struct drm_device *dev = encoder->dev;
2278        struct radeon_device *rdev = dev->dev_private;
2279        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2280        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2281        int encoder_mode;
2282
2283        radeon_encoder->pixel_clock = adjusted_mode->clock;
2284
2285        /* need to call this here rather than in prepare() since we need some crtc info */
2286        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2287
2288        if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2289                if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2290                        atombios_yuv_setup(encoder, true);
2291                else
2292                        atombios_yuv_setup(encoder, false);
2293        }
2294
2295        switch (radeon_encoder->encoder_id) {
2296        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2297        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2298        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2299        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2300                atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2301                break;
2302        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2303        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2304        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2305        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2306        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2307                /* handled in dpms */
2308                break;
2309        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2310        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2311        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2312                atombios_dvo_setup(encoder, ATOM_ENABLE);
2313                break;
2314        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2315        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2316        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2317        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2318                atombios_dac_setup(encoder, ATOM_ENABLE);
2319                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2320                        if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2321                                atombios_tv_setup(encoder, ATOM_ENABLE);
2322                        else
2323                                atombios_tv_setup(encoder, ATOM_DISABLE);
2324                }
2325                break;
2326        }
2327
2328        atombios_apply_encoder_quirks(encoder, adjusted_mode);
2329
2330        encoder_mode = atombios_get_encoder_mode(encoder);
2331        if (connector && (radeon_audio != 0) &&
2332            ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2333             ENCODER_MODE_IS_DP(encoder_mode)))
2334                radeon_audio_mode_set(encoder, adjusted_mode);
2335}
2336
2337static bool
2338atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2339{
2340        struct drm_device *dev = encoder->dev;
2341        struct radeon_device *rdev = dev->dev_private;
2342        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2343        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2344
2345        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2346                                       ATOM_DEVICE_CV_SUPPORT |
2347                                       ATOM_DEVICE_CRT_SUPPORT)) {
2348                DAC_LOAD_DETECTION_PS_ALLOCATION args;
2349                int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2350                uint8_t frev, crev;
2351
2352                memset(&args, 0, sizeof(args));
2353
2354                if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2355                        return false;
2356
2357                args.sDacload.ucMisc = 0;
2358
2359                if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2360                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2361                        args.sDacload.ucDacType = ATOM_DAC_A;
2362                else
2363                        args.sDacload.ucDacType = ATOM_DAC_B;
2364
2365                if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2366                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2367                else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2368                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2369                else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2370                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2371                        if (crev >= 3)
2372                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2373                } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2374                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2375                        if (crev >= 3)
2376                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2377                }
2378
2379                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2380
2381                return true;
2382        } else
2383                return false;
2384}
2385
2386static enum drm_connector_status
2387radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2388{
2389        struct drm_device *dev = encoder->dev;
2390        struct radeon_device *rdev = dev->dev_private;
2391        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2392        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2393        uint32_t bios_0_scratch;
2394
2395        if (!atombios_dac_load_detect(encoder, connector)) {
2396                DRM_DEBUG_KMS("detect returned false \n");
2397                return connector_status_unknown;
2398        }
2399
2400        if (rdev->family >= CHIP_R600)
2401                bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2402        else
2403                bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2404
2405        DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2406        if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2407                if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2408                        return connector_status_connected;
2409        }
2410        if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2411                if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2412                        return connector_status_connected;
2413        }
2414        if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2415                if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2416                        return connector_status_connected;
2417        }
2418        if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2419                if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2420                        return connector_status_connected; /* CTV */
2421                else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2422                        return connector_status_connected; /* STV */
2423        }
2424        return connector_status_disconnected;
2425}
2426
2427static enum drm_connector_status
2428radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2429{
2430        struct drm_device *dev = encoder->dev;
2431        struct radeon_device *rdev = dev->dev_private;
2432        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2433        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2434        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2435        u32 bios_0_scratch;
2436
2437        if (!ASIC_IS_DCE4(rdev))
2438                return connector_status_unknown;
2439
2440        if (!ext_encoder)
2441                return connector_status_unknown;
2442
2443        if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2444                return connector_status_unknown;
2445
2446        /* load detect on the dp bridge */
2447        atombios_external_encoder_setup(encoder, ext_encoder,
2448                                        EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2449
2450        bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2451
2452        DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2453        if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2454                if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2455                        return connector_status_connected;
2456        }
2457        if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2458                if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2459                        return connector_status_connected;
2460        }
2461        if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2462                if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2463                        return connector_status_connected;
2464        }
2465        if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2466                if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2467                        return connector_status_connected; /* CTV */
2468                else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2469                        return connector_status_connected; /* STV */
2470        }
2471        return connector_status_disconnected;
2472}
2473
2474void
2475radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2476{
2477        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2478
2479        if (ext_encoder)
2480                /* ddc_setup on the dp bridge */
2481                atombios_external_encoder_setup(encoder, ext_encoder,
2482                                                EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2483
2484}
2485
2486static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2487{
2488        struct radeon_device *rdev = encoder->dev->dev_private;
2489        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2490        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2491
2492        if ((radeon_encoder->active_device &
2493             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2494            (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2495             ENCODER_OBJECT_ID_NONE)) {
2496                struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2497                if (dig) {
2498                        if (dig->dig_encoder >= 0)
2499                                radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2500                        dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2501                        if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2502                                if (rdev->family >= CHIP_R600)
2503                                        dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2504                                else
2505                                        /* RS600/690/740 have only 1 afmt block */
2506                                        dig->afmt = rdev->mode_info.afmt[0];
2507                        }
2508                }
2509        }
2510
2511        radeon_atom_output_lock(encoder, true);
2512
2513        if (connector) {
2514                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2515
2516                /* select the clock/data port if it uses a router */
2517                if (radeon_connector->router.cd_valid)
2518                        radeon_router_select_cd_port(radeon_connector);
2519
2520                /* turn eDP panel on for mode set */
2521                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2522                        atombios_set_edp_panel_power(connector,
2523                                                     ATOM_TRANSMITTER_ACTION_POWER_ON);
2524        }
2525
2526        /* this is needed for the pll/ss setup to work correctly in some cases */
2527        atombios_set_encoder_crtc_source(encoder);
2528        /* set up the FMT blocks */
2529        if (ASIC_IS_DCE8(rdev))
2530                dce8_program_fmt(encoder);
2531        else if (ASIC_IS_DCE4(rdev))
2532                dce4_program_fmt(encoder);
2533        else if (ASIC_IS_DCE3(rdev))
2534                dce3_program_fmt(encoder);
2535        else if (ASIC_IS_AVIVO(rdev))
2536                avivo_program_fmt(encoder);
2537}
2538
2539static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2540{
2541        /* need to call this here as we need the crtc set up */
2542        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2543        radeon_atom_output_lock(encoder, false);
2544}
2545
2546static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2547{
2548        struct drm_device *dev = encoder->dev;
2549        struct radeon_device *rdev = dev->dev_private;
2550        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2551        struct radeon_encoder_atom_dig *dig;
2552
2553        /* check for pre-DCE3 cards with shared encoders;
2554         * can't really use the links individually, so don't disable
2555         * the encoder if it's in use by another connector
2556         */
2557        if (!ASIC_IS_DCE3(rdev)) {
2558                struct drm_encoder *other_encoder;
2559                struct radeon_encoder *other_radeon_encoder;
2560
2561                list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2562                        other_radeon_encoder = to_radeon_encoder(other_encoder);
2563                        if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2564                            drm_helper_encoder_in_use(other_encoder))
2565                                goto disable_done;
2566                }
2567        }
2568
2569        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2570
2571        switch (radeon_encoder->encoder_id) {
2572        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2573        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2574        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2575        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2576                atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2577                break;
2578        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2579        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2580        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2581        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2582        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2583                /* handled in dpms */
2584                break;
2585        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2586        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2587        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2588                atombios_dvo_setup(encoder, ATOM_DISABLE);
2589                break;
2590        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2591        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2592        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2593        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2594                atombios_dac_setup(encoder, ATOM_DISABLE);
2595                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2596                        atombios_tv_setup(encoder, ATOM_DISABLE);
2597                break;
2598        }
2599
2600disable_done:
2601        if (radeon_encoder_is_digital(encoder)) {
2602                if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2603                        if (rdev->asic->display.hdmi_enable)
2604                                radeon_hdmi_enable(rdev, encoder, false);
2605                }
2606                if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2607                        dig = radeon_encoder->enc_priv;
2608                        radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2609                        dig->dig_encoder = -1;
2610                        radeon_encoder->active_device = 0;
2611                }
2612        } else
2613                radeon_encoder->active_device = 0;
2614}
2615
2616/* these are handled by the primary encoders */
2617static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2618{
2619
2620}
2621
2622static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2623{
2624
2625}
2626
2627static void
2628radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2629                         struct drm_display_mode *mode,
2630                         struct drm_display_mode *adjusted_mode)
2631{
2632
2633}
2634
2635static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2636{
2637
2638}
2639
2640static void
2641radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2642{
2643
2644}
2645
2646static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2647        .dpms = radeon_atom_ext_dpms,
2648        .prepare = radeon_atom_ext_prepare,
2649        .mode_set = radeon_atom_ext_mode_set,
2650        .commit = radeon_atom_ext_commit,
2651        .disable = radeon_atom_ext_disable,
2652        /* no detect for TMDS/LVDS yet */
2653};
2654
2655static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2656        .dpms = radeon_atom_encoder_dpms,
2657        .mode_fixup = radeon_atom_mode_fixup,
2658        .prepare = radeon_atom_encoder_prepare,
2659        .mode_set = radeon_atom_encoder_mode_set,
2660        .commit = radeon_atom_encoder_commit,
2661        .disable = radeon_atom_encoder_disable,
2662        .detect = radeon_atom_dig_detect,
2663};
2664
2665static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2666        .dpms = radeon_atom_encoder_dpms,
2667        .mode_fixup = radeon_atom_mode_fixup,
2668        .prepare = radeon_atom_encoder_prepare,
2669        .mode_set = radeon_atom_encoder_mode_set,
2670        .commit = radeon_atom_encoder_commit,
2671        .detect = radeon_atom_dac_detect,
2672};
2673
2674void radeon_enc_destroy(struct drm_encoder *encoder)
2675{
2676        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2677        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2678                radeon_atom_backlight_exit(radeon_encoder);
2679        kfree(radeon_encoder->enc_priv);
2680        drm_encoder_cleanup(encoder);
2681        kfree(radeon_encoder);
2682}
2683
2684static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2685        .destroy = radeon_enc_destroy,
2686};
2687
2688static struct radeon_encoder_atom_dac *
2689radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2690{
2691        struct drm_device *dev = radeon_encoder->base.dev;
2692        struct radeon_device *rdev = dev->dev_private;
2693        struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2694
2695        if (!dac)
2696                return NULL;
2697
2698        dac->tv_std = radeon_atombios_get_tv_info(rdev);
2699        return dac;
2700}
2701
2702static struct radeon_encoder_atom_dig *
2703radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2704{
2705        int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2706        struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2707
2708        if (!dig)
2709                return NULL;
2710
2711        /* coherent mode by default */
2712        dig->coherent_mode = true;
2713        dig->dig_encoder = -1;
2714
2715        if (encoder_enum == 2)
2716                dig->linkb = true;
2717        else
2718                dig->linkb = false;
2719
2720        return dig;
2721}
2722
2723void
2724radeon_add_atom_encoder(struct drm_device *dev,
2725                        uint32_t encoder_enum,
2726                        uint32_t supported_device,
2727                        u16 caps)
2728{
2729        struct radeon_device *rdev = dev->dev_private;
2730        struct drm_encoder *encoder;
2731        struct radeon_encoder *radeon_encoder;
2732
2733        /* see if we already added it */
2734        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2735                radeon_encoder = to_radeon_encoder(encoder);
2736                if (radeon_encoder->encoder_enum == encoder_enum) {
2737                        radeon_encoder->devices |= supported_device;
2738                        return;
2739                }
2740
2741        }
2742
2743        /* add a new one */
2744        radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2745        if (!radeon_encoder)
2746                return;
2747
2748        encoder = &radeon_encoder->base;
2749        switch (rdev->num_crtc) {
2750        case 1:
2751                encoder->possible_crtcs = 0x1;
2752                break;
2753        case 2:
2754        default:
2755                encoder->possible_crtcs = 0x3;
2756                break;
2757        case 4:
2758                encoder->possible_crtcs = 0xf;
2759                break;
2760        case 6:
2761                encoder->possible_crtcs = 0x3f;
2762                break;
2763        }
2764
2765        radeon_encoder->enc_priv = NULL;
2766
2767        radeon_encoder->encoder_enum = encoder_enum;
2768        radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2769        radeon_encoder->devices = supported_device;
2770        radeon_encoder->rmx_type = RMX_OFF;
2771        radeon_encoder->underscan_type = UNDERSCAN_OFF;
2772        radeon_encoder->is_ext_encoder = false;
2773        radeon_encoder->caps = caps;
2774
2775        switch (radeon_encoder->encoder_id) {
2776        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2777        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2778        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2779        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2780                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2781                        radeon_encoder->rmx_type = RMX_FULL;
2782                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2783                                         DRM_MODE_ENCODER_LVDS, NULL);
2784                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2785                } else {
2786                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2787                                         DRM_MODE_ENCODER_TMDS, NULL);
2788                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2789                }
2790                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2791                break;
2792        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2793                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2794                                 DRM_MODE_ENCODER_DAC, NULL);
2795                radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2796                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2797                break;
2798        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2799        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2800        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2801                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2802                                 DRM_MODE_ENCODER_TVDAC, NULL);
2803                radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2804                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2805                break;
2806        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2807        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2808        case ENCODER_OBJECT_ID_INTERNAL_DDI:
2809        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2810        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2811        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2812        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2813        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2814                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2815                        radeon_encoder->rmx_type = RMX_FULL;
2816                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2817                                         DRM_MODE_ENCODER_LVDS, NULL);
2818                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2819                } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2820                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2821                                         DRM_MODE_ENCODER_DAC, NULL);
2822                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2823                } else {
2824                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2825                                         DRM_MODE_ENCODER_TMDS, NULL);
2826                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2827                }
2828                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2829                break;
2830        case ENCODER_OBJECT_ID_SI170B:
2831        case ENCODER_OBJECT_ID_CH7303:
2832        case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2833        case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2834        case ENCODER_OBJECT_ID_TITFP513:
2835        case ENCODER_OBJECT_ID_VT1623:
2836        case ENCODER_OBJECT_ID_HDMI_SI1930:
2837        case ENCODER_OBJECT_ID_TRAVIS:
2838        case ENCODER_OBJECT_ID_NUTMEG:
2839                /* these are handled by the primary encoders */
2840                radeon_encoder->is_ext_encoder = true;
2841                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2842                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2843                                         DRM_MODE_ENCODER_LVDS, NULL);
2844                else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2845                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2846                                         DRM_MODE_ENCODER_DAC, NULL);
2847                else
2848                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2849                                         DRM_MODE_ENCODER_TMDS, NULL);
2850                drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2851                break;
2852        }
2853}
2854