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12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/mv643xx_i2c.h>
19#include <linux/platform_device.h>
20#include <linux/reset.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_irq.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/delay.h>
28
29#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32
33#define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34#define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35#define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36#define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37#define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38#define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
39
40
41#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42#define MV64XXX_I2C_STATUS_MAST_START 0x08
43#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
58
59
60#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
69
70
71#define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72#define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78#define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
79
80
81#define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
82
83
84enum {
85 MV64XXX_I2C_STATE_INVALID,
86 MV64XXX_I2C_STATE_IDLE,
87 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
88 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
89 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
90 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
93};
94
95
96enum {
97 MV64XXX_I2C_ACTION_INVALID,
98 MV64XXX_I2C_ACTION_CONTINUE,
99 MV64XXX_I2C_ACTION_SEND_RESTART,
100 MV64XXX_I2C_ACTION_SEND_ADDR_1,
101 MV64XXX_I2C_ACTION_SEND_ADDR_2,
102 MV64XXX_I2C_ACTION_SEND_DATA,
103 MV64XXX_I2C_ACTION_RCV_DATA,
104 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
105 MV64XXX_I2C_ACTION_SEND_STOP,
106};
107
108struct mv64xxx_i2c_regs {
109 u8 addr;
110 u8 ext_addr;
111 u8 data;
112 u8 control;
113 u8 status;
114 u8 clock;
115 u8 soft_reset;
116};
117
118struct mv64xxx_i2c_data {
119 struct i2c_msg *msgs;
120 int num_msgs;
121 int irq;
122 u32 state;
123 u32 action;
124 u32 aborting;
125 u32 cntl_bits;
126 void __iomem *reg_base;
127 struct mv64xxx_i2c_regs reg_offsets;
128 u32 addr1;
129 u32 addr2;
130 u32 bytes_left;
131 u32 byte_posn;
132 u32 send_stop;
133 u32 block;
134 int rc;
135 u32 freq_m;
136 u32 freq_n;
137 struct clk *clk;
138 struct clk *reg_clk;
139 wait_queue_head_t waitq;
140 spinlock_t lock;
141 struct i2c_msg *msg;
142 struct i2c_adapter adapter;
143 bool offload_enabled;
144
145 bool errata_delay;
146 struct reset_control *rstc;
147 bool irq_clear_inverted;
148
149 bool clk_n_base_0;
150};
151
152static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
153 .addr = 0x00,
154 .ext_addr = 0x10,
155 .data = 0x04,
156 .control = 0x08,
157 .status = 0x0c,
158 .clock = 0x0c,
159 .soft_reset = 0x1c,
160};
161
162static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
163 .addr = 0x00,
164 .ext_addr = 0x04,
165 .data = 0x08,
166 .control = 0x0c,
167 .status = 0x10,
168 .clock = 0x14,
169 .soft_reset = 0x18,
170};
171
172static void
173mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
174 struct i2c_msg *msg)
175{
176 u32 dir = 0;
177
178 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
179 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
180
181 if (msg->flags & I2C_M_RD)
182 dir = 1;
183
184 if (msg->flags & I2C_M_TEN) {
185 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
186 drv_data->addr2 = (u32)msg->addr & 0xff;
187 } else {
188 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
189 drv_data->addr2 = 0;
190 }
191}
192
193
194
195
196
197
198
199
200
201
202static void
203mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
204{
205 if (drv_data->offload_enabled) {
206 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
208 writel(0, drv_data->reg_base +
209 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
210 writel(0, drv_data->reg_base +
211 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
212 }
213
214 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
215 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
216 drv_data->reg_base + drv_data->reg_offsets.clock);
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
219 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
220 drv_data->reg_base + drv_data->reg_offsets.control);
221 drv_data->state = MV64XXX_I2C_STATE_IDLE;
222}
223
224static void
225mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
226{
227
228
229
230
231
232 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
233 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
234 return;
235 }
236
237
238 switch (status) {
239
240 case MV64XXX_I2C_STATUS_MAST_START:
241 case MV64XXX_I2C_STATUS_MAST_REPEAT_START:
242 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
243 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
244 break;
245
246
247 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK:
248 if (drv_data->msg->flags & I2C_M_TEN) {
249 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
250 drv_data->state =
251 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
252 break;
253 }
254 fallthrough;
255 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK:
256 case MV64XXX_I2C_STATUS_MAST_WR_ACK:
257 if ((drv_data->bytes_left == 0)
258 || (drv_data->aborting
259 && (drv_data->byte_posn != 0))) {
260 if (drv_data->send_stop || drv_data->aborting) {
261 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
262 drv_data->state = MV64XXX_I2C_STATE_IDLE;
263 } else {
264 drv_data->action =
265 MV64XXX_I2C_ACTION_SEND_RESTART;
266 drv_data->state =
267 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
268 }
269 } else {
270 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
271 drv_data->state =
272 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
273 drv_data->bytes_left--;
274 }
275 break;
276
277
278 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK:
279 if (drv_data->msg->flags & I2C_M_TEN) {
280 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
281 drv_data->state =
282 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
283 break;
284 }
285 fallthrough;
286 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK:
287 if (drv_data->bytes_left == 0) {
288 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
289 drv_data->state = MV64XXX_I2C_STATE_IDLE;
290 break;
291 }
292 fallthrough;
293 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK:
294 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
295 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
296 else {
297 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
298 drv_data->bytes_left--;
299 }
300 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
301
302 if ((drv_data->bytes_left == 1) || drv_data->aborting)
303 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
304 break;
305
306 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK:
307 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
308 drv_data->state = MV64XXX_I2C_STATE_IDLE;
309 break;
310
311 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK:
312 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK:
313 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK:
314
315 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
316 drv_data->state = MV64XXX_I2C_STATE_IDLE;
317 drv_data->rc = -ENXIO;
318 break;
319
320 default:
321 dev_err(&drv_data->adapter.dev,
322 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
323 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
324 drv_data->state, status, drv_data->msg->addr,
325 drv_data->msg->flags);
326 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
327 mv64xxx_i2c_hw_init(drv_data);
328 drv_data->rc = -EIO;
329 }
330}
331
332static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
333{
334 drv_data->msg = drv_data->msgs;
335 drv_data->byte_posn = 0;
336 drv_data->bytes_left = drv_data->msg->len;
337 drv_data->aborting = 0;
338 drv_data->rc = 0;
339
340 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
341 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
342 drv_data->reg_base + drv_data->reg_offsets.control);
343}
344
345static void
346mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
347{
348 switch(drv_data->action) {
349 case MV64XXX_I2C_ACTION_SEND_RESTART:
350
351 BUG_ON(drv_data->num_msgs == 0);
352
353 drv_data->msgs++;
354 drv_data->num_msgs--;
355 mv64xxx_i2c_send_start(drv_data);
356
357 if (drv_data->errata_delay)
358 udelay(5);
359
360
361
362
363
364
365 drv_data->send_stop = drv_data->num_msgs == 1;
366 break;
367
368 case MV64XXX_I2C_ACTION_CONTINUE:
369 writel(drv_data->cntl_bits,
370 drv_data->reg_base + drv_data->reg_offsets.control);
371 break;
372
373 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
374 writel(drv_data->addr1,
375 drv_data->reg_base + drv_data->reg_offsets.data);
376 writel(drv_data->cntl_bits,
377 drv_data->reg_base + drv_data->reg_offsets.control);
378 break;
379
380 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
381 writel(drv_data->addr2,
382 drv_data->reg_base + drv_data->reg_offsets.data);
383 writel(drv_data->cntl_bits,
384 drv_data->reg_base + drv_data->reg_offsets.control);
385 break;
386
387 case MV64XXX_I2C_ACTION_SEND_DATA:
388 writel(drv_data->msg->buf[drv_data->byte_posn++],
389 drv_data->reg_base + drv_data->reg_offsets.data);
390 writel(drv_data->cntl_bits,
391 drv_data->reg_base + drv_data->reg_offsets.control);
392 break;
393
394 case MV64XXX_I2C_ACTION_RCV_DATA:
395 drv_data->msg->buf[drv_data->byte_posn++] =
396 readl(drv_data->reg_base + drv_data->reg_offsets.data);
397 writel(drv_data->cntl_bits,
398 drv_data->reg_base + drv_data->reg_offsets.control);
399 break;
400
401 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
402 drv_data->msg->buf[drv_data->byte_posn++] =
403 readl(drv_data->reg_base + drv_data->reg_offsets.data);
404 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
405 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
406 drv_data->reg_base + drv_data->reg_offsets.control);
407 drv_data->block = 0;
408 if (drv_data->errata_delay)
409 udelay(5);
410
411 wake_up(&drv_data->waitq);
412 break;
413
414 case MV64XXX_I2C_ACTION_INVALID:
415 default:
416 dev_err(&drv_data->adapter.dev,
417 "mv64xxx_i2c_do_action: Invalid action: %d\n",
418 drv_data->action);
419 drv_data->rc = -EIO;
420 fallthrough;
421 case MV64XXX_I2C_ACTION_SEND_STOP:
422 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
423 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
424 drv_data->reg_base + drv_data->reg_offsets.control);
425 drv_data->block = 0;
426 wake_up(&drv_data->waitq);
427 break;
428 }
429}
430
431static void
432mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
433 struct i2c_msg *msg)
434{
435 u32 buf[2];
436
437 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
438 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
439
440 memcpy(msg->buf, buf, msg->len);
441}
442
443static int
444mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
445{
446 u32 cause, status;
447
448 cause = readl(drv_data->reg_base +
449 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
450 if (!cause)
451 return IRQ_NONE;
452
453 status = readl(drv_data->reg_base +
454 MV64XXX_I2C_REG_BRIDGE_STATUS);
455
456 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
457 drv_data->rc = -EIO;
458 goto out;
459 }
460
461 drv_data->rc = 0;
462
463
464
465
466
467 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
468 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
469 drv_data->msgs++;
470 drv_data->num_msgs--;
471 }
472
473
474
475
476 else if (drv_data->num_msgs == 2 &&
477 !(drv_data->msgs[0].flags & I2C_M_RD) &&
478 drv_data->msgs[1].flags & I2C_M_RD) {
479 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
480 drv_data->msgs += 2;
481 drv_data->num_msgs -= 2;
482 }
483
484out:
485 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
486 writel(0, drv_data->reg_base +
487 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
488 drv_data->block = 0;
489
490 wake_up(&drv_data->waitq);
491
492 return IRQ_HANDLED;
493}
494
495static irqreturn_t
496mv64xxx_i2c_intr(int irq, void *dev_id)
497{
498 struct mv64xxx_i2c_data *drv_data = dev_id;
499 unsigned long flags;
500 u32 status;
501 irqreturn_t rc = IRQ_NONE;
502
503 spin_lock_irqsave(&drv_data->lock, flags);
504
505 if (drv_data->offload_enabled)
506 rc = mv64xxx_i2c_intr_offload(drv_data);
507
508 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
509 MV64XXX_I2C_REG_CONTROL_IFLG) {
510 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
511 mv64xxx_i2c_fsm(drv_data, status);
512 mv64xxx_i2c_do_action(drv_data);
513
514 if (drv_data->irq_clear_inverted)
515 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
516 drv_data->reg_base + drv_data->reg_offsets.control);
517
518 rc = IRQ_HANDLED;
519 }
520 spin_unlock_irqrestore(&drv_data->lock, flags);
521
522 return rc;
523}
524
525
526
527
528
529
530
531
532static void
533mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
534{
535 long time_left;
536 unsigned long flags;
537 char abort = 0;
538
539 time_left = wait_event_timeout(drv_data->waitq,
540 !drv_data->block, drv_data->adapter.timeout);
541
542 spin_lock_irqsave(&drv_data->lock, flags);
543 if (!time_left) {
544 drv_data->rc = -ETIMEDOUT;
545 abort = 1;
546 } else if (time_left < 0) {
547 drv_data->rc = time_left;
548 abort = 1;
549 }
550
551 if (abort && drv_data->block) {
552 drv_data->aborting = 1;
553 spin_unlock_irqrestore(&drv_data->lock, flags);
554
555 time_left = wait_event_timeout(drv_data->waitq,
556 !drv_data->block, drv_data->adapter.timeout);
557
558 if ((time_left <= 0) && drv_data->block) {
559 drv_data->state = MV64XXX_I2C_STATE_IDLE;
560 dev_err(&drv_data->adapter.dev,
561 "mv64xxx: I2C bus locked, block: %d, "
562 "time_left: %d\n", drv_data->block,
563 (int)time_left);
564 mv64xxx_i2c_hw_init(drv_data);
565 }
566 } else
567 spin_unlock_irqrestore(&drv_data->lock, flags);
568}
569
570static int
571mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
572 int is_last)
573{
574 unsigned long flags;
575
576 spin_lock_irqsave(&drv_data->lock, flags);
577
578 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
579
580 drv_data->send_stop = is_last;
581 drv_data->block = 1;
582 mv64xxx_i2c_send_start(drv_data);
583 spin_unlock_irqrestore(&drv_data->lock, flags);
584
585 mv64xxx_i2c_wait_for_completion(drv_data);
586 return drv_data->rc;
587}
588
589static void
590mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
591{
592 struct i2c_msg *msg = drv_data->msgs;
593 u32 buf[2];
594
595 memcpy(buf, msg->buf, msg->len);
596
597 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
598 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
599}
600
601static int
602mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
603{
604 struct i2c_msg *msgs = drv_data->msgs;
605 int num = drv_data->num_msgs;
606 unsigned long ctrl_reg;
607 unsigned long flags;
608
609 spin_lock_irqsave(&drv_data->lock, flags);
610
611
612 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
613 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
614
615 if (msgs[0].flags & I2C_M_TEN)
616 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
617
618
619 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
620 size_t len = msgs[0].len - 1;
621
622 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
623 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
624 mv64xxx_i2c_prepare_tx(drv_data);
625 }
626
627 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
628 size_t len = msgs[0].len - 1;
629
630 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
631 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
632 }
633
634
635
636
637 else if (num == 2) {
638 size_t lentx = msgs[0].len - 1;
639 size_t lenrx = msgs[1].len - 1;
640
641 ctrl_reg |=
642 MV64XXX_I2C_BRIDGE_CONTROL_RD |
643 MV64XXX_I2C_BRIDGE_CONTROL_WR |
644 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
645 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
646 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
647 mv64xxx_i2c_prepare_tx(drv_data);
648 }
649
650
651 drv_data->block = 1;
652 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
653 spin_unlock_irqrestore(&drv_data->lock, flags);
654
655 mv64xxx_i2c_wait_for_completion(drv_data);
656
657 return drv_data->rc;
658}
659
660static bool
661mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
662{
663 return msg->len <= 8 && msg->len >= 1;
664}
665
666static bool
667mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
668{
669 struct i2c_msg *msgs = drv_data->msgs;
670 int num = drv_data->num_msgs;
671
672 if (!drv_data->offload_enabled)
673 return false;
674
675
676
677
678
679
680 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
681 return true;
682
683
684
685
686
687
688 if (num == 2 &&
689 mv64xxx_i2c_valid_offload_sz(msgs) &&
690 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
691 !(msgs[0].flags & I2C_M_RD) &&
692 msgs[1].flags & I2C_M_RD)
693 return true;
694
695 return false;
696}
697
698
699
700
701
702
703
704
705static u32
706mv64xxx_i2c_functionality(struct i2c_adapter *adap)
707{
708 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
709}
710
711static int
712mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
713{
714 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
715 int rc, ret = num;
716
717 BUG_ON(drv_data->msgs != NULL);
718 drv_data->msgs = msgs;
719 drv_data->num_msgs = num;
720
721 if (mv64xxx_i2c_can_offload(drv_data))
722 rc = mv64xxx_i2c_offload_xfer(drv_data);
723 else
724 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
725
726 if (rc < 0)
727 ret = rc;
728
729 drv_data->num_msgs = 0;
730 drv_data->msgs = NULL;
731
732 return ret;
733}
734
735static const struct i2c_algorithm mv64xxx_i2c_algo = {
736 .master_xfer = mv64xxx_i2c_xfer,
737 .functionality = mv64xxx_i2c_functionality,
738};
739
740
741
742
743
744
745
746
747static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
748 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
749 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
750 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
751 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
752 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
753 {}
754};
755MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
756
757#ifdef CONFIG_OF
758static int
759mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
760 const int tclk, const int n, const int m)
761{
762 if (drv_data->clk_n_base_0)
763 return tclk / (10 * (m + 1) * (1 << n));
764 else
765 return tclk / (10 * (m + 1) * (2 << n));
766}
767
768static bool
769mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
770 const u32 req_freq, const u32 tclk)
771{
772 int freq, delta, best_delta = INT_MAX;
773 int m, n;
774
775 for (n = 0; n <= 7; n++)
776 for (m = 0; m <= 15; m++) {
777 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
778 delta = req_freq - freq;
779 if (delta >= 0 && delta < best_delta) {
780 drv_data->freq_m = m;
781 drv_data->freq_n = n;
782 best_delta = delta;
783 }
784 if (best_delta == 0)
785 return true;
786 }
787 if (best_delta == INT_MAX)
788 return false;
789 return true;
790}
791
792static int
793mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
794 struct device *dev)
795{
796 const struct of_device_id *device;
797 struct device_node *np = dev->of_node;
798 u32 bus_freq, tclk;
799 int rc = 0;
800
801
802
803
804
805 if (IS_ERR(drv_data->clk)) {
806 rc = -ENODEV;
807 goto out;
808 }
809 tclk = clk_get_rate(drv_data->clk);
810
811 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
812 bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
813
814 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
815 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
816 drv_data->clk_n_base_0 = true;
817
818 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
819 rc = -EINVAL;
820 goto out;
821 }
822
823 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
824 if (IS_ERR(drv_data->rstc)) {
825 rc = PTR_ERR(drv_data->rstc);
826 goto out;
827 }
828 reset_control_deassert(drv_data->rstc);
829
830
831
832
833 drv_data->adapter.timeout = HZ;
834
835 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
836 if (!device)
837 return -ENODEV;
838
839 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
840
841
842
843
844
845 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
846 drv_data->offload_enabled = true;
847
848 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
849 drv_data->errata_delay = true;
850 }
851
852 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
853 drv_data->offload_enabled = false;
854
855 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
856 drv_data->errata_delay = true;
857 }
858
859 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
860 drv_data->irq_clear_inverted = true;
861
862out:
863 return rc;
864}
865#else
866static int
867mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
868 struct device *dev)
869{
870 return -ENODEV;
871}
872#endif
873
874static int
875mv64xxx_i2c_probe(struct platform_device *pd)
876{
877 struct mv64xxx_i2c_data *drv_data;
878 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
879 int rc;
880
881 if ((!pdata && !pd->dev.of_node))
882 return -ENODEV;
883
884 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
885 GFP_KERNEL);
886 if (!drv_data)
887 return -ENOMEM;
888
889 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
890 if (IS_ERR(drv_data->reg_base))
891 return PTR_ERR(drv_data->reg_base);
892
893 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
894 sizeof(drv_data->adapter.name));
895
896 init_waitqueue_head(&drv_data->waitq);
897 spin_lock_init(&drv_data->lock);
898
899
900 drv_data->clk = devm_clk_get(&pd->dev, NULL);
901 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
902 return -EPROBE_DEFER;
903 if (!IS_ERR(drv_data->clk))
904 clk_prepare_enable(drv_data->clk);
905
906 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
907 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
908 return -EPROBE_DEFER;
909 if (!IS_ERR(drv_data->reg_clk))
910 clk_prepare_enable(drv_data->reg_clk);
911
912 drv_data->irq = platform_get_irq(pd, 0);
913
914 if (pdata) {
915 drv_data->freq_m = pdata->freq_m;
916 drv_data->freq_n = pdata->freq_n;
917 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
918 drv_data->offload_enabled = false;
919 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
920 } else if (pd->dev.of_node) {
921 rc = mv64xxx_of_config(drv_data, &pd->dev);
922 if (rc)
923 goto exit_clk;
924 }
925 if (drv_data->irq < 0) {
926 rc = drv_data->irq;
927 goto exit_reset;
928 }
929
930 drv_data->adapter.dev.parent = &pd->dev;
931 drv_data->adapter.algo = &mv64xxx_i2c_algo;
932 drv_data->adapter.owner = THIS_MODULE;
933 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
934 drv_data->adapter.nr = pd->id;
935 drv_data->adapter.dev.of_node = pd->dev.of_node;
936 platform_set_drvdata(pd, drv_data);
937 i2c_set_adapdata(&drv_data->adapter, drv_data);
938
939 mv64xxx_i2c_hw_init(drv_data);
940
941 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
942 MV64XXX_I2C_CTLR_NAME, drv_data);
943 if (rc) {
944 dev_err(&drv_data->adapter.dev,
945 "mv64xxx: Can't register intr handler irq%d: %d\n",
946 drv_data->irq, rc);
947 goto exit_reset;
948 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
949 dev_err(&drv_data->adapter.dev,
950 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
951 goto exit_free_irq;
952 }
953
954 return 0;
955
956exit_free_irq:
957 free_irq(drv_data->irq, drv_data);
958exit_reset:
959 reset_control_assert(drv_data->rstc);
960exit_clk:
961 clk_disable_unprepare(drv_data->reg_clk);
962 clk_disable_unprepare(drv_data->clk);
963
964 return rc;
965}
966
967static int
968mv64xxx_i2c_remove(struct platform_device *dev)
969{
970 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
971
972 i2c_del_adapter(&drv_data->adapter);
973 free_irq(drv_data->irq, drv_data);
974 reset_control_assert(drv_data->rstc);
975 clk_disable_unprepare(drv_data->reg_clk);
976 clk_disable_unprepare(drv_data->clk);
977
978 return 0;
979}
980
981#ifdef CONFIG_PM
982static int mv64xxx_i2c_resume(struct device *dev)
983{
984 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
985
986 mv64xxx_i2c_hw_init(drv_data);
987
988 return 0;
989}
990
991static const struct dev_pm_ops mv64xxx_i2c_pm = {
992 .resume = mv64xxx_i2c_resume,
993};
994
995#define mv64xxx_i2c_pm_ops (&mv64xxx_i2c_pm)
996#else
997#define mv64xxx_i2c_pm_ops NULL
998#endif
999
1000static struct platform_driver mv64xxx_i2c_driver = {
1001 .probe = mv64xxx_i2c_probe,
1002 .remove = mv64xxx_i2c_remove,
1003 .driver = {
1004 .name = MV64XXX_I2C_CTLR_NAME,
1005 .pm = mv64xxx_i2c_pm_ops,
1006 .of_match_table = mv64xxx_i2c_of_match_table,
1007 },
1008};
1009
1010module_platform_driver(mv64xxx_i2c_driver);
1011
1012MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1013MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1014MODULE_LICENSE("GPL");
1015
