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14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/dmaengine.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/i2c.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/reset.h>
29#include <linux/slab.h>
30
31
32#define ICSCR 0x00
33#define ICMCR 0x04
34#define ICSSR 0x08
35#define ICMSR 0x0C
36#define ICSIER 0x10
37#define ICMIER 0x14
38#define ICCCR 0x18
39#define ICSAR 0x1C
40#define ICMAR 0x20
41#define ICRXTX 0x24
42#define ICFBSCR 0x38
43#define ICDMAER 0x3c
44
45
46#define SDBS (1 << 3)
47#define SIE (1 << 2)
48#define GCAE (1 << 1)
49#define FNA (1 << 0)
50
51
52#define MDBS (1 << 7)
53#define FSCL (1 << 6)
54#define FSDA (1 << 5)
55#define OBPC (1 << 4)
56#define MIE (1 << 3)
57#define TSBE (1 << 2)
58#define FSB (1 << 1)
59#define ESG (1 << 0)
60
61
62#define GCAR (1 << 6)
63#define STM (1 << 5)
64#define SSR (1 << 4)
65#define SDE (1 << 3)
66#define SDT (1 << 2)
67#define SDR (1 << 1)
68#define SAR (1 << 0)
69
70
71#define MNR (1 << 6)
72#define MAL (1 << 5)
73#define MST (1 << 4)
74#define MDE (1 << 3)
75#define MDT (1 << 2)
76#define MDR (1 << 1)
77#define MAT (1 << 0)
78
79
80#define RSDMAE (1 << 3)
81#define TSDMAE (1 << 2)
82#define RMDMAE (1 << 1)
83#define TMDMAE (1 << 0)
84
85
86#define TCYC17 0x0f
87
88#define RCAR_MIN_DMA_LEN 8
89
90#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
91#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
92#define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
93#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
94
95#define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
96#define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
97#define RCAR_IRQ_STOP (MST)
98
99#define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0x7F)
100#define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0x7F)
101
102#define ID_LAST_MSG (1 << 0)
103#define ID_FIRST_MSG (1 << 1)
104#define ID_DONE (1 << 2)
105#define ID_ARBLOST (1 << 3)
106#define ID_NACK (1 << 4)
107
108#define ID_P_REP_AFTER_RD BIT(29)
109#define ID_P_NO_RXDMA BIT(30)
110#define ID_P_PM_BLOCKED BIT(31)
111#define ID_P_MASK GENMASK(31, 29)
112
113enum rcar_i2c_type {
114 I2C_RCAR_GEN1,
115 I2C_RCAR_GEN2,
116 I2C_RCAR_GEN3,
117};
118
119struct rcar_i2c_priv {
120 void __iomem *io;
121 struct i2c_adapter adap;
122 struct i2c_msg *msg;
123 int msgs_left;
124 struct clk *clk;
125
126 wait_queue_head_t wait;
127
128 int pos;
129 u32 icccr;
130 u32 flags;
131 u8 recovery_icmcr;
132 enum rcar_i2c_type devtype;
133 struct i2c_client *slave;
134
135 struct resource *res;
136 struct dma_chan *dma_tx;
137 struct dma_chan *dma_rx;
138 struct scatterlist sg;
139 enum dma_data_direction dma_direction;
140
141 struct reset_control *rstc;
142 int irq;
143};
144
145#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
146#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
147
148#define LOOP_TIMEOUT 1024
149
150
151static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
152{
153 writel(val, priv->io + reg);
154}
155
156static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
157{
158 return readl(priv->io + reg);
159}
160
161static int rcar_i2c_get_scl(struct i2c_adapter *adap)
162{
163 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
164
165 return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
166
167};
168
169static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
170{
171 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
172
173 if (val)
174 priv->recovery_icmcr |= FSCL;
175 else
176 priv->recovery_icmcr &= ~FSCL;
177
178 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
179};
180
181static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
182{
183 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
184
185 if (val)
186 priv->recovery_icmcr |= FSDA;
187 else
188 priv->recovery_icmcr &= ~FSDA;
189
190 rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
191};
192
193static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
194{
195 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
196
197 return !(rcar_i2c_read(priv, ICMCR) & FSDA);
198
199};
200
201static struct i2c_bus_recovery_info rcar_i2c_bri = {
202 .get_scl = rcar_i2c_get_scl,
203 .set_scl = rcar_i2c_set_scl,
204 .set_sda = rcar_i2c_set_sda,
205 .get_bus_free = rcar_i2c_get_bus_free,
206 .recover_bus = i2c_generic_scl_recovery,
207};
208static void rcar_i2c_init(struct rcar_i2c_priv *priv)
209{
210
211 rcar_i2c_write(priv, ICMIER, 0);
212 rcar_i2c_write(priv, ICMCR, MDBS);
213 rcar_i2c_write(priv, ICMSR, 0);
214
215 rcar_i2c_write(priv, ICCCR, priv->icccr);
216
217 if (priv->devtype == I2C_RCAR_GEN3)
218 rcar_i2c_write(priv, ICFBSCR, TCYC17);
219
220}
221
222static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
223{
224 int i;
225
226 for (i = 0; i < LOOP_TIMEOUT; i++) {
227
228 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
229 return 0;
230 udelay(1);
231 }
232
233
234 priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
235 return i2c_recover_bus(&priv->adap);
236}
237
238static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
239{
240 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
241 unsigned long rate;
242 struct device *dev = rcar_i2c_priv_to_dev(priv);
243 struct i2c_timings t = {
244 .bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ,
245 .scl_fall_ns = 35,
246 .scl_rise_ns = 200,
247 .scl_int_delay_ns = 50,
248 };
249
250
251 i2c_parse_fw_timings(dev, &t, false);
252
253 switch (priv->devtype) {
254 case I2C_RCAR_GEN1:
255 cdf_width = 2;
256 break;
257 case I2C_RCAR_GEN2:
258 case I2C_RCAR_GEN3:
259 cdf_width = 3;
260 break;
261 default:
262 dev_err(dev, "device type error\n");
263 return -EIO;
264 }
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281 rate = clk_get_rate(priv->clk);
282 cdf = rate / 20000000;
283 if (cdf >= 1U << cdf_width) {
284 dev_err(dev, "Input clock %lu too high\n", rate);
285 return -EIO;
286 }
287 ick = rate / (cdf + 1);
288
289
290
291
292
293
294
295
296
297 sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
298 round = (ick + 500000) / 1000000 * sum;
299 round = (round + 500) / 1000;
300
301
302
303
304
305
306
307
308
309
310
311
312
313 for (scgd = 0; scgd < 0x40; scgd++) {
314 scl = ick / (20 + (scgd * 8) + round);
315 if (scl <= t.bus_freq_hz)
316 goto scgd_find;
317 }
318 dev_err(dev, "it is impossible to calculate best SCL\n");
319 return -EIO;
320
321scgd_find:
322 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
323 scl, t.bus_freq_hz, rate, round, cdf, scgd);
324
325
326 priv->icccr = scgd << cdf_width | cdf;
327
328 return 0;
329}
330
331static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
332{
333 int read = !!rcar_i2c_is_recv(priv);
334
335 priv->pos = 0;
336 if (priv->msgs_left == 1)
337 priv->flags |= ID_LAST_MSG;
338
339 rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
340
341
342
343
344
345 if (priv->flags & ID_FIRST_MSG) {
346 rcar_i2c_write(priv, ICMSR, 0);
347 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
348 } else {
349 if (priv->flags & ID_P_REP_AFTER_RD)
350 priv->flags &= ~ID_P_REP_AFTER_RD;
351 else
352 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
353 rcar_i2c_write(priv, ICMSR, 0);
354 }
355 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
356}
357
358static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
359{
360 priv->msg++;
361 priv->msgs_left--;
362 priv->flags &= ID_P_MASK;
363 rcar_i2c_prepare_msg(priv);
364}
365
366static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
367{
368 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
369 ? priv->dma_rx : priv->dma_tx;
370
371 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
372 sg_dma_len(&priv->sg), priv->dma_direction);
373
374
375 if (priv->devtype == I2C_RCAR_GEN3 &&
376 priv->dma_direction == DMA_FROM_DEVICE)
377 priv->flags |= ID_P_NO_RXDMA;
378
379 priv->dma_direction = DMA_NONE;
380
381
382 rcar_i2c_write(priv, ICDMAER, 0);
383}
384
385static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
386{
387 if (priv->dma_direction == DMA_NONE)
388 return;
389 else if (priv->dma_direction == DMA_FROM_DEVICE)
390 dmaengine_terminate_all(priv->dma_rx);
391 else if (priv->dma_direction == DMA_TO_DEVICE)
392 dmaengine_terminate_all(priv->dma_tx);
393
394 rcar_i2c_dma_unmap(priv);
395}
396
397static void rcar_i2c_dma_callback(void *data)
398{
399 struct rcar_i2c_priv *priv = data;
400
401 priv->pos += sg_dma_len(&priv->sg);
402
403 rcar_i2c_dma_unmap(priv);
404}
405
406static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
407{
408 struct device *dev = rcar_i2c_priv_to_dev(priv);
409 struct i2c_msg *msg = priv->msg;
410 bool read = msg->flags & I2C_M_RD;
411 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
412 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
413 struct dma_async_tx_descriptor *txdesc;
414 dma_addr_t dma_addr;
415 dma_cookie_t cookie;
416 unsigned char *buf;
417 int len;
418
419
420 if (IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
421 !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
422 return false;
423
424 if (read) {
425
426
427
428
429 buf = priv->msg->buf;
430 len = priv->msg->len - 2;
431 } else {
432
433
434
435 buf = priv->msg->buf + 1;
436 len = priv->msg->len - 1;
437 }
438
439 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
440 if (dma_mapping_error(chan->device->dev, dma_addr)) {
441 dev_dbg(dev, "dma map failed, using PIO\n");
442 return false;
443 }
444
445 sg_dma_len(&priv->sg) = len;
446 sg_dma_address(&priv->sg) = dma_addr;
447
448 priv->dma_direction = dir;
449
450 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
451 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
453 if (!txdesc) {
454 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
455 rcar_i2c_cleanup_dma(priv);
456 return false;
457 }
458
459 txdesc->callback = rcar_i2c_dma_callback;
460 txdesc->callback_param = priv;
461
462 cookie = dmaengine_submit(txdesc);
463 if (dma_submit_error(cookie)) {
464 dev_dbg(dev, "submitting dma failed, using PIO\n");
465 rcar_i2c_cleanup_dma(priv);
466 return false;
467 }
468
469
470 if (read)
471 rcar_i2c_write(priv, ICDMAER, RMDMAE);
472 else
473 rcar_i2c_write(priv, ICDMAER, TMDMAE);
474
475 dma_async_issue_pending(chan);
476 return true;
477}
478
479static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
480{
481 struct i2c_msg *msg = priv->msg;
482
483
484 if (!(msr & MDE))
485 return;
486
487
488 if (priv->pos == 1 && rcar_i2c_dma(priv))
489 return;
490
491 if (priv->pos < msg->len) {
492
493
494
495
496
497
498
499 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
500 priv->pos++;
501 } else {
502
503
504
505
506
507
508
509
510 if (priv->flags & ID_LAST_MSG) {
511
512
513
514
515
516 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
517 } else {
518 rcar_i2c_next_msg(priv);
519 return;
520 }
521 }
522
523 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
524}
525
526static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
527{
528 struct i2c_msg *msg = priv->msg;
529
530
531 if (!(msr & MDR))
532 return;
533
534 if (msr & MAT) {
535
536
537
538
539 rcar_i2c_dma(priv);
540 } else if (priv->pos < msg->len) {
541
542 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
543 priv->pos++;
544 }
545
546
547 if (priv->pos + 1 == msg->len) {
548 if (priv->flags & ID_LAST_MSG) {
549 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
550 } else {
551 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
552 priv->flags |= ID_P_REP_AFTER_RD;
553 }
554 }
555
556 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
557 rcar_i2c_next_msg(priv);
558 else
559 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
560}
561
562static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
563{
564 u32 ssr_raw, ssr_filtered;
565 u8 value;
566
567 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
568 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
569
570 if (!ssr_filtered)
571 return false;
572
573
574 if (ssr_filtered & SAR) {
575
576 if (ssr_raw & STM) {
577 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
578 rcar_i2c_write(priv, ICRXTX, value);
579 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
580 } else {
581 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
582 rcar_i2c_read(priv, ICRXTX);
583 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
584 }
585
586
587 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
588 }
589
590
591 if (ssr_filtered & SSR) {
592 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
593 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
594 rcar_i2c_write(priv, ICSIER, SAR);
595 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
596 }
597
598
599 if (ssr_filtered & SDR) {
600 int ret;
601
602 value = rcar_i2c_read(priv, ICRXTX);
603 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
604
605 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
606 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
607 }
608
609
610 if (ssr_filtered & SDE) {
611 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
612 rcar_i2c_write(priv, ICRXTX, value);
613 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
614 }
615
616 return true;
617}
618
619
620
621
622
623
624
625
626
627
628static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
629{
630 struct rcar_i2c_priv *priv = ptr;
631 u32 msr, val;
632
633
634 if (likely(!(priv->flags & ID_P_REP_AFTER_RD))) {
635 val = rcar_i2c_read(priv, ICMCR);
636 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
637 }
638
639 msr = rcar_i2c_read(priv, ICMSR);
640
641
642 msr &= rcar_i2c_read(priv, ICMIER);
643 if (!msr) {
644 if (rcar_i2c_slave_irq(priv))
645 return IRQ_HANDLED;
646
647 return IRQ_NONE;
648 }
649
650
651 if (msr & MAL) {
652 priv->flags |= ID_DONE | ID_ARBLOST;
653 goto out;
654 }
655
656
657 if (msr & MNR) {
658
659 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
660 priv->flags |= ID_NACK;
661 goto out;
662 }
663
664
665 if (msr & MST) {
666 priv->msgs_left--;
667 priv->flags |= ID_DONE;
668 goto out;
669 }
670
671 if (rcar_i2c_is_recv(priv))
672 rcar_i2c_irq_recv(priv, msr);
673 else
674 rcar_i2c_irq_send(priv, msr);
675
676out:
677 if (priv->flags & ID_DONE) {
678 rcar_i2c_write(priv, ICMIER, 0);
679 rcar_i2c_write(priv, ICMSR, 0);
680 wake_up(&priv->wait);
681 }
682
683 return IRQ_HANDLED;
684}
685
686static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
687 enum dma_transfer_direction dir,
688 dma_addr_t port_addr)
689{
690 struct dma_chan *chan;
691 struct dma_slave_config cfg;
692 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
693 int ret;
694
695 chan = dma_request_chan(dev, chan_name);
696 if (IS_ERR(chan)) {
697 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
698 chan_name, PTR_ERR(chan));
699 return chan;
700 }
701
702 memset(&cfg, 0, sizeof(cfg));
703 cfg.direction = dir;
704 if (dir == DMA_MEM_TO_DEV) {
705 cfg.dst_addr = port_addr;
706 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
707 } else {
708 cfg.src_addr = port_addr;
709 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
710 }
711
712 ret = dmaengine_slave_config(chan, &cfg);
713 if (ret) {
714 dev_dbg(dev, "slave_config failed for %s (%d)\n",
715 chan_name, ret);
716 dma_release_channel(chan);
717 return ERR_PTR(ret);
718 }
719
720 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
721 return chan;
722}
723
724static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
725 struct i2c_msg *msg)
726{
727 struct device *dev = rcar_i2c_priv_to_dev(priv);
728 bool read;
729 struct dma_chan *chan;
730 enum dma_transfer_direction dir;
731
732 read = msg->flags & I2C_M_RD;
733
734 chan = read ? priv->dma_rx : priv->dma_tx;
735 if (PTR_ERR(chan) != -EPROBE_DEFER)
736 return;
737
738 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
739 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
740
741 if (read)
742 priv->dma_rx = chan;
743 else
744 priv->dma_tx = chan;
745}
746
747static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
748{
749 if (!IS_ERR(priv->dma_tx)) {
750 dma_release_channel(priv->dma_tx);
751 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
752 }
753
754 if (!IS_ERR(priv->dma_rx)) {
755 dma_release_channel(priv->dma_rx);
756 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
757 }
758}
759
760
761static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
762{
763 int i, ret;
764
765 ret = reset_control_reset(priv->rstc);
766 if (ret)
767 return ret;
768
769 for (i = 0; i < LOOP_TIMEOUT; i++) {
770 ret = reset_control_status(priv->rstc);
771 if (ret == 0)
772 return 0;
773 udelay(1);
774 }
775
776 return -ETIMEDOUT;
777}
778
779static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
780 struct i2c_msg *msgs,
781 int num)
782{
783 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
784 struct device *dev = rcar_i2c_priv_to_dev(priv);
785 int i, ret;
786 long time_left;
787
788 pm_runtime_get_sync(dev);
789
790
791 ret = rcar_i2c_bus_barrier(priv);
792 if (ret < 0)
793 goto out;
794
795
796 if (priv->devtype == I2C_RCAR_GEN3) {
797 priv->flags |= ID_P_NO_RXDMA;
798 if (!IS_ERR(priv->rstc)) {
799 ret = rcar_i2c_do_reset(priv);
800 if (ret == 0)
801 priv->flags &= ~ID_P_NO_RXDMA;
802 }
803 }
804
805 rcar_i2c_init(priv);
806
807 for (i = 0; i < num; i++)
808 rcar_i2c_request_dma(priv, msgs + i);
809
810
811 priv->msg = msgs;
812 priv->msgs_left = num;
813 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
814 rcar_i2c_prepare_msg(priv);
815
816 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
817 num * adap->timeout);
818
819
820 if (priv->dma_direction != DMA_NONE)
821 rcar_i2c_cleanup_dma(priv);
822
823 if (!time_left) {
824 rcar_i2c_init(priv);
825 ret = -ETIMEDOUT;
826 } else if (priv->flags & ID_NACK) {
827 ret = -ENXIO;
828 } else if (priv->flags & ID_ARBLOST) {
829 ret = -EAGAIN;
830 } else {
831 ret = num - priv->msgs_left;
832 }
833out:
834 pm_runtime_put(dev);
835
836 if (ret < 0 && ret != -ENXIO)
837 dev_err(dev, "error %d : %x\n", ret, priv->flags);
838
839 return ret;
840}
841
842static int rcar_reg_slave(struct i2c_client *slave)
843{
844 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
845
846 if (priv->slave)
847 return -EBUSY;
848
849 if (slave->flags & I2C_CLIENT_TEN)
850 return -EAFNOSUPPORT;
851
852
853 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
854
855 priv->slave = slave;
856 rcar_i2c_write(priv, ICSAR, slave->addr);
857 rcar_i2c_write(priv, ICSSR, 0);
858 rcar_i2c_write(priv, ICSIER, SAR);
859 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
860
861 return 0;
862}
863
864static int rcar_unreg_slave(struct i2c_client *slave)
865{
866 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
867
868 WARN_ON(!priv->slave);
869
870
871 disable_irq(priv->irq);
872 rcar_i2c_write(priv, ICSIER, 0);
873 rcar_i2c_write(priv, ICSSR, 0);
874 enable_irq(priv->irq);
875 rcar_i2c_write(priv, ICSCR, SDBS);
876 rcar_i2c_write(priv, ICSAR, 0);
877
878 priv->slave = NULL;
879
880 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
881
882 return 0;
883}
884
885static u32 rcar_i2c_func(struct i2c_adapter *adap)
886{
887
888
889
890
891
892
893 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
894 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
895}
896
897static const struct i2c_algorithm rcar_i2c_algo = {
898 .master_xfer = rcar_i2c_master_xfer,
899 .functionality = rcar_i2c_func,
900 .reg_slave = rcar_reg_slave,
901 .unreg_slave = rcar_unreg_slave,
902};
903
904static const struct i2c_adapter_quirks rcar_i2c_quirks = {
905 .flags = I2C_AQ_NO_ZERO_LEN,
906};
907
908static const struct of_device_id rcar_i2c_dt_ids[] = {
909 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
910 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
911 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
912 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
913 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
914 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
915 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
916 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
917 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
918 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
919 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
920 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
921 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
922 {},
923};
924MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
925
926static int rcar_i2c_probe(struct platform_device *pdev)
927{
928 struct rcar_i2c_priv *priv;
929 struct i2c_adapter *adap;
930 struct device *dev = &pdev->dev;
931 int ret;
932
933
934 BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
935
936 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
937 if (!priv)
938 return -ENOMEM;
939
940 priv->clk = devm_clk_get(dev, NULL);
941 if (IS_ERR(priv->clk)) {
942 dev_err(dev, "cannot get clock\n");
943 return PTR_ERR(priv->clk);
944 }
945
946 priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
947 if (IS_ERR(priv->io))
948 return PTR_ERR(priv->io);
949
950 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
951 init_waitqueue_head(&priv->wait);
952
953 adap = &priv->adap;
954 adap->nr = pdev->id;
955 adap->algo = &rcar_i2c_algo;
956 adap->class = I2C_CLASS_DEPRECATED;
957 adap->retries = 3;
958 adap->dev.parent = dev;
959 adap->dev.of_node = dev->of_node;
960 adap->bus_recovery_info = &rcar_i2c_bri;
961 adap->quirks = &rcar_i2c_quirks;
962 i2c_set_adapdata(adap, priv);
963 strlcpy(adap->name, pdev->name, sizeof(adap->name));
964
965
966 sg_init_table(&priv->sg, 1);
967 priv->dma_direction = DMA_NONE;
968 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
969
970
971 pm_runtime_enable(dev);
972 pm_runtime_get_sync(dev);
973 ret = rcar_i2c_clock_calculate(priv);
974 if (ret < 0)
975 goto out_pm_put;
976
977 rcar_i2c_write(priv, ICSAR, 0);
978
979 if (priv->devtype == I2C_RCAR_GEN3) {
980 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
981 if (!IS_ERR(priv->rstc)) {
982 ret = reset_control_status(priv->rstc);
983 if (ret < 0)
984 priv->rstc = ERR_PTR(-ENOTSUPP);
985 }
986 }
987
988
989 if (of_property_read_bool(dev->of_node, "multi-master"))
990 priv->flags |= ID_P_PM_BLOCKED;
991 else
992 pm_runtime_put(dev);
993
994
995 priv->irq = platform_get_irq(pdev, 0);
996 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
997 if (ret < 0) {
998 dev_err(dev, "cannot get irq %d\n", priv->irq);
999 goto out_pm_disable;
1000 }
1001
1002 platform_set_drvdata(pdev, priv);
1003
1004 ret = i2c_add_numbered_adapter(adap);
1005 if (ret < 0)
1006 goto out_pm_disable;
1007
1008 dev_info(dev, "probed\n");
1009
1010 return 0;
1011
1012 out_pm_put:
1013 pm_runtime_put(dev);
1014 out_pm_disable:
1015 pm_runtime_disable(dev);
1016 return ret;
1017}
1018
1019static int rcar_i2c_remove(struct platform_device *pdev)
1020{
1021 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1022 struct device *dev = &pdev->dev;
1023
1024 i2c_del_adapter(&priv->adap);
1025 rcar_i2c_release_dma(priv);
1026 if (priv->flags & ID_P_PM_BLOCKED)
1027 pm_runtime_put(dev);
1028 pm_runtime_disable(dev);
1029
1030 return 0;
1031}
1032
1033#ifdef CONFIG_PM_SLEEP
1034static int rcar_i2c_suspend(struct device *dev)
1035{
1036 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1037
1038 i2c_mark_adapter_suspended(&priv->adap);
1039 return 0;
1040}
1041
1042static int rcar_i2c_resume(struct device *dev)
1043{
1044 struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1045
1046 i2c_mark_adapter_resumed(&priv->adap);
1047 return 0;
1048}
1049
1050static const struct dev_pm_ops rcar_i2c_pm_ops = {
1051 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1052};
1053
1054#define DEV_PM_OPS (&rcar_i2c_pm_ops)
1055#else
1056#define DEV_PM_OPS NULL
1057#endif
1058
1059static struct platform_driver rcar_i2c_driver = {
1060 .driver = {
1061 .name = "i2c-rcar",
1062 .of_match_table = rcar_i2c_dt_ids,
1063 .pm = DEV_PM_OPS,
1064 },
1065 .probe = rcar_i2c_probe,
1066 .remove = rcar_i2c_remove,
1067};
1068
1069module_platform_driver(rcar_i2c_driver);
1070
1071MODULE_LICENSE("GPL v2");
1072MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1073MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
1074