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9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/err.h>
15#include <linux/i2c.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/irq.h>
21#include <linux/kernel.h>
22#include <linux/ktime.h>
23#include <linux/module.h>
24#include <linux/of_device.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/reset.h>
29
30#define BYTES_PER_FIFO_WORD 4
31
32#define I2C_CNFG 0x000
33#define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
34#define I2C_CNFG_PACKET_MODE_EN BIT(10)
35#define I2C_CNFG_NEW_MASTER_FSM BIT(11)
36#define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
37#define I2C_STATUS 0x01c
38#define I2C_SL_CNFG 0x020
39#define I2C_SL_CNFG_NACK BIT(1)
40#define I2C_SL_CNFG_NEWSL BIT(2)
41#define I2C_SL_ADDR1 0x02c
42#define I2C_SL_ADDR2 0x030
43#define I2C_TLOW_SEXT 0x034
44#define I2C_TX_FIFO 0x050
45#define I2C_RX_FIFO 0x054
46#define I2C_PACKET_TRANSFER_STATUS 0x058
47#define I2C_FIFO_CONTROL 0x05c
48#define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
49#define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
50#define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
51#define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
52#define I2C_FIFO_STATUS 0x060
53#define I2C_FIFO_STATUS_TX GENMASK(7, 4)
54#define I2C_FIFO_STATUS_RX GENMASK(3, 0)
55#define I2C_INT_MASK 0x064
56#define I2C_INT_STATUS 0x068
57#define I2C_INT_BUS_CLR_DONE BIT(11)
58#define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
59#define I2C_INT_NO_ACK BIT(3)
60#define I2C_INT_ARBITRATION_LOST BIT(2)
61#define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
62#define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
63#define I2C_CLK_DIVISOR 0x06c
64#define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
65#define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
66
67#define DVC_CTRL_REG1 0x000
68#define DVC_CTRL_REG1_INTR_EN BIT(10)
69#define DVC_CTRL_REG3 0x008
70#define DVC_CTRL_REG3_SW_PROG BIT(26)
71#define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
72#define DVC_STATUS 0x00c
73#define DVC_STATUS_I2C_DONE_INTR BIT(30)
74
75#define I2C_ERR_NONE 0x00
76#define I2C_ERR_NO_ACK BIT(0)
77#define I2C_ERR_ARBITRATION_LOST BIT(1)
78#define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
79#define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
80
81#define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
82#define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
83#define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
84#define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
85#define PACKET_HEADER0_PROTOCOL_I2C 1
86
87#define I2C_HEADER_CONT_ON_NAK BIT(21)
88#define I2C_HEADER_READ BIT(19)
89#define I2C_HEADER_10BIT_ADDR BIT(18)
90#define I2C_HEADER_IE_ENABLE BIT(17)
91#define I2C_HEADER_REPEAT_START BIT(16)
92#define I2C_HEADER_CONTINUE_XFER BIT(15)
93#define I2C_HEADER_SLAVE_ADDR_SHIFT 1
94
95#define I2C_BUS_CLEAR_CNFG 0x084
96#define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
97#define I2C_BC_STOP_COND BIT(2)
98#define I2C_BC_TERMINATE BIT(1)
99#define I2C_BC_ENABLE BIT(0)
100#define I2C_BUS_CLEAR_STATUS 0x088
101#define I2C_BC_STATUS BIT(0)
102
103#define I2C_CONFIG_LOAD 0x08c
104#define I2C_MSTR_CONFIG_LOAD BIT(0)
105
106#define I2C_CLKEN_OVERRIDE 0x090
107#define I2C_MST_CORE_CLKEN_OVR BIT(0)
108
109#define I2C_INTERFACE_TIMING_0 0x094
110#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
111#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
112#define I2C_INTERFACE_TIMING_1 0x098
113#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
114#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
115#define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
116#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
117
118#define I2C_HS_INTERFACE_TIMING_0 0x09c
119#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
120#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
121#define I2C_HS_INTERFACE_TIMING_1 0x0a0
122#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
123#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
124#define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
125
126#define I2C_MST_FIFO_CONTROL 0x0b4
127#define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
128#define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
129#define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
130#define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
131
132#define I2C_MST_FIFO_STATUS 0x0b8
133#define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
134#define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
135
136
137#define I2C_CONFIG_LOAD_TIMEOUT 1000000
138
139
140#define I2C_PACKET_HEADER_SIZE 12
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147
148#define I2C_PIO_MODE_PREFERRED_LEN 32
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156
157enum msg_end_type {
158 MSG_END_STOP,
159 MSG_END_REPEAT_START,
160 MSG_END_CONTINUE,
161};
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208struct tegra_i2c_hw_feature {
209 bool has_continue_xfer_support;
210 bool has_per_pkt_xfer_complete_irq;
211 bool has_single_clk_source;
212 bool has_config_load_reg;
213 int clk_divisor_hs_mode;
214 int clk_divisor_std_mode;
215 int clk_divisor_fast_mode;
216 u16 clk_divisor_fast_plus_mode;
217 bool has_multi_master_mode;
218 bool has_slcg_override_reg;
219 bool has_mst_fifo;
220 const struct i2c_adapter_quirks *quirks;
221 bool supports_bus_clear;
222 bool has_apb_dma;
223 u8 tlow_std_mode;
224 u8 thigh_std_mode;
225 u8 tlow_fast_fastplus_mode;
226 u8 thigh_fast_fastplus_mode;
227 u32 setup_hold_time_std_mode;
228 u32 setup_hold_time_fast_fast_plus_mode;
229 u32 setup_hold_time_hs_mode;
230 bool has_interface_timing_reg;
231};
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264struct tegra_i2c_dev {
265 struct device *dev;
266 const struct tegra_i2c_hw_feature *hw;
267 struct i2c_adapter adapter;
268 struct clk *div_clk;
269 struct clk *fast_clk;
270 struct clk *slow_clk;
271 struct reset_control *rst;
272 void __iomem *base;
273 phys_addr_t base_phys;
274 int cont_id;
275 int irq;
276 int is_dvc;
277 bool is_vi;
278 struct completion msg_complete;
279 int msg_err;
280 u8 *msg_buf;
281 size_t msg_buf_remaining;
282 int msg_read;
283 u32 bus_clk_rate;
284 u16 clk_divisor_non_hs_mode;
285 bool is_multimaster_mode;
286 struct dma_chan *tx_dma_chan;
287 struct dma_chan *rx_dma_chan;
288 dma_addr_t dma_phys;
289 u32 *dma_buf;
290 unsigned int dma_buf_size;
291 bool is_curr_dma_xfer;
292 struct completion dma_complete;
293 bool is_curr_atomic_xfer;
294};
295
296static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit);
297
298static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
299 unsigned long reg)
300{
301 writel_relaxed(val, i2c_dev->base + reg);
302}
303
304static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
305{
306 return readl_relaxed(i2c_dev->base + reg);
307}
308
309
310
311
312
313static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
314 unsigned long reg)
315{
316 if (i2c_dev->is_dvc)
317 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
318 else if (i2c_dev->is_vi)
319 reg = 0xc00 + (reg << 2);
320 return reg;
321}
322
323static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
324 unsigned long reg)
325{
326 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
327
328
329 if (reg != I2C_TX_FIFO)
330 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
331}
332
333static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
334{
335 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
336}
337
338static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
339 unsigned long reg, int len)
340{
341 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
342}
343
344static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
345 unsigned long reg, int len)
346{
347 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
348}
349
350static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
351{
352 u32 int_mask;
353
354 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
355 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
356}
357
358static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
359{
360 u32 int_mask;
361
362 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
363 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
364}
365
366static void tegra_i2c_dma_complete(void *args)
367{
368 struct tegra_i2c_dev *i2c_dev = args;
369
370 complete(&i2c_dev->dma_complete);
371}
372
373static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
374{
375 struct dma_async_tx_descriptor *dma_desc;
376 enum dma_transfer_direction dir;
377 struct dma_chan *chan;
378
379 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
380 reinit_completion(&i2c_dev->dma_complete);
381 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
382 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
383 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
384 len, dir, DMA_PREP_INTERRUPT |
385 DMA_CTRL_ACK);
386 if (!dma_desc) {
387 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n");
388 return -EINVAL;
389 }
390
391 dma_desc->callback = tegra_i2c_dma_complete;
392 dma_desc->callback_param = i2c_dev;
393 dmaengine_submit(dma_desc);
394 dma_async_issue_pending(chan);
395 return 0;
396}
397
398static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
399{
400 if (i2c_dev->dma_buf) {
401 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
402 i2c_dev->dma_buf, i2c_dev->dma_phys);
403 i2c_dev->dma_buf = NULL;
404 }
405
406 if (i2c_dev->tx_dma_chan) {
407 dma_release_channel(i2c_dev->tx_dma_chan);
408 i2c_dev->tx_dma_chan = NULL;
409 }
410
411 if (i2c_dev->rx_dma_chan) {
412 dma_release_channel(i2c_dev->rx_dma_chan);
413 i2c_dev->rx_dma_chan = NULL;
414 }
415}
416
417static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
418{
419 struct dma_chan *chan;
420 u32 *dma_buf;
421 dma_addr_t dma_phys;
422 int err;
423
424 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
425 return 0;
426
427 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
428 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n");
429 return 0;
430 }
431
432 chan = dma_request_chan(i2c_dev->dev, "rx");
433 if (IS_ERR(chan)) {
434 err = PTR_ERR(chan);
435 goto err_out;
436 }
437
438 i2c_dev->rx_dma_chan = chan;
439
440 chan = dma_request_chan(i2c_dev->dev, "tx");
441 if (IS_ERR(chan)) {
442 err = PTR_ERR(chan);
443 goto err_out;
444 }
445
446 i2c_dev->tx_dma_chan = chan;
447
448 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
449 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
450 if (!dma_buf) {
451 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n");
452 err = -ENOMEM;
453 goto err_out;
454 }
455
456 i2c_dev->dma_buf = dma_buf;
457 i2c_dev->dma_phys = dma_phys;
458 return 0;
459
460err_out:
461 tegra_i2c_release_dma(i2c_dev);
462 if (err != -EPROBE_DEFER) {
463 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
464 dev_err(i2c_dev->dev, "falling back to PIO\n");
465 return 0;
466 }
467
468 return err;
469}
470
471static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
472{
473 unsigned long timeout = jiffies + HZ;
474 unsigned int offset;
475 u32 mask, val;
476
477 if (i2c_dev->hw->has_mst_fifo) {
478 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
479 I2C_MST_FIFO_CONTROL_RX_FLUSH;
480 offset = I2C_MST_FIFO_CONTROL;
481 } else {
482 mask = I2C_FIFO_CONTROL_TX_FLUSH |
483 I2C_FIFO_CONTROL_RX_FLUSH;
484 offset = I2C_FIFO_CONTROL;
485 }
486
487 val = i2c_readl(i2c_dev, offset);
488 val |= mask;
489 i2c_writel(i2c_dev, val, offset);
490
491 while (i2c_readl(i2c_dev, offset) & mask) {
492 if (time_after(jiffies, timeout)) {
493 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
494 return -ETIMEDOUT;
495 }
496 usleep_range(1000, 2000);
497 }
498 return 0;
499}
500
501static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
502{
503 u32 val;
504 int rx_fifo_avail;
505 u8 *buf = i2c_dev->msg_buf;
506 size_t buf_remaining = i2c_dev->msg_buf_remaining;
507 int words_to_transfer;
508
509
510
511
512
513 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
514 return -EINVAL;
515
516 if (i2c_dev->hw->has_mst_fifo) {
517 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
518 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
519 } else {
520 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
521 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
522 }
523
524
525 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
526 if (words_to_transfer > rx_fifo_avail)
527 words_to_transfer = rx_fifo_avail;
528
529 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
530
531 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
532 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
533 rx_fifo_avail -= words_to_transfer;
534
535
536
537
538
539 if (rx_fifo_avail > 0 && buf_remaining > 0) {
540
541
542
543
544
545 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
546 val = cpu_to_le32(val);
547 memcpy(buf, &val, buf_remaining);
548 buf_remaining = 0;
549 rx_fifo_avail--;
550 }
551
552
553 if (WARN_ON_ONCE(rx_fifo_avail))
554 return -EINVAL;
555
556 i2c_dev->msg_buf_remaining = buf_remaining;
557 i2c_dev->msg_buf = buf;
558
559 return 0;
560}
561
562static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
563{
564 u32 val;
565 int tx_fifo_avail;
566 u8 *buf = i2c_dev->msg_buf;
567 size_t buf_remaining = i2c_dev->msg_buf_remaining;
568 int words_to_transfer;
569
570 if (i2c_dev->hw->has_mst_fifo) {
571 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
572 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
573 } else {
574 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
575 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
576 }
577
578
579 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
580
581
582 if (words_to_transfer) {
583 if (words_to_transfer > tx_fifo_avail)
584 words_to_transfer = tx_fifo_avail;
585
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588
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591
592
593 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
594 tx_fifo_avail -= words_to_transfer;
595 i2c_dev->msg_buf_remaining = buf_remaining;
596 i2c_dev->msg_buf = buf +
597 words_to_transfer * BYTES_PER_FIFO_WORD;
598 barrier();
599
600 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
601
602 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
603 }
604
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607
608
609
610 if (tx_fifo_avail > 0 && buf_remaining > 0) {
611
612
613
614
615
616 memcpy(&val, buf, buf_remaining);
617 val = le32_to_cpu(val);
618
619
620 i2c_dev->msg_buf_remaining = 0;
621 i2c_dev->msg_buf = NULL;
622 barrier();
623
624 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
625 }
626
627 return 0;
628}
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630
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634
635
636
637static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
638{
639 u32 val;
640
641 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
642 val |= DVC_CTRL_REG3_SW_PROG;
643 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
644 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
645
646 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
647 val |= DVC_CTRL_REG1_INTR_EN;
648 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
649}
650
651static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
652{
653 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
654 int ret;
655
656 ret = pinctrl_pm_select_default_state(i2c_dev->dev);
657 if (ret)
658 return ret;
659
660 ret = clk_enable(i2c_dev->fast_clk);
661 if (ret < 0) {
662 dev_err(i2c_dev->dev,
663 "Enabling fast clk failed, err %d\n", ret);
664 return ret;
665 }
666
667 ret = clk_enable(i2c_dev->slow_clk);
668 if (ret < 0) {
669 dev_err(dev, "failed to enable slow clock: %d\n", ret);
670 goto disable_fast_clk;
671 }
672
673 ret = clk_enable(i2c_dev->div_clk);
674 if (ret < 0) {
675 dev_err(i2c_dev->dev,
676 "Enabling div clk failed, err %d\n", ret);
677 goto disable_slow_clk;
678 }
679
680
681
682
683
684
685
686 if (i2c_dev->is_vi) {
687 ret = tegra_i2c_init(i2c_dev, true);
688 if (ret)
689 goto disable_div_clk;
690 }
691
692 return 0;
693
694disable_div_clk:
695 clk_disable(i2c_dev->div_clk);
696disable_slow_clk:
697 clk_disable(i2c_dev->slow_clk);
698disable_fast_clk:
699 clk_disable(i2c_dev->fast_clk);
700 return ret;
701}
702
703static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
704{
705 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
706
707 clk_disable(i2c_dev->div_clk);
708 clk_disable(i2c_dev->slow_clk);
709 clk_disable(i2c_dev->fast_clk);
710
711 return pinctrl_pm_select_idle_state(i2c_dev->dev);
712}
713
714static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
715{
716 unsigned long reg_offset;
717 void __iomem *addr;
718 u32 val;
719 int err;
720
721 if (i2c_dev->hw->has_config_load_reg) {
722 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD);
723 addr = i2c_dev->base + reg_offset;
724 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
725
726 if (i2c_dev->is_curr_atomic_xfer)
727 err = readl_relaxed_poll_timeout_atomic(
728 addr, val, val == 0, 1000,
729 I2C_CONFIG_LOAD_TIMEOUT);
730 else
731 err = readl_relaxed_poll_timeout(
732 addr, val, val == 0, 1000,
733 I2C_CONFIG_LOAD_TIMEOUT);
734
735 if (err) {
736 dev_warn(i2c_dev->dev,
737 "timeout waiting for config load\n");
738 return err;
739 }
740 }
741
742 return 0;
743}
744
745static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
746{
747 u32 value;
748
749 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
750 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
751 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
752
753 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
754 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
755 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
756 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
757 i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
758
759 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
760 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
761 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
762
763 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
764 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
765 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
766 i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
767
768 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
769 i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
770
771 i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
772}
773
774static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
775{
776 u32 val;
777 int err;
778 u32 clk_divisor, clk_multiplier;
779 u32 tsu_thd;
780 u8 tlow, thigh;
781
782 reset_control_assert(i2c_dev->rst);
783 udelay(2);
784 reset_control_deassert(i2c_dev->rst);
785
786 if (i2c_dev->is_dvc)
787 tegra_dvc_init(i2c_dev);
788
789 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
790 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
791
792 if (i2c_dev->hw->has_multi_master_mode)
793 val |= I2C_CNFG_MULTI_MASTER_MODE;
794
795 i2c_writel(i2c_dev, val, I2C_CNFG);
796 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
797
798 if (i2c_dev->is_vi)
799 tegra_i2c_vi_init(i2c_dev);
800
801
802 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
803 i2c_dev->hw->clk_divisor_hs_mode) |
804 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE,
805 i2c_dev->clk_divisor_non_hs_mode);
806 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
807
808 if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
809 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
810 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
811 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
812 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
813 } else {
814 tlow = i2c_dev->hw->tlow_std_mode;
815 thigh = i2c_dev->hw->thigh_std_mode;
816 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
817 }
818
819 if (i2c_dev->hw->has_interface_timing_reg) {
820 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
821 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
822 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
823 }
824
825
826
827
828
829 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
830 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
831
832 if (!clk_reinit) {
833 clk_multiplier = (tlow + thigh + 2);
834 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1);
835 err = clk_set_rate(i2c_dev->div_clk,
836 i2c_dev->bus_clk_rate * clk_multiplier);
837 if (err) {
838 dev_err(i2c_dev->dev,
839 "failed changing clock rate: %d\n", err);
840 return err;
841 }
842 }
843
844 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
845 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
846
847 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
848 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
849 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
850 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
851 }
852
853 err = tegra_i2c_flush_fifos(i2c_dev);
854 if (err)
855 return err;
856
857 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
858 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
859
860 err = tegra_i2c_wait_for_config_load(i2c_dev);
861 if (err)
862 return err;
863
864 return 0;
865}
866
867static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
868{
869 u32 cnfg;
870
871
872
873
874
875
876
877 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
878
879 cnfg = i2c_readl(i2c_dev, I2C_CNFG);
880 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
881 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
882
883 return tegra_i2c_wait_for_config_load(i2c_dev);
884}
885
886static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
887{
888 u32 status;
889 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
890 struct tegra_i2c_dev *i2c_dev = dev_id;
891
892 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
893
894 if (status == 0) {
895 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
896 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
897 i2c_readl(i2c_dev, I2C_STATUS),
898 i2c_readl(i2c_dev, I2C_CNFG));
899 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
900 goto err;
901 }
902
903 if (unlikely(status & status_err)) {
904 tegra_i2c_disable_packet_mode(i2c_dev);
905 if (status & I2C_INT_NO_ACK)
906 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
907 if (status & I2C_INT_ARBITRATION_LOST)
908 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
909 goto err;
910 }
911
912
913
914
915
916 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
917 goto err;
918
919 if (!i2c_dev->is_curr_dma_xfer) {
920 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
921 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
922
923
924
925
926
927 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
928 goto err;
929 }
930 }
931
932 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
933 if (i2c_dev->msg_buf_remaining)
934 tegra_i2c_fill_tx_fifo(i2c_dev);
935 else
936 tegra_i2c_mask_irq(i2c_dev,
937 I2C_INT_TX_FIFO_DATA_REQ);
938 }
939 }
940
941 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
942 if (i2c_dev->is_dvc)
943 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
944
945
946
947
948
949
950
951
952 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
953 if (i2c_dev->is_curr_dma_xfer)
954 i2c_dev->msg_buf_remaining = 0;
955
956
957
958
959 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
960 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
961 goto err;
962 }
963 complete(&i2c_dev->msg_complete);
964 }
965 goto done;
966err:
967
968 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
969 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
970 I2C_INT_RX_FIFO_DATA_REQ);
971 if (i2c_dev->hw->supports_bus_clear)
972 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
973 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
974 if (i2c_dev->is_dvc)
975 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
976
977 if (i2c_dev->is_curr_dma_xfer) {
978 if (i2c_dev->msg_read)
979 dmaengine_terminate_async(i2c_dev->rx_dma_chan);
980 else
981 dmaengine_terminate_async(i2c_dev->tx_dma_chan);
982
983 complete(&i2c_dev->dma_complete);
984 }
985
986 complete(&i2c_dev->msg_complete);
987done:
988 return IRQ_HANDLED;
989}
990
991static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
992 size_t len)
993{
994 u32 val, reg;
995 u8 dma_burst;
996 struct dma_slave_config slv_config = {0};
997 struct dma_chan *chan;
998 int ret;
999 unsigned long reg_offset;
1000
1001 if (i2c_dev->hw->has_mst_fifo)
1002 reg = I2C_MST_FIFO_CONTROL;
1003 else
1004 reg = I2C_FIFO_CONTROL;
1005
1006 if (i2c_dev->is_curr_dma_xfer) {
1007 if (len & 0xF)
1008 dma_burst = 1;
1009 else if (len & 0x10)
1010 dma_burst = 4;
1011 else
1012 dma_burst = 8;
1013
1014 if (i2c_dev->msg_read) {
1015 chan = i2c_dev->rx_dma_chan;
1016 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1017 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1018 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1019 slv_config.src_maxburst = dma_burst;
1020
1021 if (i2c_dev->hw->has_mst_fifo)
1022 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1023 else
1024 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1025 } else {
1026 chan = i2c_dev->tx_dma_chan;
1027 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1028 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1029 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1030 slv_config.dst_maxburst = dma_burst;
1031
1032 if (i2c_dev->hw->has_mst_fifo)
1033 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1034 else
1035 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1036 }
1037
1038 slv_config.device_fc = true;
1039 ret = dmaengine_slave_config(chan, &slv_config);
1040 if (ret < 0) {
1041 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n",
1042 ret);
1043 dev_err(i2c_dev->dev, "falling back to PIO\n");
1044 tegra_i2c_release_dma(i2c_dev);
1045 i2c_dev->is_curr_dma_xfer = false;
1046 } else {
1047 goto out;
1048 }
1049 }
1050
1051 if (i2c_dev->hw->has_mst_fifo)
1052 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1053 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1054 else
1055 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1056 I2C_FIFO_CONTROL_RX_TRIG(1);
1057out:
1058 i2c_writel(i2c_dev, val, reg);
1059}
1060
1061static unsigned long
1062tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1063 struct completion *complete,
1064 unsigned int timeout_ms)
1065{
1066 ktime_t ktime = ktime_get();
1067 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1068
1069 do {
1070 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1071
1072 if (status)
1073 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1074
1075 if (completion_done(complete)) {
1076 s64 delta = ktime_ms_delta(ktimeout, ktime);
1077
1078 return msecs_to_jiffies(delta) ?: 1;
1079 }
1080
1081 ktime = ktime_get();
1082
1083 } while (ktime_before(ktime, ktimeout));
1084
1085 return 0;
1086}
1087
1088static unsigned long
1089tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev,
1090 struct completion *complete,
1091 unsigned int timeout_ms)
1092{
1093 unsigned long ret;
1094
1095 if (i2c_dev->is_curr_atomic_xfer) {
1096 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete,
1097 timeout_ms);
1098 } else {
1099 enable_irq(i2c_dev->irq);
1100 ret = wait_for_completion_timeout(complete,
1101 msecs_to_jiffies(timeout_ms));
1102 disable_irq(i2c_dev->irq);
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114 if (ret == 0)
1115 ret = tegra_i2c_poll_completion_timeout(i2c_dev,
1116 complete, 0);
1117 }
1118
1119 return ret;
1120}
1121
1122static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1123{
1124 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1125 int err;
1126 unsigned long time_left;
1127 u32 reg;
1128
1129 reinit_completion(&i2c_dev->msg_complete);
1130 reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1131 I2C_BC_TERMINATE;
1132 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1133 if (i2c_dev->hw->has_config_load_reg) {
1134 err = tegra_i2c_wait_for_config_load(i2c_dev);
1135 if (err)
1136 return err;
1137 }
1138
1139 reg |= I2C_BC_ENABLE;
1140 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG);
1141 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1142
1143 time_left = tegra_i2c_wait_completion_timeout(
1144 i2c_dev, &i2c_dev->msg_complete, 50);
1145 if (time_left == 0) {
1146 dev_err(i2c_dev->dev, "timed out for bus clear\n");
1147 return -ETIMEDOUT;
1148 }
1149
1150 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1151 if (!(reg & I2C_BC_STATUS)) {
1152 dev_err(i2c_dev->dev,
1153 "un-recovered arbitration lost\n");
1154 return -EIO;
1155 }
1156
1157 return -EAGAIN;
1158}
1159
1160static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1161 struct i2c_msg *msg,
1162 enum msg_end_type end_state)
1163{
1164 u32 packet_header;
1165 u32 int_mask;
1166 unsigned long time_left;
1167 size_t xfer_size;
1168 u32 *buffer = NULL;
1169 int err = 0;
1170 bool dma;
1171 u16 xfer_time = 100;
1172
1173 tegra_i2c_flush_fifos(i2c_dev);
1174
1175 i2c_dev->msg_buf = msg->buf;
1176 i2c_dev->msg_buf_remaining = msg->len;
1177 i2c_dev->msg_err = I2C_ERR_NONE;
1178 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
1179 reinit_completion(&i2c_dev->msg_complete);
1180
1181 if (i2c_dev->msg_read)
1182 xfer_size = msg->len;
1183 else
1184 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1185
1186 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1187 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) &&
1188 i2c_dev->dma_buf &&
1189 !i2c_dev->is_curr_atomic_xfer;
1190 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1191 dma = i2c_dev->is_curr_dma_xfer;
1192
1193
1194
1195
1196 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1197 i2c_dev->bus_clk_rate);
1198
1199 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1200 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1201 if (dma) {
1202 if (i2c_dev->msg_read) {
1203 dma_sync_single_for_device(i2c_dev->dev,
1204 i2c_dev->dma_phys,
1205 xfer_size,
1206 DMA_FROM_DEVICE);
1207 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1208 if (err < 0) {
1209 dev_err(i2c_dev->dev,
1210 "starting RX DMA failed, err %d\n",
1211 err);
1212 return err;
1213 }
1214
1215 } else {
1216 dma_sync_single_for_cpu(i2c_dev->dev,
1217 i2c_dev->dma_phys,
1218 xfer_size,
1219 DMA_TO_DEVICE);
1220 buffer = i2c_dev->dma_buf;
1221 }
1222 }
1223
1224 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1225 FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1226 PACKET_HEADER0_PROTOCOL_I2C) |
1227 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1228 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1229 if (dma && !i2c_dev->msg_read)
1230 *buffer++ = packet_header;
1231 else
1232 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1233
1234 packet_header = msg->len - 1;
1235 if (dma && !i2c_dev->msg_read)
1236 *buffer++ = packet_header;
1237 else
1238 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1239
1240 packet_header = I2C_HEADER_IE_ENABLE;
1241 if (end_state == MSG_END_CONTINUE)
1242 packet_header |= I2C_HEADER_CONTINUE_XFER;
1243 else if (end_state == MSG_END_REPEAT_START)
1244 packet_header |= I2C_HEADER_REPEAT_START;
1245 if (msg->flags & I2C_M_TEN) {
1246 packet_header |= msg->addr;
1247 packet_header |= I2C_HEADER_10BIT_ADDR;
1248 } else {
1249 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1250 }
1251 if (msg->flags & I2C_M_IGNORE_NAK)
1252 packet_header |= I2C_HEADER_CONT_ON_NAK;
1253 if (msg->flags & I2C_M_RD)
1254 packet_header |= I2C_HEADER_READ;
1255 if (dma && !i2c_dev->msg_read)
1256 *buffer++ = packet_header;
1257 else
1258 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1259
1260 if (!i2c_dev->msg_read) {
1261 if (dma) {
1262 memcpy(buffer, msg->buf, msg->len);
1263 dma_sync_single_for_device(i2c_dev->dev,
1264 i2c_dev->dma_phys,
1265 xfer_size,
1266 DMA_TO_DEVICE);
1267 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1268 if (err < 0) {
1269 dev_err(i2c_dev->dev,
1270 "starting TX DMA failed, err %d\n",
1271 err);
1272 return err;
1273 }
1274 } else {
1275 tegra_i2c_fill_tx_fifo(i2c_dev);
1276 }
1277 }
1278
1279 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1280 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1281 if (!dma) {
1282 if (msg->flags & I2C_M_RD)
1283 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1284 else if (i2c_dev->msg_buf_remaining)
1285 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1286 }
1287
1288 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1289 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
1290 i2c_readl(i2c_dev, I2C_INT_MASK));
1291
1292 if (dma) {
1293 time_left = tegra_i2c_wait_completion_timeout(
1294 i2c_dev, &i2c_dev->dma_complete, xfer_time);
1295
1296
1297
1298
1299
1300
1301 dmaengine_synchronize(i2c_dev->msg_read ?
1302 i2c_dev->rx_dma_chan :
1303 i2c_dev->tx_dma_chan);
1304
1305 dmaengine_terminate_sync(i2c_dev->msg_read ?
1306 i2c_dev->rx_dma_chan :
1307 i2c_dev->tx_dma_chan);
1308
1309 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1310 dev_err(i2c_dev->dev, "DMA transfer timeout\n");
1311 tegra_i2c_init(i2c_dev, true);
1312 return -ETIMEDOUT;
1313 }
1314
1315 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1316 dma_sync_single_for_cpu(i2c_dev->dev,
1317 i2c_dev->dma_phys,
1318 xfer_size,
1319 DMA_FROM_DEVICE);
1320 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf,
1321 msg->len);
1322 }
1323 }
1324
1325 time_left = tegra_i2c_wait_completion_timeout(
1326 i2c_dev, &i2c_dev->msg_complete, xfer_time);
1327
1328 tegra_i2c_mask_irq(i2c_dev, int_mask);
1329
1330 if (time_left == 0) {
1331 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
1332 tegra_i2c_init(i2c_dev, true);
1333 return -ETIMEDOUT;
1334 }
1335
1336 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1337 time_left, completion_done(&i2c_dev->msg_complete),
1338 i2c_dev->msg_err);
1339
1340 i2c_dev->is_curr_dma_xfer = false;
1341 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
1342 return 0;
1343
1344 tegra_i2c_init(i2c_dev, true);
1345
1346 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1347 if (!i2c_dev->is_multimaster_mode)
1348 return i2c_recover_bus(&i2c_dev->adapter);
1349 return -EAGAIN;
1350 }
1351
1352 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1353 if (msg->flags & I2C_M_IGNORE_NAK)
1354 return 0;
1355 return -EREMOTEIO;
1356 }
1357
1358 return -EIO;
1359}
1360
1361static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1362 int num)
1363{
1364 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1365 int i;
1366 int ret;
1367
1368 ret = pm_runtime_get_sync(i2c_dev->dev);
1369 if (ret < 0) {
1370 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1371 return ret;
1372 }
1373
1374 for (i = 0; i < num; i++) {
1375 enum msg_end_type end_type = MSG_END_STOP;
1376
1377 if (i < (num - 1)) {
1378 if (msgs[i + 1].flags & I2C_M_NOSTART)
1379 end_type = MSG_END_CONTINUE;
1380 else
1381 end_type = MSG_END_REPEAT_START;
1382 }
1383 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1384 if (ret)
1385 break;
1386 }
1387
1388 pm_runtime_put(i2c_dev->dev);
1389
1390 return ret ?: i;
1391}
1392
1393static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1394 struct i2c_msg msgs[], int num)
1395{
1396 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1397 int ret;
1398
1399 i2c_dev->is_curr_atomic_xfer = true;
1400 ret = tegra_i2c_xfer(adap, msgs, num);
1401 i2c_dev->is_curr_atomic_xfer = false;
1402
1403 return ret;
1404}
1405
1406static u32 tegra_i2c_func(struct i2c_adapter *adap)
1407{
1408 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1409 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1410 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1411
1412 if (i2c_dev->hw->has_continue_xfer_support)
1413 ret |= I2C_FUNC_NOSTART;
1414 return ret;
1415}
1416
1417static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1418{
1419 struct device_node *np = i2c_dev->dev->of_node;
1420 int ret;
1421 bool multi_mode;
1422
1423 ret = of_property_read_u32(np, "clock-frequency",
1424 &i2c_dev->bus_clk_rate);
1425 if (ret)
1426 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
1427
1428 multi_mode = of_property_read_bool(np, "multi-master");
1429 i2c_dev->is_multimaster_mode = multi_mode;
1430}
1431
1432static const struct i2c_algorithm tegra_i2c_algo = {
1433 .master_xfer = tegra_i2c_xfer,
1434 .master_xfer_atomic = tegra_i2c_xfer_atomic,
1435 .functionality = tegra_i2c_func,
1436};
1437
1438
1439static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1440 .flags = I2C_AQ_NO_ZERO_LEN,
1441 .max_read_len = SZ_4K,
1442 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1443};
1444
1445static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1446 .flags = I2C_AQ_NO_ZERO_LEN,
1447 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1448};
1449
1450static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1451 .recover_bus = tegra_i2c_issue_bus_clear,
1452};
1453
1454static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1455 .has_continue_xfer_support = false,
1456 .has_per_pkt_xfer_complete_irq = false,
1457 .has_single_clk_source = false,
1458 .clk_divisor_hs_mode = 3,
1459 .clk_divisor_std_mode = 0,
1460 .clk_divisor_fast_mode = 0,
1461 .clk_divisor_fast_plus_mode = 0,
1462 .has_config_load_reg = false,
1463 .has_multi_master_mode = false,
1464 .has_slcg_override_reg = false,
1465 .has_mst_fifo = false,
1466 .quirks = &tegra_i2c_quirks,
1467 .supports_bus_clear = false,
1468 .has_apb_dma = true,
1469 .tlow_std_mode = 0x4,
1470 .thigh_std_mode = 0x2,
1471 .tlow_fast_fastplus_mode = 0x4,
1472 .thigh_fast_fastplus_mode = 0x2,
1473 .setup_hold_time_std_mode = 0x0,
1474 .setup_hold_time_fast_fast_plus_mode = 0x0,
1475 .setup_hold_time_hs_mode = 0x0,
1476 .has_interface_timing_reg = false,
1477};
1478
1479static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1480 .has_continue_xfer_support = true,
1481 .has_per_pkt_xfer_complete_irq = false,
1482 .has_single_clk_source = false,
1483 .clk_divisor_hs_mode = 3,
1484 .clk_divisor_std_mode = 0,
1485 .clk_divisor_fast_mode = 0,
1486 .clk_divisor_fast_plus_mode = 0,
1487 .has_config_load_reg = false,
1488 .has_multi_master_mode = false,
1489 .has_slcg_override_reg = false,
1490 .has_mst_fifo = false,
1491 .quirks = &tegra_i2c_quirks,
1492 .supports_bus_clear = false,
1493 .has_apb_dma = true,
1494 .tlow_std_mode = 0x4,
1495 .thigh_std_mode = 0x2,
1496 .tlow_fast_fastplus_mode = 0x4,
1497 .thigh_fast_fastplus_mode = 0x2,
1498 .setup_hold_time_std_mode = 0x0,
1499 .setup_hold_time_fast_fast_plus_mode = 0x0,
1500 .setup_hold_time_hs_mode = 0x0,
1501 .has_interface_timing_reg = false,
1502};
1503
1504static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1505 .has_continue_xfer_support = true,
1506 .has_per_pkt_xfer_complete_irq = true,
1507 .has_single_clk_source = true,
1508 .clk_divisor_hs_mode = 1,
1509 .clk_divisor_std_mode = 0x19,
1510 .clk_divisor_fast_mode = 0x19,
1511 .clk_divisor_fast_plus_mode = 0x10,
1512 .has_config_load_reg = false,
1513 .has_multi_master_mode = false,
1514 .has_slcg_override_reg = false,
1515 .has_mst_fifo = false,
1516 .quirks = &tegra_i2c_quirks,
1517 .supports_bus_clear = true,
1518 .has_apb_dma = true,
1519 .tlow_std_mode = 0x4,
1520 .thigh_std_mode = 0x2,
1521 .tlow_fast_fastplus_mode = 0x4,
1522 .thigh_fast_fastplus_mode = 0x2,
1523 .setup_hold_time_std_mode = 0x0,
1524 .setup_hold_time_fast_fast_plus_mode = 0x0,
1525 .setup_hold_time_hs_mode = 0x0,
1526 .has_interface_timing_reg = false,
1527};
1528
1529static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1530 .has_continue_xfer_support = true,
1531 .has_per_pkt_xfer_complete_irq = true,
1532 .has_single_clk_source = true,
1533 .clk_divisor_hs_mode = 1,
1534 .clk_divisor_std_mode = 0x19,
1535 .clk_divisor_fast_mode = 0x19,
1536 .clk_divisor_fast_plus_mode = 0x10,
1537 .has_config_load_reg = true,
1538 .has_multi_master_mode = false,
1539 .has_slcg_override_reg = true,
1540 .has_mst_fifo = false,
1541 .quirks = &tegra_i2c_quirks,
1542 .supports_bus_clear = true,
1543 .has_apb_dma = true,
1544 .tlow_std_mode = 0x4,
1545 .thigh_std_mode = 0x2,
1546 .tlow_fast_fastplus_mode = 0x4,
1547 .thigh_fast_fastplus_mode = 0x2,
1548 .setup_hold_time_std_mode = 0x0,
1549 .setup_hold_time_fast_fast_plus_mode = 0x0,
1550 .setup_hold_time_hs_mode = 0x0,
1551 .has_interface_timing_reg = true,
1552};
1553
1554static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1555 .has_continue_xfer_support = true,
1556 .has_per_pkt_xfer_complete_irq = true,
1557 .has_single_clk_source = true,
1558 .clk_divisor_hs_mode = 1,
1559 .clk_divisor_std_mode = 0x19,
1560 .clk_divisor_fast_mode = 0x19,
1561 .clk_divisor_fast_plus_mode = 0x10,
1562 .has_config_load_reg = true,
1563 .has_multi_master_mode = false,
1564 .has_slcg_override_reg = true,
1565 .has_mst_fifo = false,
1566 .quirks = &tegra_i2c_quirks,
1567 .supports_bus_clear = true,
1568 .has_apb_dma = true,
1569 .tlow_std_mode = 0x4,
1570 .thigh_std_mode = 0x2,
1571 .tlow_fast_fastplus_mode = 0x4,
1572 .thigh_fast_fastplus_mode = 0x2,
1573 .setup_hold_time_std_mode = 0,
1574 .setup_hold_time_fast_fast_plus_mode = 0,
1575 .setup_hold_time_hs_mode = 0,
1576 .has_interface_timing_reg = true,
1577};
1578
1579static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1580 .has_continue_xfer_support = true,
1581 .has_per_pkt_xfer_complete_irq = true,
1582 .has_single_clk_source = true,
1583 .clk_divisor_hs_mode = 1,
1584 .clk_divisor_std_mode = 0x16,
1585 .clk_divisor_fast_mode = 0x19,
1586 .clk_divisor_fast_plus_mode = 0x10,
1587 .has_config_load_reg = true,
1588 .has_multi_master_mode = false,
1589 .has_slcg_override_reg = true,
1590 .has_mst_fifo = false,
1591 .quirks = &tegra_i2c_quirks,
1592 .supports_bus_clear = true,
1593 .has_apb_dma = false,
1594 .tlow_std_mode = 0x4,
1595 .thigh_std_mode = 0x3,
1596 .tlow_fast_fastplus_mode = 0x4,
1597 .thigh_fast_fastplus_mode = 0x2,
1598 .setup_hold_time_std_mode = 0,
1599 .setup_hold_time_fast_fast_plus_mode = 0,
1600 .setup_hold_time_hs_mode = 0,
1601 .has_interface_timing_reg = true,
1602};
1603
1604static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1605 .has_continue_xfer_support = true,
1606 .has_per_pkt_xfer_complete_irq = true,
1607 .has_single_clk_source = true,
1608 .clk_divisor_hs_mode = 1,
1609 .clk_divisor_std_mode = 0x4f,
1610 .clk_divisor_fast_mode = 0x3c,
1611 .clk_divisor_fast_plus_mode = 0x16,
1612 .has_config_load_reg = true,
1613 .has_multi_master_mode = true,
1614 .has_slcg_override_reg = true,
1615 .has_mst_fifo = true,
1616 .quirks = &tegra194_i2c_quirks,
1617 .supports_bus_clear = true,
1618 .has_apb_dma = false,
1619 .tlow_std_mode = 0x8,
1620 .thigh_std_mode = 0x7,
1621 .tlow_fast_fastplus_mode = 0x2,
1622 .thigh_fast_fastplus_mode = 0x2,
1623 .setup_hold_time_std_mode = 0x08080808,
1624 .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1625 .setup_hold_time_hs_mode = 0x090909,
1626 .has_interface_timing_reg = true,
1627};
1628
1629
1630static const struct of_device_id tegra_i2c_of_match[] = {
1631 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1632 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1633 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1634 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1635 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1636 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1637 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1638 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1639 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1640 {},
1641};
1642MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1643
1644static int tegra_i2c_probe(struct platform_device *pdev)
1645{
1646 struct device *dev = &pdev->dev;
1647 struct tegra_i2c_dev *i2c_dev;
1648 struct resource *res;
1649 struct clk *div_clk;
1650 struct clk *fast_clk;
1651 void __iomem *base;
1652 phys_addr_t base_phys;
1653 int irq;
1654 int ret;
1655
1656 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1657 base_phys = res->start;
1658 base = devm_ioremap_resource(&pdev->dev, res);
1659 if (IS_ERR(base))
1660 return PTR_ERR(base);
1661
1662 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1663 if (!res) {
1664 dev_err(&pdev->dev, "no irq resource\n");
1665 return -EINVAL;
1666 }
1667 irq = res->start;
1668
1669 div_clk = devm_clk_get(&pdev->dev, "div-clk");
1670 if (IS_ERR(div_clk)) {
1671 if (PTR_ERR(div_clk) != -EPROBE_DEFER)
1672 dev_err(&pdev->dev, "missing controller clock\n");
1673
1674 return PTR_ERR(div_clk);
1675 }
1676
1677 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1678 if (!i2c_dev)
1679 return -ENOMEM;
1680
1681 i2c_dev->base = base;
1682 i2c_dev->base_phys = base_phys;
1683 i2c_dev->div_clk = div_clk;
1684 i2c_dev->adapter.algo = &tegra_i2c_algo;
1685 i2c_dev->adapter.retries = 1;
1686 i2c_dev->adapter.timeout = 6 * HZ;
1687 i2c_dev->irq = irq;
1688 i2c_dev->cont_id = pdev->id;
1689 i2c_dev->dev = &pdev->dev;
1690
1691 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c");
1692 if (IS_ERR(i2c_dev->rst)) {
1693 dev_err(&pdev->dev, "missing controller reset\n");
1694 return PTR_ERR(i2c_dev->rst);
1695 }
1696
1697 tegra_i2c_parse_dt(i2c_dev);
1698
1699 i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1700 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
1701 "nvidia,tegra20-i2c-dvc");
1702 i2c_dev->is_vi = of_device_is_compatible(dev->of_node,
1703 "nvidia,tegra210-i2c-vi");
1704 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1705 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len +
1706 I2C_PACKET_HEADER_SIZE;
1707 init_completion(&i2c_dev->msg_complete);
1708 init_completion(&i2c_dev->dma_complete);
1709
1710 if (!i2c_dev->hw->has_single_clk_source) {
1711 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
1712 if (IS_ERR(fast_clk)) {
1713 dev_err(&pdev->dev, "missing fast clock\n");
1714 return PTR_ERR(fast_clk);
1715 }
1716 i2c_dev->fast_clk = fast_clk;
1717 }
1718
1719 if (i2c_dev->is_vi) {
1720 i2c_dev->slow_clk = devm_clk_get(dev, "slow");
1721 if (IS_ERR(i2c_dev->slow_clk)) {
1722 if (PTR_ERR(i2c_dev->slow_clk) != -EPROBE_DEFER)
1723 dev_err(dev, "failed to get slow clock: %ld\n",
1724 PTR_ERR(i2c_dev->slow_clk));
1725
1726 return PTR_ERR(i2c_dev->slow_clk);
1727 }
1728 }
1729
1730 platform_set_drvdata(pdev, i2c_dev);
1731
1732 ret = clk_prepare(i2c_dev->fast_clk);
1733 if (ret < 0) {
1734 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1735 return ret;
1736 }
1737
1738 ret = clk_prepare(i2c_dev->slow_clk);
1739 if (ret < 0) {
1740 dev_err(dev, "failed to prepare slow clock: %d\n", ret);
1741 goto unprepare_fast_clk;
1742 }
1743
1744 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ &&
1745 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ)
1746 i2c_dev->clk_divisor_non_hs_mode =
1747 i2c_dev->hw->clk_divisor_fast_plus_mode;
1748 else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
1749 i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
1750 i2c_dev->clk_divisor_non_hs_mode =
1751 i2c_dev->hw->clk_divisor_fast_mode;
1752 else
1753 i2c_dev->clk_divisor_non_hs_mode =
1754 i2c_dev->hw->clk_divisor_std_mode;
1755
1756 ret = clk_prepare(i2c_dev->div_clk);
1757 if (ret < 0) {
1758 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
1759 goto unprepare_slow_clk;
1760 }
1761
1762
1763
1764
1765
1766
1767
1768
1769 if (!i2c_dev->is_vi)
1770 pm_runtime_irq_safe(&pdev->dev);
1771 pm_runtime_enable(&pdev->dev);
1772 if (!pm_runtime_enabled(&pdev->dev)) {
1773 ret = tegra_i2c_runtime_resume(&pdev->dev);
1774 if (ret < 0) {
1775 dev_err(&pdev->dev, "runtime resume failed\n");
1776 goto unprepare_div_clk;
1777 }
1778 } else {
1779 ret = pm_runtime_get_sync(i2c_dev->dev);
1780 if (ret < 0) {
1781 dev_err(&pdev->dev, "runtime resume failed\n");
1782 goto disable_rpm;
1783 }
1784 }
1785
1786 if (i2c_dev->is_multimaster_mode) {
1787 ret = clk_enable(i2c_dev->div_clk);
1788 if (ret < 0) {
1789 dev_err(i2c_dev->dev, "div_clk enable failed %d\n",
1790 ret);
1791 goto put_rpm;
1792 }
1793 }
1794
1795 if (i2c_dev->hw->supports_bus_clear)
1796 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1797
1798 ret = tegra_i2c_init_dma(i2c_dev);
1799 if (ret < 0)
1800 goto disable_div_clk;
1801
1802 ret = tegra_i2c_init(i2c_dev, false);
1803 if (ret) {
1804 dev_err(&pdev->dev, "Failed to initialize i2c controller\n");
1805 goto release_dma;
1806 }
1807
1808 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1809
1810 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, tegra_i2c_isr,
1811 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c_dev);
1812 if (ret) {
1813 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
1814 goto release_dma;
1815 }
1816
1817 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1818 i2c_dev->adapter.owner = THIS_MODULE;
1819 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1820 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev),
1821 sizeof(i2c_dev->adapter.name));
1822 i2c_dev->adapter.dev.parent = &pdev->dev;
1823 i2c_dev->adapter.nr = pdev->id;
1824 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
1825
1826 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
1827 if (ret)
1828 goto release_dma;
1829
1830 pm_runtime_put(&pdev->dev);
1831
1832 return 0;
1833
1834release_dma:
1835 tegra_i2c_release_dma(i2c_dev);
1836
1837disable_div_clk:
1838 if (i2c_dev->is_multimaster_mode)
1839 clk_disable(i2c_dev->div_clk);
1840
1841put_rpm:
1842 if (pm_runtime_enabled(&pdev->dev))
1843 pm_runtime_put_sync(&pdev->dev);
1844 else
1845 tegra_i2c_runtime_suspend(&pdev->dev);
1846
1847disable_rpm:
1848 if (pm_runtime_enabled(&pdev->dev))
1849 pm_runtime_disable(&pdev->dev);
1850
1851unprepare_div_clk:
1852 clk_unprepare(i2c_dev->div_clk);
1853
1854unprepare_slow_clk:
1855 clk_unprepare(i2c_dev->slow_clk);
1856
1857unprepare_fast_clk:
1858 clk_unprepare(i2c_dev->fast_clk);
1859
1860 return ret;
1861}
1862
1863static int tegra_i2c_remove(struct platform_device *pdev)
1864{
1865 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1866
1867 i2c_del_adapter(&i2c_dev->adapter);
1868
1869 if (i2c_dev->is_multimaster_mode)
1870 clk_disable(i2c_dev->div_clk);
1871
1872 pm_runtime_disable(&pdev->dev);
1873 if (!pm_runtime_status_suspended(&pdev->dev))
1874 tegra_i2c_runtime_suspend(&pdev->dev);
1875
1876 clk_unprepare(i2c_dev->div_clk);
1877 clk_unprepare(i2c_dev->slow_clk);
1878 clk_unprepare(i2c_dev->fast_clk);
1879
1880 tegra_i2c_release_dma(i2c_dev);
1881 return 0;
1882}
1883
1884static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1885{
1886 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1887 int err = 0;
1888
1889 i2c_mark_adapter_suspended(&i2c_dev->adapter);
1890
1891 if (!pm_runtime_status_suspended(dev))
1892 err = tegra_i2c_runtime_suspend(dev);
1893
1894 return err;
1895}
1896
1897static int __maybe_unused tegra_i2c_resume(struct device *dev)
1898{
1899 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1900 int err;
1901
1902
1903
1904
1905
1906 err = tegra_i2c_runtime_resume(dev);
1907 if (err)
1908 return err;
1909
1910 err = tegra_i2c_init(i2c_dev, false);
1911 if (err)
1912 return err;
1913
1914
1915
1916
1917
1918
1919 if (pm_runtime_status_suspended(dev)) {
1920 err = tegra_i2c_runtime_suspend(dev);
1921 if (err)
1922 return err;
1923 }
1924
1925 i2c_mark_adapter_resumed(&i2c_dev->adapter);
1926
1927 return 0;
1928}
1929
1930static const struct dev_pm_ops tegra_i2c_pm = {
1931 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1932 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1933 NULL)
1934};
1935
1936static struct platform_driver tegra_i2c_driver = {
1937 .probe = tegra_i2c_probe,
1938 .remove = tegra_i2c_remove,
1939 .driver = {
1940 .name = "tegra-i2c",
1941 .of_match_table = tegra_i2c_of_match,
1942 .pm = &tegra_i2c_pm,
1943 },
1944};
1945
1946module_platform_driver(tegra_i2c_driver);
1947
1948MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1949MODULE_AUTHOR("Colin Cross");
1950MODULE_LICENSE("GPL v2");
1951