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32#include <linux/module.h>
33#include <rdma/ib_verbs.h>
34#include <rdma/ib_addr.h>
35#include <rdma/ib_user_verbs.h>
36#include <rdma/iw_cm.h>
37#include <rdma/ib_mad.h>
38#include <linux/netdevice.h>
39#include <linux/iommu.h>
40#include <linux/pci.h>
41#include <net/addrconf.h>
42
43#include <linux/qed/qed_chain.h>
44#include <linux/qed/qed_if.h>
45#include "qedr.h"
46#include "verbs.h"
47#include <rdma/qedr-abi.h>
48#include "qedr_iw_cm.h"
49
50MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
51MODULE_AUTHOR("QLogic Corporation");
52MODULE_LICENSE("Dual BSD/GPL");
53
54#define QEDR_WQ_MULTIPLIER_DFT (3)
55
56static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
57 enum ib_event_type type)
58{
59 struct ib_event ibev;
60
61 ibev.device = &dev->ibdev;
62 ibev.element.port_num = port_num;
63 ibev.event = type;
64
65 ib_dispatch_event(&ibev);
66}
67
68static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
69 u8 port_num)
70{
71 return IB_LINK_LAYER_ETHERNET;
72}
73
74static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
75{
76 struct qedr_dev *qedr = get_qedr_dev(ibdev);
77 u32 fw_ver = (u32)qedr->attr.fw_ver;
78
79 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
80 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
81 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
82}
83
84static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
85 struct ib_port_immutable *immutable)
86{
87 struct ib_port_attr attr;
88 int err;
89
90 err = qedr_query_port(ibdev, port_num, &attr);
91 if (err)
92 return err;
93
94 immutable->pkey_tbl_len = attr.pkey_tbl_len;
95 immutable->gid_tbl_len = attr.gid_tbl_len;
96 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
97 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
98 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
99
100 return 0;
101}
102
103static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
104 struct ib_port_immutable *immutable)
105{
106 struct ib_port_attr attr;
107 int err;
108
109 err = qedr_query_port(ibdev, port_num, &attr);
110 if (err)
111 return err;
112
113 immutable->gid_tbl_len = 1;
114 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
115 immutable->max_mad_size = 0;
116
117 return 0;
118}
119
120
121static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
122 char *buf)
123{
124 struct qedr_dev *dev =
125 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
126
127 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->attr.hw_ver);
128}
129static DEVICE_ATTR_RO(hw_rev);
130
131static ssize_t hca_type_show(struct device *device,
132 struct device_attribute *attr, char *buf)
133{
134 struct qedr_dev *dev =
135 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
136
137 return scnprintf(buf, PAGE_SIZE, "FastLinQ QL%x %s\n",
138 dev->pdev->device,
139 rdma_protocol_iwarp(&dev->ibdev, 1) ?
140 "iWARP" : "RoCE");
141}
142static DEVICE_ATTR_RO(hca_type);
143
144static struct attribute *qedr_attributes[] = {
145 &dev_attr_hw_rev.attr,
146 &dev_attr_hca_type.attr,
147 NULL
148};
149
150static const struct attribute_group qedr_attr_group = {
151 .attrs = qedr_attributes,
152};
153
154static const struct ib_device_ops qedr_iw_dev_ops = {
155 .get_port_immutable = qedr_iw_port_immutable,
156 .iw_accept = qedr_iw_accept,
157 .iw_add_ref = qedr_iw_qp_add_ref,
158 .iw_connect = qedr_iw_connect,
159 .iw_create_listen = qedr_iw_create_listen,
160 .iw_destroy_listen = qedr_iw_destroy_listen,
161 .iw_get_qp = qedr_iw_get_qp,
162 .iw_reject = qedr_iw_reject,
163 .iw_rem_ref = qedr_iw_qp_rem_ref,
164 .query_gid = qedr_iw_query_gid,
165};
166
167static int qedr_iw_register_device(struct qedr_dev *dev)
168{
169 dev->ibdev.node_type = RDMA_NODE_RNIC;
170
171 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
172
173 memcpy(dev->ibdev.iw_ifname,
174 dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
175
176 return 0;
177}
178
179static const struct ib_device_ops qedr_roce_dev_ops = {
180 .get_port_immutable = qedr_roce_port_immutable,
181 .query_pkey = qedr_query_pkey,
182};
183
184static void qedr_roce_register_device(struct qedr_dev *dev)
185{
186 dev->ibdev.node_type = RDMA_NODE_IB_CA;
187
188 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
189}
190
191static const struct ib_device_ops qedr_dev_ops = {
192 .owner = THIS_MODULE,
193 .driver_id = RDMA_DRIVER_QEDR,
194 .uverbs_abi_ver = QEDR_ABI_VERSION,
195
196 .alloc_mr = qedr_alloc_mr,
197 .alloc_pd = qedr_alloc_pd,
198 .alloc_ucontext = qedr_alloc_ucontext,
199 .create_ah = qedr_create_ah,
200 .create_cq = qedr_create_cq,
201 .create_qp = qedr_create_qp,
202 .create_srq = qedr_create_srq,
203 .dealloc_pd = qedr_dealloc_pd,
204 .dealloc_ucontext = qedr_dealloc_ucontext,
205 .dereg_mr = qedr_dereg_mr,
206 .destroy_ah = qedr_destroy_ah,
207 .destroy_cq = qedr_destroy_cq,
208 .destroy_qp = qedr_destroy_qp,
209 .destroy_srq = qedr_destroy_srq,
210 .get_dev_fw_str = qedr_get_dev_fw_str,
211 .get_dma_mr = qedr_get_dma_mr,
212 .get_link_layer = qedr_link_layer,
213 .map_mr_sg = qedr_map_mr_sg,
214 .mmap = qedr_mmap,
215 .mmap_free = qedr_mmap_free,
216 .modify_qp = qedr_modify_qp,
217 .modify_srq = qedr_modify_srq,
218 .poll_cq = qedr_poll_cq,
219 .post_recv = qedr_post_recv,
220 .post_send = qedr_post_send,
221 .post_srq_recv = qedr_post_srq_recv,
222 .process_mad = qedr_process_mad,
223 .query_device = qedr_query_device,
224 .query_port = qedr_query_port,
225 .query_qp = qedr_query_qp,
226 .query_srq = qedr_query_srq,
227 .reg_user_mr = qedr_reg_user_mr,
228 .req_notify_cq = qedr_arm_cq,
229 .resize_cq = qedr_resize_cq,
230
231 INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
232 INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
233 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
234 INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
235 INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
236};
237
238static int qedr_register_device(struct qedr_dev *dev)
239{
240 int rc;
241
242 dev->ibdev.node_guid = dev->attr.node_guid;
243 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
244
245 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
246 QEDR_UVERBS(QUERY_DEVICE) |
247 QEDR_UVERBS(QUERY_PORT) |
248 QEDR_UVERBS(ALLOC_PD) |
249 QEDR_UVERBS(DEALLOC_PD) |
250 QEDR_UVERBS(CREATE_COMP_CHANNEL) |
251 QEDR_UVERBS(CREATE_CQ) |
252 QEDR_UVERBS(RESIZE_CQ) |
253 QEDR_UVERBS(DESTROY_CQ) |
254 QEDR_UVERBS(REQ_NOTIFY_CQ) |
255 QEDR_UVERBS(CREATE_QP) |
256 QEDR_UVERBS(MODIFY_QP) |
257 QEDR_UVERBS(QUERY_QP) |
258 QEDR_UVERBS(DESTROY_QP) |
259 QEDR_UVERBS(CREATE_SRQ) |
260 QEDR_UVERBS(DESTROY_SRQ) |
261 QEDR_UVERBS(QUERY_SRQ) |
262 QEDR_UVERBS(MODIFY_SRQ) |
263 QEDR_UVERBS(POST_SRQ_RECV) |
264 QEDR_UVERBS(REG_MR) |
265 QEDR_UVERBS(DEREG_MR) |
266 QEDR_UVERBS(POLL_CQ) |
267 QEDR_UVERBS(POST_SEND) |
268 QEDR_UVERBS(POST_RECV);
269
270 if (IS_IWARP(dev)) {
271 rc = qedr_iw_register_device(dev);
272 if (rc)
273 return rc;
274 } else {
275 qedr_roce_register_device(dev);
276 }
277
278 dev->ibdev.phys_port_cnt = 1;
279 dev->ibdev.num_comp_vectors = dev->num_cnq;
280 dev->ibdev.dev.parent = &dev->pdev->dev;
281
282 rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
283 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
284
285 rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
286 if (rc)
287 return rc;
288
289 return ib_register_device(&dev->ibdev, "qedr%d");
290}
291
292
293static int qedr_alloc_mem_sb(struct qedr_dev *dev,
294 struct qed_sb_info *sb_info, u16 sb_id)
295{
296 struct status_block_e4 *sb_virt;
297 dma_addr_t sb_phys;
298 int rc;
299
300 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
301 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
302 if (!sb_virt)
303 return -ENOMEM;
304
305 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
306 sb_virt, sb_phys, sb_id,
307 QED_SB_TYPE_CNQ);
308 if (rc) {
309 pr_err("Status block initialization failed\n");
310 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
311 sb_virt, sb_phys);
312 return rc;
313 }
314
315 return 0;
316}
317
318static void qedr_free_mem_sb(struct qedr_dev *dev,
319 struct qed_sb_info *sb_info, int sb_id)
320{
321 if (sb_info->sb_virt) {
322 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
323 QED_SB_TYPE_CNQ);
324 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
325 (void *)sb_info->sb_virt, sb_info->sb_phys);
326 }
327}
328
329static void qedr_free_resources(struct qedr_dev *dev)
330{
331 int i;
332
333 if (IS_IWARP(dev))
334 destroy_workqueue(dev->iwarp_wq);
335
336 for (i = 0; i < dev->num_cnq; i++) {
337 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
338 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
339 }
340
341 kfree(dev->cnq_array);
342 kfree(dev->sb_array);
343 kfree(dev->sgid_tbl);
344}
345
346static int qedr_alloc_resources(struct qedr_dev *dev)
347{
348 struct qed_chain_init_params params = {
349 .mode = QED_CHAIN_MODE_PBL,
350 .intended_use = QED_CHAIN_USE_TO_CONSUME,
351 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
352 .elem_size = sizeof(struct regpair *),
353 };
354 struct qedr_cnq *cnq;
355 __le16 *cons_pi;
356 int i, rc;
357
358 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
359 GFP_KERNEL);
360 if (!dev->sgid_tbl)
361 return -ENOMEM;
362
363 spin_lock_init(&dev->sgid_lock);
364 xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
365
366 if (IS_IWARP(dev)) {
367 xa_init(&dev->qps);
368 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
369 }
370
371
372 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
373 GFP_KERNEL);
374 if (!dev->sb_array) {
375 rc = -ENOMEM;
376 goto err1;
377 }
378
379 dev->cnq_array = kcalloc(dev->num_cnq,
380 sizeof(*dev->cnq_array), GFP_KERNEL);
381 if (!dev->cnq_array) {
382 rc = -ENOMEM;
383 goto err2;
384 }
385
386 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
387
388
389 params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE,
390 QEDR_ROCE_MAX_CNQ_SIZE);
391
392 for (i = 0; i < dev->num_cnq; i++) {
393 cnq = &dev->cnq_array[i];
394
395 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
396 dev->sb_start + i);
397 if (rc)
398 goto err3;
399
400 rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl,
401 ¶ms);
402 if (rc)
403 goto err4;
404
405 cnq->dev = dev;
406 cnq->sb = &dev->sb_array[i];
407 cons_pi = dev->sb_array[i].sb_virt->pi_array;
408 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
409 cnq->index = i;
410 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
411
412 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
413 i, qed_chain_get_cons_idx(&cnq->pbl));
414 }
415
416 return 0;
417err4:
418 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
419err3:
420 for (--i; i >= 0; i--) {
421 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
422 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
423 }
424 kfree(dev->cnq_array);
425err2:
426 kfree(dev->sb_array);
427err1:
428 kfree(dev->sgid_tbl);
429 return rc;
430}
431
432static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
433{
434 int rc = pci_enable_atomic_ops_to_root(pdev,
435 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
436
437 if (rc) {
438 dev->atomic_cap = IB_ATOMIC_NONE;
439 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
440 } else {
441 dev->atomic_cap = IB_ATOMIC_GLOB;
442 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
443 }
444}
445
446static const struct qed_rdma_ops *qed_ops;
447
448#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
449
450static irqreturn_t qedr_irq_handler(int irq, void *handle)
451{
452 u16 hw_comp_cons, sw_comp_cons;
453 struct qedr_cnq *cnq = handle;
454 struct regpair *cq_handle;
455 struct qedr_cq *cq;
456
457 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
458
459 qed_sb_update_sb_idx(cnq->sb);
460
461 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
462 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
463
464
465 rmb();
466
467 while (sw_comp_cons != hw_comp_cons) {
468 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
469 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
470 cq_handle->lo);
471
472 if (cq == NULL) {
473 DP_ERR(cnq->dev,
474 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
475 cq_handle->hi, cq_handle->lo, sw_comp_cons,
476 hw_comp_cons);
477
478 break;
479 }
480
481 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
482 DP_ERR(cnq->dev,
483 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
484 cq_handle->hi, cq_handle->lo, cq);
485 break;
486 }
487
488 cq->arm_flags = 0;
489
490 if (!cq->destroyed && cq->ibcq.comp_handler)
491 (*cq->ibcq.comp_handler)
492 (&cq->ibcq, cq->ibcq.cq_context);
493
494
495
496
497
498
499
500 cq->cnq_notif++;
501
502 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
503
504 cnq->n_comp++;
505 }
506
507 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
508 sw_comp_cons);
509
510 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
511
512 return IRQ_HANDLED;
513}
514
515static void qedr_sync_free_irqs(struct qedr_dev *dev)
516{
517 u32 vector;
518 u16 idx;
519 int i;
520
521 for (i = 0; i < dev->int_info.used_cnt; i++) {
522 if (dev->int_info.msix_cnt) {
523 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
524 vector = dev->int_info.msix[idx].vector;
525 synchronize_irq(vector);
526 free_irq(vector, &dev->cnq_array[i]);
527 }
528 }
529
530 dev->int_info.used_cnt = 0;
531}
532
533static int qedr_req_msix_irqs(struct qedr_dev *dev)
534{
535 int i, rc = 0;
536 u16 idx;
537
538 if (dev->num_cnq > dev->int_info.msix_cnt) {
539 DP_ERR(dev,
540 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
541 dev->num_cnq, dev->int_info.msix_cnt);
542 return -EINVAL;
543 }
544
545 for (i = 0; i < dev->num_cnq; i++) {
546 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
547 rc = request_irq(dev->int_info.msix[idx].vector,
548 qedr_irq_handler, 0, dev->cnq_array[i].name,
549 &dev->cnq_array[i]);
550 if (rc) {
551 DP_ERR(dev, "Request cnq %d irq failed\n", i);
552 qedr_sync_free_irqs(dev);
553 } else {
554 DP_DEBUG(dev, QEDR_MSG_INIT,
555 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
556 dev->cnq_array[i].name, i,
557 &dev->cnq_array[i]);
558 dev->int_info.used_cnt++;
559 }
560 }
561
562 return rc;
563}
564
565static int qedr_setup_irqs(struct qedr_dev *dev)
566{
567 int rc;
568
569 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
570
571
572 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
573 if (rc < 0)
574 return rc;
575
576 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
577 if (rc) {
578 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
579 return rc;
580 }
581
582 if (dev->int_info.msix_cnt) {
583 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
584 dev->int_info.msix_cnt);
585 rc = qedr_req_msix_irqs(dev);
586 if (rc)
587 return rc;
588 }
589
590 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
591
592 return 0;
593}
594
595static int qedr_set_device_attr(struct qedr_dev *dev)
596{
597 struct qed_rdma_device *qed_attr;
598 struct qedr_device_attr *attr;
599 u32 page_size;
600
601
602 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
603
604
605 page_size = ~dev->attr.page_size_caps + 1;
606 if (page_size > PAGE_SIZE) {
607 DP_ERR(dev,
608 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
609 PAGE_SIZE, page_size);
610 return -ENODEV;
611 }
612
613
614 attr = &dev->attr;
615 attr->vendor_id = qed_attr->vendor_id;
616 attr->vendor_part_id = qed_attr->vendor_part_id;
617 attr->hw_ver = qed_attr->hw_ver;
618 attr->fw_ver = qed_attr->fw_ver;
619 attr->node_guid = qed_attr->node_guid;
620 attr->sys_image_guid = qed_attr->sys_image_guid;
621 attr->max_cnq = qed_attr->max_cnq;
622 attr->max_sge = qed_attr->max_sge;
623 attr->max_inline = qed_attr->max_inline;
624 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
625 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
626 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
627 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
628 attr->max_dev_resp_rd_atomic_resc =
629 qed_attr->max_dev_resp_rd_atomic_resc;
630 attr->max_cq = qed_attr->max_cq;
631 attr->max_qp = qed_attr->max_qp;
632 attr->max_mr = qed_attr->max_mr;
633 attr->max_mr_size = qed_attr->max_mr_size;
634 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
635 attr->max_mw = qed_attr->max_mw;
636 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
637 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
638 attr->max_pd = qed_attr->max_pd;
639 attr->max_ah = qed_attr->max_ah;
640 attr->max_pkey = qed_attr->max_pkey;
641 attr->max_srq = qed_attr->max_srq;
642 attr->max_srq_wr = qed_attr->max_srq_wr;
643 attr->dev_caps = qed_attr->dev_caps;
644 attr->page_size_caps = qed_attr->page_size_caps;
645 attr->dev_ack_delay = qed_attr->dev_ack_delay;
646 attr->reserved_lkey = qed_attr->reserved_lkey;
647 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
648 attr->max_stats_queues = qed_attr->max_stats_queues;
649
650 return 0;
651}
652
653static void qedr_unaffiliated_event(void *context, u8 event_code)
654{
655 pr_err("unaffiliated event not implemented yet\n");
656}
657
658static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
659{
660#define EVENT_TYPE_NOT_DEFINED 0
661#define EVENT_TYPE_CQ 1
662#define EVENT_TYPE_QP 2
663#define EVENT_TYPE_SRQ 3
664 struct qedr_dev *dev = (struct qedr_dev *)context;
665 struct regpair *async_handle = (struct regpair *)fw_handle;
666 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
667 u8 event_type = EVENT_TYPE_NOT_DEFINED;
668 struct ib_event event;
669 struct ib_srq *ibsrq;
670 struct qedr_srq *srq;
671 unsigned long flags;
672 struct ib_cq *ibcq;
673 struct ib_qp *ibqp;
674 struct qedr_cq *cq;
675 struct qedr_qp *qp;
676 u16 srq_id;
677
678 if (IS_ROCE(dev)) {
679 switch (e_code) {
680 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
681 event.event = IB_EVENT_CQ_ERR;
682 event_type = EVENT_TYPE_CQ;
683 break;
684 case ROCE_ASYNC_EVENT_SQ_DRAINED:
685 event.event = IB_EVENT_SQ_DRAINED;
686 event_type = EVENT_TYPE_QP;
687 break;
688 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
689 event.event = IB_EVENT_QP_FATAL;
690 event_type = EVENT_TYPE_QP;
691 break;
692 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
693 event.event = IB_EVENT_QP_REQ_ERR;
694 event_type = EVENT_TYPE_QP;
695 break;
696 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
697 event.event = IB_EVENT_QP_ACCESS_ERR;
698 event_type = EVENT_TYPE_QP;
699 break;
700 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
701 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
702 event_type = EVENT_TYPE_SRQ;
703 break;
704 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
705 event.event = IB_EVENT_SRQ_ERR;
706 event_type = EVENT_TYPE_SRQ;
707 break;
708 default:
709 DP_ERR(dev, "unsupported event %d on handle=%llx\n",
710 e_code, roce_handle64);
711 }
712 } else {
713 switch (e_code) {
714 case QED_IWARP_EVENT_SRQ_LIMIT:
715 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
716 event_type = EVENT_TYPE_SRQ;
717 break;
718 case QED_IWARP_EVENT_SRQ_EMPTY:
719 event.event = IB_EVENT_SRQ_ERR;
720 event_type = EVENT_TYPE_SRQ;
721 break;
722 default:
723 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
724 roce_handle64);
725 }
726 }
727 switch (event_type) {
728 case EVENT_TYPE_CQ:
729 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
730 if (cq) {
731 ibcq = &cq->ibcq;
732 if (ibcq->event_handler) {
733 event.device = ibcq->device;
734 event.element.cq = ibcq;
735 ibcq->event_handler(&event, ibcq->cq_context);
736 }
737 } else {
738 WARN(1,
739 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
740 roce_handle64);
741 }
742 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
743 break;
744 case EVENT_TYPE_QP:
745 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
746 if (qp) {
747 ibqp = &qp->ibqp;
748 if (ibqp->event_handler) {
749 event.device = ibqp->device;
750 event.element.qp = ibqp;
751 ibqp->event_handler(&event, ibqp->qp_context);
752 }
753 } else {
754 WARN(1,
755 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
756 roce_handle64);
757 }
758 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
759 break;
760 case EVENT_TYPE_SRQ:
761 srq_id = (u16)roce_handle64;
762 xa_lock_irqsave(&dev->srqs, flags);
763 srq = xa_load(&dev->srqs, srq_id);
764 if (srq) {
765 ibsrq = &srq->ibsrq;
766 if (ibsrq->event_handler) {
767 event.device = ibsrq->device;
768 event.element.srq = ibsrq;
769 ibsrq->event_handler(&event,
770 ibsrq->srq_context);
771 }
772 } else {
773 DP_NOTICE(dev,
774 "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
775 roce_handle64);
776 }
777 xa_unlock_irqrestore(&dev->srqs, flags);
778 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
779 default:
780 break;
781 }
782}
783
784static int qedr_init_hw(struct qedr_dev *dev)
785{
786 struct qed_rdma_add_user_out_params out_params;
787 struct qed_rdma_start_in_params *in_params;
788 struct qed_rdma_cnq_params *cur_pbl;
789 struct qed_rdma_events events;
790 dma_addr_t p_phys_table;
791 u32 page_cnt;
792 int rc = 0;
793 int i;
794
795 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
796 if (!in_params) {
797 rc = -ENOMEM;
798 goto out;
799 }
800
801 in_params->desired_cnq = dev->num_cnq;
802 for (i = 0; i < dev->num_cnq; i++) {
803 cur_pbl = &in_params->cnq_pbl_list[i];
804
805 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
806 cur_pbl->num_pbl_pages = page_cnt;
807
808 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
809 cur_pbl->pbl_ptr = (u64)p_phys_table;
810 }
811
812 events.affiliated_event = qedr_affiliated_event;
813 events.unaffiliated_event = qedr_unaffiliated_event;
814 events.context = dev;
815
816 in_params->events = &events;
817 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
818 in_params->max_mtu = dev->ndev->mtu;
819 dev->iwarp_max_mtu = dev->ndev->mtu;
820 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
821
822 rc = dev->ops->rdma_init(dev->cdev, in_params);
823 if (rc)
824 goto out;
825
826 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
827 if (rc)
828 goto out;
829
830 dev->db_addr = out_params.dpi_addr;
831 dev->db_phys_addr = out_params.dpi_phys_addr;
832 dev->db_size = out_params.dpi_size;
833 dev->dpi = out_params.dpi;
834
835 rc = qedr_set_device_attr(dev);
836out:
837 kfree(in_params);
838 if (rc)
839 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
840
841 return rc;
842}
843
844static void qedr_stop_hw(struct qedr_dev *dev)
845{
846 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
847 dev->ops->rdma_stop(dev->rdma_ctx);
848}
849
850static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
851 struct net_device *ndev)
852{
853 struct qed_dev_rdma_info dev_info;
854 struct qedr_dev *dev;
855 int rc = 0;
856
857 dev = ib_alloc_device(qedr_dev, ibdev);
858 if (!dev) {
859 pr_err("Unable to allocate ib device\n");
860 return NULL;
861 }
862
863 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
864
865 dev->pdev = pdev;
866 dev->ndev = ndev;
867 dev->cdev = cdev;
868
869 qed_ops = qed_get_rdma_ops();
870 if (!qed_ops) {
871 DP_ERR(dev, "Failed to get qed roce operations\n");
872 goto init_err;
873 }
874
875 dev->ops = qed_ops;
876 rc = qed_ops->fill_dev_info(cdev, &dev_info);
877 if (rc)
878 goto init_err;
879
880 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
881 dev->rdma_type = dev_info.rdma_type;
882 dev->num_hwfns = dev_info.common.num_hwfns;
883
884 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
885 rc = dev->ops->iwarp_set_engine_affin(cdev, false);
886 if (rc) {
887 DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
888 goto init_err;
889 }
890 }
891 dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
892
893 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
894
895 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
896 if (!dev->num_cnq) {
897 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
898 rc = -ENOMEM;
899 goto init_err;
900 }
901
902 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
903
904 qedr_pci_set_atomic(dev, pdev);
905
906 rc = qedr_alloc_resources(dev);
907 if (rc)
908 goto init_err;
909
910 rc = qedr_init_hw(dev);
911 if (rc)
912 goto alloc_err;
913
914 rc = qedr_setup_irqs(dev);
915 if (rc)
916 goto irq_err;
917
918 rc = qedr_register_device(dev);
919 if (rc) {
920 DP_ERR(dev, "Unable to allocate register device\n");
921 goto reg_err;
922 }
923
924 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
925 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
926
927 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
928 return dev;
929
930reg_err:
931 qedr_sync_free_irqs(dev);
932irq_err:
933 qedr_stop_hw(dev);
934alloc_err:
935 qedr_free_resources(dev);
936init_err:
937 ib_dealloc_device(&dev->ibdev);
938 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
939
940 return NULL;
941}
942
943static void qedr_remove(struct qedr_dev *dev)
944{
945
946
947
948 ib_unregister_device(&dev->ibdev);
949
950 qedr_stop_hw(dev);
951 qedr_sync_free_irqs(dev);
952 qedr_free_resources(dev);
953
954 if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
955 dev->ops->iwarp_set_engine_affin(dev->cdev, true);
956
957 ib_dealloc_device(&dev->ibdev);
958}
959
960static void qedr_close(struct qedr_dev *dev)
961{
962 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
963 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
964}
965
966static void qedr_shutdown(struct qedr_dev *dev)
967{
968 qedr_close(dev);
969 qedr_remove(dev);
970}
971
972static void qedr_open(struct qedr_dev *dev)
973{
974 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
975 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
976}
977
978static void qedr_mac_address_change(struct qedr_dev *dev)
979{
980 union ib_gid *sgid = &dev->sgid_tbl[0];
981 u8 guid[8], mac_addr[6];
982 int rc;
983
984
985 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
986 guid[0] = mac_addr[0] ^ 2;
987 guid[1] = mac_addr[1];
988 guid[2] = mac_addr[2];
989 guid[3] = 0xff;
990 guid[4] = 0xfe;
991 guid[5] = mac_addr[3];
992 guid[6] = mac_addr[4];
993 guid[7] = mac_addr[5];
994 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
995 memcpy(&sgid->raw[8], guid, sizeof(guid));
996
997
998 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
999 dev->gsi_ll2_mac_address,
1000 dev->ndev->dev_addr);
1001
1002 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
1003
1004 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
1005
1006 if (rc)
1007 DP_ERR(dev, "Error updating mac filter\n");
1008}
1009
1010
1011
1012
1013
1014static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1015{
1016 switch (event) {
1017 case QEDE_UP:
1018 qedr_open(dev);
1019 break;
1020 case QEDE_DOWN:
1021 qedr_close(dev);
1022 break;
1023 case QEDE_CLOSE:
1024 qedr_shutdown(dev);
1025 break;
1026 case QEDE_CHANGE_ADDR:
1027 qedr_mac_address_change(dev);
1028 break;
1029 default:
1030 pr_err("Event not supported\n");
1031 }
1032}
1033
1034static struct qedr_driver qedr_drv = {
1035 .name = "qedr_driver",
1036 .add = qedr_add,
1037 .remove = qedr_remove,
1038 .notify = qedr_notify,
1039};
1040
1041static int __init qedr_init_module(void)
1042{
1043 return qede_rdma_register_driver(&qedr_drv);
1044}
1045
1046static void __exit qedr_exit_module(void)
1047{
1048 qede_rdma_unregister_driver(&qedr_drv);
1049}
1050
1051module_init(qedr_init_module);
1052module_exit(qedr_exit_module);
1053
