1
2
3
4
5
6
7
8
9
10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <media/media-entity.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-subdev.h>
22
23#include "camss-ispif.h"
24#include "camss.h"
25
26#define MSM_ISPIF_NAME "msm_ispif"
27
28#define ISPIF_RST_CMD_0 0x008
29#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
30#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
31#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
32#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
33#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
34#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
35#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
36#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
37#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
38#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
39#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
40#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
41#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
42#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
43#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
44#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
45#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
46#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
47#define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
48#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
49#define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
50#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
52#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
54#define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
55#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
57#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
59#define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
60#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
62#define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
63#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
64#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
65#define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
66#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
67#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
68#define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
69#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
70#define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
71#define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
72#define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
73#define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
74#define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
75#define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
76#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
77 (0x254 + 0x200 * (m) + 0x4 * (n))
78#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
79 (0x264 + 0x200 * (m) + 0x4 * (n))
80
81#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
82 (0x270 + 0x200 * (m) + 0x4 * (n))
83#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
84 (0x27c + 0x200 * (m) + 0x4 * (n))
85#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
86 (1 << ((cid % 8) * 4))
87#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
88 (0x2c0 + 0x200 * (m) + 0x4 * (n))
89#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
90 (0x2d0 + 0x200 * (m) + 0x4 * (n))
91
92#define CSI_PIX_CLK_MUX_SEL 0x000
93#define CSI_RDI_CLK_MUX_SEL 0x008
94
95#define ISPIF_TIMEOUT_SLEEP_US 1000
96#define ISPIF_TIMEOUT_ALL_US 1000000
97#define ISPIF_RESET_TIMEOUT_MS 500
98
99enum ispif_intf_cmd {
100 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
101 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
102 CMD_DISABLE_IMMEDIATELY = 0x2,
103 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
104 CMD_ALL_NO_CHANGE = 0xffffffff,
105};
106
107static const u32 ispif_formats_8x16[] = {
108 MEDIA_BUS_FMT_UYVY8_2X8,
109 MEDIA_BUS_FMT_VYUY8_2X8,
110 MEDIA_BUS_FMT_YUYV8_2X8,
111 MEDIA_BUS_FMT_YVYU8_2X8,
112 MEDIA_BUS_FMT_SBGGR8_1X8,
113 MEDIA_BUS_FMT_SGBRG8_1X8,
114 MEDIA_BUS_FMT_SGRBG8_1X8,
115 MEDIA_BUS_FMT_SRGGB8_1X8,
116 MEDIA_BUS_FMT_SBGGR10_1X10,
117 MEDIA_BUS_FMT_SGBRG10_1X10,
118 MEDIA_BUS_FMT_SGRBG10_1X10,
119 MEDIA_BUS_FMT_SRGGB10_1X10,
120 MEDIA_BUS_FMT_SBGGR12_1X12,
121 MEDIA_BUS_FMT_SGBRG12_1X12,
122 MEDIA_BUS_FMT_SGRBG12_1X12,
123 MEDIA_BUS_FMT_SRGGB12_1X12,
124 MEDIA_BUS_FMT_Y10_1X10,
125};
126
127static const u32 ispif_formats_8x96[] = {
128 MEDIA_BUS_FMT_UYVY8_2X8,
129 MEDIA_BUS_FMT_VYUY8_2X8,
130 MEDIA_BUS_FMT_YUYV8_2X8,
131 MEDIA_BUS_FMT_YVYU8_2X8,
132 MEDIA_BUS_FMT_SBGGR8_1X8,
133 MEDIA_BUS_FMT_SGBRG8_1X8,
134 MEDIA_BUS_FMT_SGRBG8_1X8,
135 MEDIA_BUS_FMT_SRGGB8_1X8,
136 MEDIA_BUS_FMT_SBGGR10_1X10,
137 MEDIA_BUS_FMT_SGBRG10_1X10,
138 MEDIA_BUS_FMT_SGRBG10_1X10,
139 MEDIA_BUS_FMT_SRGGB10_1X10,
140 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
141 MEDIA_BUS_FMT_SBGGR12_1X12,
142 MEDIA_BUS_FMT_SGBRG12_1X12,
143 MEDIA_BUS_FMT_SGRBG12_1X12,
144 MEDIA_BUS_FMT_SRGGB12_1X12,
145 MEDIA_BUS_FMT_SBGGR14_1X14,
146 MEDIA_BUS_FMT_SGBRG14_1X14,
147 MEDIA_BUS_FMT_SGRBG14_1X14,
148 MEDIA_BUS_FMT_SRGGB14_1X14,
149 MEDIA_BUS_FMT_Y10_1X10,
150 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
151};
152
153
154
155
156
157
158
159
160static irqreturn_t ispif_isr_8x96(int irq, void *dev)
161{
162 struct ispif_device *ispif = dev;
163 u32 value0, value1, value2, value3, value4, value5;
164
165 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
166 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
167 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
168 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
169 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
170 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
171
172 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
173 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
174 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
175 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
176 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
177 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
178
179 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
180
181 if ((value0 >> 27) & 0x1)
182 complete(&ispif->reset_complete);
183
184 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
185 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
186
187 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
188 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
189
190 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
191 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
192
193 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
194 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
195
196 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
197 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
198
199 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
200 dev_err_ratelimited(to_device(ispif), "VFE1 pix0 overflow\n");
201
202 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
203 dev_err_ratelimited(to_device(ispif), "VFE1 rdi0 overflow\n");
204
205 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
206 dev_err_ratelimited(to_device(ispif), "VFE1 pix1 overflow\n");
207
208 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
209 dev_err_ratelimited(to_device(ispif), "VFE1 rdi1 overflow\n");
210
211 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
212 dev_err_ratelimited(to_device(ispif), "VFE1 rdi2 overflow\n");
213
214 return IRQ_HANDLED;
215}
216
217
218
219
220
221
222
223
224static irqreturn_t ispif_isr_8x16(int irq, void *dev)
225{
226 struct ispif_device *ispif = dev;
227 u32 value0, value1, value2;
228
229 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
230 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
231 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
232
233 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
234 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
235 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
236
237 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
238
239 if ((value0 >> 27) & 0x1)
240 complete(&ispif->reset_complete);
241
242 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
243 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
244
245 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
246 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
247
248 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
249 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
250
251 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
252 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
253
254 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
255 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
256
257 return IRQ_HANDLED;
258}
259
260
261
262
263
264
265
266static int ispif_reset(struct ispif_device *ispif)
267{
268 unsigned long time;
269 u32 val;
270 int ret;
271
272 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0);
273 if (ret < 0)
274 return ret;
275
276 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1);
277 if (ret < 0)
278 return ret;
279
280 ret = camss_enable_clocks(ispif->nclocks_for_reset,
281 ispif->clock_for_reset,
282 to_device(ispif));
283 if (ret < 0)
284 return ret;
285
286 reinit_completion(&ispif->reset_complete);
287
288 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
289 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
290 ISPIF_RST_CMD_0_SW_REG_RST |
291 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
292 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
293 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
294 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
295 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
296 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
297 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
298 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
299 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
300 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
301 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
302 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
303 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
304 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
305
306 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
307
308 time = wait_for_completion_timeout(&ispif->reset_complete,
309 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
310 if (!time) {
311 dev_err(to_device(ispif), "ISPIF reset timeout\n");
312 ret = -EIO;
313 }
314
315 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
316
317 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0);
318 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE1);
319
320 return ret;
321}
322
323
324
325
326
327
328
329
330static int ispif_set_power(struct v4l2_subdev *sd, int on)
331{
332 struct ispif_line *line = v4l2_get_subdevdata(sd);
333 struct ispif_device *ispif = line->ispif;
334 struct device *dev = to_device(ispif);
335 int ret = 0;
336
337 mutex_lock(&ispif->power_lock);
338
339 if (on) {
340 if (ispif->power_count) {
341
342 ispif->power_count++;
343 goto exit;
344 }
345
346 ret = pm_runtime_get_sync(dev);
347 if (ret < 0) {
348 pm_runtime_put_sync(dev);
349 goto exit;
350 }
351
352 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
353 if (ret < 0) {
354 pm_runtime_put_sync(dev);
355 goto exit;
356 }
357
358 ret = ispif_reset(ispif);
359 if (ret < 0) {
360 pm_runtime_put_sync(dev);
361 camss_disable_clocks(ispif->nclocks, ispif->clock);
362 goto exit;
363 }
364
365 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
366 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
367
368 ispif->power_count++;
369 } else {
370 if (ispif->power_count == 0) {
371 dev_err(dev, "ispif power off on power_count == 0\n");
372 goto exit;
373 } else if (ispif->power_count == 1) {
374 camss_disable_clocks(ispif->nclocks, ispif->clock);
375 pm_runtime_put_sync(dev);
376 }
377
378 ispif->power_count--;
379 }
380
381exit:
382 mutex_unlock(&ispif->power_lock);
383
384 return ret;
385}
386
387
388
389
390
391
392
393
394
395static void ispif_select_clk_mux(struct ispif_device *ispif,
396 enum ispif_intf intf, u8 csid,
397 u8 vfe, u8 enable)
398{
399 u32 val;
400
401 switch (intf) {
402 case PIX0:
403 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
404 val &= ~(0xf << (vfe * 8));
405 if (enable)
406 val |= (csid << (vfe * 8));
407 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
408 break;
409
410 case RDI0:
411 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
412 val &= ~(0xf << (vfe * 12));
413 if (enable)
414 val |= (csid << (vfe * 12));
415 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
416 break;
417
418 case PIX1:
419 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
420 val &= ~(0xf << (4 + (vfe * 8)));
421 if (enable)
422 val |= (csid << (4 + (vfe * 8)));
423 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
424 break;
425
426 case RDI1:
427 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
428 val &= ~(0xf << (4 + (vfe * 12)));
429 if (enable)
430 val |= (csid << (4 + (vfe * 12)));
431 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
432 break;
433
434 case RDI2:
435 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
436 val &= ~(0xf << (8 + (vfe * 12)));
437 if (enable)
438 val |= (csid << (8 + (vfe * 12)));
439 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
440 break;
441 }
442
443 mb();
444}
445
446
447
448
449
450
451
452
453
454static int ispif_validate_intf_status(struct ispif_device *ispif,
455 enum ispif_intf intf, u8 vfe)
456{
457 int ret = 0;
458 u32 val = 0;
459
460 switch (intf) {
461 case PIX0:
462 val = readl_relaxed(ispif->base +
463 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
464 break;
465 case RDI0:
466 val = readl_relaxed(ispif->base +
467 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
468 break;
469 case PIX1:
470 val = readl_relaxed(ispif->base +
471 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
472 break;
473 case RDI1:
474 val = readl_relaxed(ispif->base +
475 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
476 break;
477 case RDI2:
478 val = readl_relaxed(ispif->base +
479 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
480 break;
481 }
482
483 if ((val & 0xf) != 0xf) {
484 dev_err(to_device(ispif), "%s: ispif is busy: 0x%x\n",
485 __func__, val);
486 ret = -EBUSY;
487 }
488
489 return ret;
490}
491
492
493
494
495
496
497
498
499
500static int ispif_wait_for_stop(struct ispif_device *ispif,
501 enum ispif_intf intf, u8 vfe)
502{
503 u32 addr = 0;
504 u32 stop_flag = 0;
505 int ret;
506
507 switch (intf) {
508 case PIX0:
509 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
510 break;
511 case RDI0:
512 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
513 break;
514 case PIX1:
515 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
516 break;
517 case RDI1:
518 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
519 break;
520 case RDI2:
521 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
522 break;
523 }
524
525 ret = readl_poll_timeout(ispif->base + addr,
526 stop_flag,
527 (stop_flag & 0xf) == 0xf,
528 ISPIF_TIMEOUT_SLEEP_US,
529 ISPIF_TIMEOUT_ALL_US);
530 if (ret < 0)
531 dev_err(to_device(ispif), "%s: ispif stop timeout\n",
532 __func__);
533
534 return ret;
535}
536
537
538
539
540
541
542
543
544
545static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
546 u8 csid, u8 vfe, u8 enable)
547{
548 u32 val;
549
550 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
551 switch (intf) {
552 case PIX0:
553 val &= ~(BIT(1) | BIT(0));
554 if (enable)
555 val |= csid;
556 break;
557 case RDI0:
558 val &= ~(BIT(5) | BIT(4));
559 if (enable)
560 val |= (csid << 4);
561 break;
562 case PIX1:
563 val &= ~(BIT(9) | BIT(8));
564 if (enable)
565 val |= (csid << 8);
566 break;
567 case RDI1:
568 val &= ~(BIT(13) | BIT(12));
569 if (enable)
570 val |= (csid << 12);
571 break;
572 case RDI2:
573 val &= ~(BIT(21) | BIT(20));
574 if (enable)
575 val |= (csid << 20);
576 break;
577 }
578
579 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
580}
581
582
583
584
585
586
587
588
589
590static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
591 u8 cid, u8 vfe, u8 enable)
592{
593 u32 cid_mask = 1 << cid;
594 u32 addr = 0;
595 u32 val;
596
597 switch (intf) {
598 case PIX0:
599 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
600 break;
601 case RDI0:
602 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
603 break;
604 case PIX1:
605 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
606 break;
607 case RDI1:
608 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
609 break;
610 case RDI2:
611 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
612 break;
613 }
614
615 val = readl_relaxed(ispif->base + addr);
616 if (enable)
617 val |= cid_mask;
618 else
619 val &= ~cid_mask;
620
621 writel(val, ispif->base + addr);
622}
623
624
625
626
627
628
629
630
631static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
632 u8 vfe, u8 enable)
633{
634 u32 val;
635
636 switch (intf) {
637 case PIX0:
638 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
639 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
640 if (enable)
641 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
642 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
643 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
644 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
645 break;
646 case RDI0:
647 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
648 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
649 if (enable)
650 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
651 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
652 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
653 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
654 break;
655 case PIX1:
656 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
657 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
658 if (enable)
659 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
660 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
661 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
662 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
663 break;
664 case RDI1:
665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
666 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
667 if (enable)
668 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
670 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
672 break;
673 case RDI2:
674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
675 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
676 if (enable)
677 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
679 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
681 break;
682 }
683
684 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
685}
686
687
688
689
690
691
692
693
694
695
696static void ispif_config_pack(struct ispif_device *ispif, u32 code,
697 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
698{
699 u32 addr, val;
700
701 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
702 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
703 return;
704
705 switch (intf) {
706 case RDI0:
707 if (cid < 8)
708 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
709 else
710 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
711 break;
712 case RDI1:
713 if (cid < 8)
714 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
715 else
716 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
717 break;
718 case RDI2:
719 if (cid < 8)
720 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
721 else
722 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
723 break;
724 default:
725 return;
726 }
727
728 if (enable)
729 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
730 else
731 val = 0;
732
733 writel_relaxed(val, ispif->base + addr);
734}
735
736
737
738
739
740
741
742
743
744static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
745 enum ispif_intf intf, u8 vfe, u8 vc)
746{
747 u32 *val;
748
749 if (intf == RDI2) {
750 val = &ispif->intf_cmd[vfe].cmd_1;
751 *val &= ~(0x3 << (vc * 2 + 8));
752 *val |= (cmd << (vc * 2 + 8));
753 wmb();
754 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
755 wmb();
756 } else {
757 val = &ispif->intf_cmd[vfe].cmd_0;
758 *val &= ~(0x3 << (vc * 2 + intf * 8));
759 *val |= (cmd << (vc * 2 + intf * 8));
760 wmb();
761 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
762 wmb();
763 }
764}
765
766
767
768
769
770
771
772
773
774
775static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
776{
777 struct ispif_line *line = v4l2_get_subdevdata(sd);
778 struct ispif_device *ispif = line->ispif;
779 enum ispif_intf intf = line->interface;
780 u8 csid = line->csid_id;
781 u8 vfe = line->vfe_id;
782 u8 vc = 0;
783 u8 cid = vc * 4;
784 int ret;
785
786 if (enable) {
787 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
788 return -ENOLINK;
789
790
791
792 mutex_lock(&ispif->config_lock);
793 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
794
795 ret = ispif_validate_intf_status(ispif, intf, vfe);
796 if (ret < 0) {
797 mutex_unlock(&ispif->config_lock);
798 return ret;
799 }
800
801 ispif_select_csid(ispif, intf, csid, vfe, 1);
802 ispif_select_cid(ispif, intf, cid, vfe, 1);
803 ispif_config_irq(ispif, intf, vfe, 1);
804 if (to_camss(ispif)->version == CAMSS_8x96)
805 ispif_config_pack(ispif,
806 line->fmt[MSM_ISPIF_PAD_SINK].code,
807 intf, cid, vfe, 1);
808 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
809 intf, vfe, vc);
810 } else {
811 mutex_lock(&ispif->config_lock);
812 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
813 intf, vfe, vc);
814 mutex_unlock(&ispif->config_lock);
815
816 ret = ispif_wait_for_stop(ispif, intf, vfe);
817 if (ret < 0)
818 return ret;
819
820 mutex_lock(&ispif->config_lock);
821 if (to_camss(ispif)->version == CAMSS_8x96)
822 ispif_config_pack(ispif,
823 line->fmt[MSM_ISPIF_PAD_SINK].code,
824 intf, cid, vfe, 0);
825 ispif_config_irq(ispif, intf, vfe, 0);
826 ispif_select_cid(ispif, intf, cid, vfe, 0);
827 ispif_select_csid(ispif, intf, csid, vfe, 0);
828 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
829 }
830
831 mutex_unlock(&ispif->config_lock);
832
833 return 0;
834}
835
836
837
838
839
840
841
842
843
844
845static struct v4l2_mbus_framefmt *
846__ispif_get_format(struct ispif_line *line,
847 struct v4l2_subdev_pad_config *cfg,
848 unsigned int pad,
849 enum v4l2_subdev_format_whence which)
850{
851 if (which == V4L2_SUBDEV_FORMAT_TRY)
852 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad);
853
854 return &line->fmt[pad];
855}
856
857
858
859
860
861
862
863
864
865static void ispif_try_format(struct ispif_line *line,
866 struct v4l2_subdev_pad_config *cfg,
867 unsigned int pad,
868 struct v4l2_mbus_framefmt *fmt,
869 enum v4l2_subdev_format_whence which)
870{
871 unsigned int i;
872
873 switch (pad) {
874 case MSM_ISPIF_PAD_SINK:
875
876
877 for (i = 0; i < line->nformats; i++)
878 if (fmt->code == line->formats[i])
879 break;
880
881
882 if (i >= line->nformats)
883 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
884
885 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
886 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
887
888 fmt->field = V4L2_FIELD_NONE;
889 fmt->colorspace = V4L2_COLORSPACE_SRGB;
890
891 break;
892
893 case MSM_ISPIF_PAD_SRC:
894
895
896 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
897 which);
898
899 break;
900 }
901
902 fmt->colorspace = V4L2_COLORSPACE_SRGB;
903}
904
905
906
907
908
909
910
911
912static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
913 struct v4l2_subdev_pad_config *cfg,
914 struct v4l2_subdev_mbus_code_enum *code)
915{
916 struct ispif_line *line = v4l2_get_subdevdata(sd);
917 struct v4l2_mbus_framefmt *format;
918
919 if (code->pad == MSM_ISPIF_PAD_SINK) {
920 if (code->index >= line->nformats)
921 return -EINVAL;
922
923 code->code = line->formats[code->index];
924 } else {
925 if (code->index > 0)
926 return -EINVAL;
927
928 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
929 code->which);
930
931 code->code = format->code;
932 }
933
934 return 0;
935}
936
937
938
939
940
941
942
943
944static int ispif_enum_frame_size(struct v4l2_subdev *sd,
945 struct v4l2_subdev_pad_config *cfg,
946 struct v4l2_subdev_frame_size_enum *fse)
947{
948 struct ispif_line *line = v4l2_get_subdevdata(sd);
949 struct v4l2_mbus_framefmt format;
950
951 if (fse->index != 0)
952 return -EINVAL;
953
954 format.code = fse->code;
955 format.width = 1;
956 format.height = 1;
957 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
958 fse->min_width = format.width;
959 fse->min_height = format.height;
960
961 if (format.code != fse->code)
962 return -EINVAL;
963
964 format.code = fse->code;
965 format.width = -1;
966 format.height = -1;
967 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
968 fse->max_width = format.width;
969 fse->max_height = format.height;
970
971 return 0;
972}
973
974
975
976
977
978
979
980
981
982static int ispif_get_format(struct v4l2_subdev *sd,
983 struct v4l2_subdev_pad_config *cfg,
984 struct v4l2_subdev_format *fmt)
985{
986 struct ispif_line *line = v4l2_get_subdevdata(sd);
987 struct v4l2_mbus_framefmt *format;
988
989 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
990 if (format == NULL)
991 return -EINVAL;
992
993 fmt->format = *format;
994
995 return 0;
996}
997
998
999
1000
1001
1002
1003
1004
1005
1006static int ispif_set_format(struct v4l2_subdev *sd,
1007 struct v4l2_subdev_pad_config *cfg,
1008 struct v4l2_subdev_format *fmt)
1009{
1010 struct ispif_line *line = v4l2_get_subdevdata(sd);
1011 struct v4l2_mbus_framefmt *format;
1012
1013 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
1014 if (format == NULL)
1015 return -EINVAL;
1016
1017 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which);
1018 *format = fmt->format;
1019
1020
1021 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1022 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC,
1023 fmt->which);
1024
1025 *format = fmt->format;
1026 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format,
1027 fmt->which);
1028 }
1029
1030 return 0;
1031}
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1043{
1044 struct v4l2_subdev_format format = {
1045 .pad = MSM_ISPIF_PAD_SINK,
1046 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1047 V4L2_SUBDEV_FORMAT_ACTIVE,
1048 .format = {
1049 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1050 .width = 1920,
1051 .height = 1080
1052 }
1053 };
1054
1055 return ispif_set_format(sd, fh ? fh->pad : NULL, &format);
1056}
1057
1058
1059
1060
1061
1062
1063
1064
1065int msm_ispif_subdev_init(struct ispif_device *ispif,
1066 const struct resources_ispif *res)
1067{
1068 struct device *dev = to_device(ispif);
1069 struct platform_device *pdev = to_platform_device(dev);
1070 struct resource *r;
1071 int i;
1072 int ret;
1073
1074
1075 if (to_camss(ispif)->version == CAMSS_8x16)
1076 ispif->line_num = 2;
1077 else if (to_camss(ispif)->version == CAMSS_8x96)
1078 ispif->line_num = 4;
1079 else
1080 return -EINVAL;
1081
1082 ispif->line = devm_kcalloc(dev, ispif->line_num, sizeof(*ispif->line),
1083 GFP_KERNEL);
1084 if (!ispif->line)
1085 return -ENOMEM;
1086
1087 for (i = 0; i < ispif->line_num; i++) {
1088 ispif->line[i].ispif = ispif;
1089 ispif->line[i].id = i;
1090
1091 if (to_camss(ispif)->version == CAMSS_8x16) {
1092 ispif->line[i].formats = ispif_formats_8x16;
1093 ispif->line[i].nformats =
1094 ARRAY_SIZE(ispif_formats_8x16);
1095 } else if (to_camss(ispif)->version == CAMSS_8x96) {
1096 ispif->line[i].formats = ispif_formats_8x96;
1097 ispif->line[i].nformats =
1098 ARRAY_SIZE(ispif_formats_8x96);
1099 } else {
1100 return -EINVAL;
1101 }
1102 }
1103
1104
1105
1106 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
1107 ispif->base = devm_ioremap_resource(dev, r);
1108 if (IS_ERR(ispif->base)) {
1109 dev_err(dev, "could not map memory\n");
1110 return PTR_ERR(ispif->base);
1111 }
1112
1113 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
1114 ispif->base_clk_mux = devm_ioremap_resource(dev, r);
1115 if (IS_ERR(ispif->base_clk_mux)) {
1116 dev_err(dev, "could not map memory\n");
1117 return PTR_ERR(ispif->base_clk_mux);
1118 }
1119
1120
1121
1122 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
1123
1124 if (!r) {
1125 dev_err(dev, "missing IRQ\n");
1126 return -EINVAL;
1127 }
1128
1129 ispif->irq = r->start;
1130 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1131 dev_name(dev), MSM_ISPIF_NAME);
1132 if (to_camss(ispif)->version == CAMSS_8x16)
1133 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1134 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1135 else if (to_camss(ispif)->version == CAMSS_8x96)
1136 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1137 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1138 else
1139 ret = -EINVAL;
1140 if (ret < 0) {
1141 dev_err(dev, "request_irq failed: %d\n", ret);
1142 return ret;
1143 }
1144
1145
1146
1147 ispif->nclocks = 0;
1148 while (res->clock[ispif->nclocks])
1149 ispif->nclocks++;
1150
1151 ispif->clock = devm_kcalloc(dev,
1152 ispif->nclocks, sizeof(*ispif->clock),
1153 GFP_KERNEL);
1154 if (!ispif->clock)
1155 return -ENOMEM;
1156
1157 for (i = 0; i < ispif->nclocks; i++) {
1158 struct camss_clock *clock = &ispif->clock[i];
1159
1160 clock->clk = devm_clk_get(dev, res->clock[i]);
1161 if (IS_ERR(clock->clk))
1162 return PTR_ERR(clock->clk);
1163
1164 clock->freq = NULL;
1165 clock->nfreqs = 0;
1166 }
1167
1168 ispif->nclocks_for_reset = 0;
1169 while (res->clock_for_reset[ispif->nclocks_for_reset])
1170 ispif->nclocks_for_reset++;
1171
1172 ispif->clock_for_reset = devm_kcalloc(dev,
1173 ispif->nclocks_for_reset,
1174 sizeof(*ispif->clock_for_reset),
1175 GFP_KERNEL);
1176 if (!ispif->clock_for_reset)
1177 return -ENOMEM;
1178
1179 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1180 struct camss_clock *clock = &ispif->clock_for_reset[i];
1181
1182 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1183 if (IS_ERR(clock->clk))
1184 return PTR_ERR(clock->clk);
1185
1186 clock->freq = NULL;
1187 clock->nfreqs = 0;
1188 }
1189
1190 mutex_init(&ispif->power_lock);
1191 ispif->power_count = 0;
1192
1193 mutex_init(&ispif->config_lock);
1194
1195 init_completion(&ispif->reset_complete);
1196
1197 return 0;
1198}
1199
1200
1201
1202
1203
1204
1205
1206static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1207{
1208 switch (line_id) {
1209 case (VFE_LINE_RDI0):
1210 return RDI0;
1211 case (VFE_LINE_RDI1):
1212 return RDI1;
1213 case (VFE_LINE_RDI2):
1214 return RDI2;
1215 case (VFE_LINE_PIX):
1216 return PIX0;
1217 default:
1218 return RDI0;
1219 }
1220}
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231static int ispif_link_setup(struct media_entity *entity,
1232 const struct media_pad *local,
1233 const struct media_pad *remote, u32 flags)
1234{
1235 if (flags & MEDIA_LNK_FL_ENABLED) {
1236 if (media_entity_remote_pad(local))
1237 return -EBUSY;
1238
1239 if (local->flags & MEDIA_PAD_FL_SINK) {
1240 struct v4l2_subdev *sd;
1241 struct ispif_line *line;
1242
1243 sd = media_entity_to_v4l2_subdev(entity);
1244 line = v4l2_get_subdevdata(sd);
1245
1246 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1247 } else {
1248 struct v4l2_subdev *sd;
1249 struct ispif_line *line;
1250 enum vfe_line_id id;
1251
1252 sd = media_entity_to_v4l2_subdev(entity);
1253 line = v4l2_get_subdevdata(sd);
1254
1255 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1256 msm_vfe_get_vfe_line_id(remote->entity, &id);
1257 line->interface = ispif_get_intf(id);
1258 }
1259 }
1260
1261 return 0;
1262}
1263
1264static const struct v4l2_subdev_core_ops ispif_core_ops = {
1265 .s_power = ispif_set_power,
1266};
1267
1268static const struct v4l2_subdev_video_ops ispif_video_ops = {
1269 .s_stream = ispif_set_stream,
1270};
1271
1272static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1273 .enum_mbus_code = ispif_enum_mbus_code,
1274 .enum_frame_size = ispif_enum_frame_size,
1275 .get_fmt = ispif_get_format,
1276 .set_fmt = ispif_set_format,
1277};
1278
1279static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1280 .core = &ispif_core_ops,
1281 .video = &ispif_video_ops,
1282 .pad = &ispif_pad_ops,
1283};
1284
1285static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1286 .open = ispif_init_formats,
1287};
1288
1289static const struct media_entity_operations ispif_media_ops = {
1290 .link_setup = ispif_link_setup,
1291 .link_validate = v4l2_subdev_link_validate,
1292};
1293
1294
1295
1296
1297
1298
1299
1300
1301int msm_ispif_register_entities(struct ispif_device *ispif,
1302 struct v4l2_device *v4l2_dev)
1303{
1304 struct device *dev = to_device(ispif);
1305 int ret;
1306 int i;
1307
1308 for (i = 0; i < ispif->line_num; i++) {
1309 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1310 struct media_pad *pads = ispif->line[i].pads;
1311
1312 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1313 sd->internal_ops = &ispif_v4l2_internal_ops;
1314 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1315 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1316 MSM_ISPIF_NAME, i);
1317 v4l2_set_subdevdata(sd, &ispif->line[i]);
1318
1319 ret = ispif_init_formats(sd, NULL);
1320 if (ret < 0) {
1321 dev_err(dev, "Failed to init format: %d\n", ret);
1322 goto error;
1323 }
1324
1325 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1326 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1327
1328 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1329 sd->entity.ops = &ispif_media_ops;
1330 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1331 pads);
1332 if (ret < 0) {
1333 dev_err(dev, "Failed to init media entity: %d\n", ret);
1334 goto error;
1335 }
1336
1337 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1338 if (ret < 0) {
1339 dev_err(dev, "Failed to register subdev: %d\n", ret);
1340 media_entity_cleanup(&sd->entity);
1341 goto error;
1342 }
1343 }
1344
1345 return 0;
1346
1347error:
1348 for (i--; i >= 0; i--) {
1349 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1350
1351 v4l2_device_unregister_subdev(sd);
1352 media_entity_cleanup(&sd->entity);
1353 }
1354
1355 return ret;
1356}
1357
1358
1359
1360
1361
1362void msm_ispif_unregister_entities(struct ispif_device *ispif)
1363{
1364 int i;
1365
1366 mutex_destroy(&ispif->power_lock);
1367 mutex_destroy(&ispif->config_lock);
1368
1369 for (i = 0; i < ispif->line_num; i++) {
1370 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1371
1372 v4l2_device_unregister_subdev(sd);
1373 media_entity_cleanup(&sd->entity);
1374 }
1375}
1376
