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11#include <linux/mfd/syscon/atmel-smc.h>
12#include <linux/string.h>
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20void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
21{
22 memset(conf, 0, sizeof(*conf));
23}
24EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
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43static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
44 unsigned int msbpos,
45 unsigned int msbwidth,
46 unsigned int msbfactor,
47 unsigned int *encodedval)
48{
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0);
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0);
51 unsigned int msb, lsb;
52 int ret = 0;
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54 msb = ncycles / msbfactor;
55 lsb = ncycles % msbfactor;
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57 if (lsb > lsbmask) {
58 lsb = 0;
59 msb++;
60 }
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67 if (msb > msbmask) {
68 msb = msbmask;
69 lsb = lsbmask;
70 ret = -ERANGE;
71 }
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73 *encodedval = (msb << msbpos) | lsb;
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75 return ret;
76}
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93int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
94 unsigned int shift, unsigned int ncycles)
95{
96 unsigned int val;
97 int ret;
98
99 if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT &&
100 shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT &&
101 shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT &&
102 shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT &&
103 shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT)
104 return -EINVAL;
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112 ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val);
113 conf->timings &= ~GENMASK(shift + 3, shift);
114 conf->timings |= val << shift;
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116 return ret;
117}
118EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing);
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135int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
136 unsigned int shift, unsigned int ncycles)
137{
138 unsigned int val;
139 int ret;
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141 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
142 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
143 return -EINVAL;
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151 ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val);
152 conf->setup &= ~GENMASK(shift + 7, shift);
153 conf->setup |= val << shift;
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155 return ret;
156}
157EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup);
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174int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
175 unsigned int shift, unsigned int ncycles)
176{
177 unsigned int val;
178 int ret;
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180 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT &&
181 shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT)
182 return -EINVAL;
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190 ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val);
191 conf->pulse &= ~GENMASK(shift + 7, shift);
192 conf->pulse |= val << shift;
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194 return ret;
195}
196EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse);
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213int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
214 unsigned int shift, unsigned int ncycles)
215{
216 unsigned int val;
217 int ret;
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219 if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT)
220 return -EINVAL;
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228 ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val);
229 conf->cycle &= ~GENMASK(shift + 15, shift);
230 conf->cycle |= val << shift;
231
232 return ret;
233}
234EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle);
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245void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
246 const struct atmel_smc_cs_conf *conf)
247{
248 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup);
249 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse);
250 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle);
251 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode);
252}
253EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply);
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265void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
266 const struct atmel_hsmc_reg_layout *layout,
267 int cs, const struct atmel_smc_cs_conf *conf)
268{
269 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup);
270 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse);
271 regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle);
272 regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings);
273 regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode);
274}
275EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply);
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286void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
287 struct atmel_smc_cs_conf *conf)
288{
289 regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup);
290 regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse);
291 regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle);
292 regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode);
293}
294EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get);
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306void atmel_hsmc_cs_conf_get(struct regmap *regmap,
307 const struct atmel_hsmc_reg_layout *layout,
308 int cs, struct atmel_smc_cs_conf *conf)
309{
310 regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup);
311 regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse);
312 regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle);
313 regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings);
314 regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode);
315}
316EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get);
317
318static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = {
319 .timing_regs_offset = 0x600,
320};
321
322static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = {
323 .timing_regs_offset = 0x700,
324};
325
326static const struct of_device_id atmel_smc_ids[] = {
327 { .compatible = "atmel,at91sam9260-smc", .data = NULL },
328 { .compatible = "atmel,sama5d3-smc", .data = &sama5d3_reg_layout },
329 { .compatible = "atmel,sama5d2-smc", .data = &sama5d2_reg_layout },
330 { },
331};
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342const struct atmel_hsmc_reg_layout *
343atmel_hsmc_get_reg_layout(struct device_node *np)
344{
345 const struct of_device_id *match;
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347 match = of_match_node(atmel_smc_ids, np);
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349 return match ? match->data : ERR_PTR(-EINVAL);
350}
351EXPORT_SYMBOL_GPL(atmel_hsmc_get_reg_layout);
352