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8#include <linux/init.h>
9#include <linux/export.h>
10#include <linux/module.h>
11#include <linux/device.h>
12#include <linux/platform_device.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/dma-mapping.h>
16#include <linux/compiler.h>
17#include <linux/stddef.h>
18#include <linux/bitops.h>
19#include <linux/types.h>
20#include <linux/err.h>
21#include <linux/interrupt.h>
22#include <linux/acpi.h>
23#include <linux/pm.h>
24#include <linux/pm_runtime.h>
25#include <linux/delay.h>
26#include <linux/dmi.h>
27
28#include <linux/mmc/host.h>
29#include <linux/mmc/pm.h>
30#include <linux/mmc/slot-gpio.h>
31
32#ifdef CONFIG_X86
33#include <asm/cpu_device_id.h>
34#include <asm/intel-family.h>
35#include <asm/iosf_mbi.h>
36#include <linux/pci.h>
37#endif
38
39#include "sdhci.h"
40
41enum {
42 SDHCI_ACPI_SD_CD = BIT(0),
43 SDHCI_ACPI_RUNTIME_PM = BIT(1),
44 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
45};
46
47struct sdhci_acpi_chip {
48 const struct sdhci_ops *ops;
49 unsigned int quirks;
50 unsigned int quirks2;
51 unsigned long caps;
52 unsigned int caps2;
53 mmc_pm_flag_t pm_caps;
54};
55
56struct sdhci_acpi_slot {
57 const struct sdhci_acpi_chip *chip;
58 unsigned int quirks;
59 unsigned int quirks2;
60 unsigned long caps;
61 unsigned int caps2;
62 mmc_pm_flag_t pm_caps;
63 unsigned int flags;
64 size_t priv_size;
65 int (*probe_slot)(struct platform_device *, struct acpi_device *);
66 int (*remove_slot)(struct platform_device *);
67 int (*free_slot)(struct platform_device *pdev);
68 int (*setup_host)(struct platform_device *pdev);
69};
70
71struct sdhci_acpi_host {
72 struct sdhci_host *host;
73 const struct sdhci_acpi_slot *slot;
74 struct platform_device *pdev;
75 bool use_runtime_pm;
76 bool is_intel;
77 bool reset_signal_volt_on_suspend;
78 unsigned long private[] ____cacheline_aligned;
79};
80
81enum {
82 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
83 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
84};
85
86static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
87{
88 return (void *)c->private;
89}
90
91static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
92{
93 return c->slot && (c->slot->flags & flag);
94}
95
96#define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
97#define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
98#define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
99#define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
100
101enum {
102 INTEL_DSM_FNS = 0,
103 INTEL_DSM_V18_SWITCH = 3,
104 INTEL_DSM_V33_SWITCH = 4,
105 INTEL_DSM_HS_CAPS = 8,
106};
107
108struct intel_host {
109 u32 dsm_fns;
110 u32 hs_caps;
111};
112
113static const guid_t intel_dsm_guid =
114 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
115 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
116
117static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
118 unsigned int fn, u32 *result)
119{
120 union acpi_object *obj;
121 int err = 0;
122
123 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
124 if (!obj)
125 return -EOPNOTSUPP;
126
127 if (obj->type == ACPI_TYPE_INTEGER) {
128 *result = obj->integer.value;
129 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
130 size_t len = min_t(size_t, obj->buffer.length, 4);
131
132 *result = 0;
133 memcpy(result, obj->buffer.pointer, len);
134 } else {
135 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
136 __func__, fn, obj->type, obj->buffer.length);
137 err = -EINVAL;
138 }
139
140 ACPI_FREE(obj);
141
142 return err;
143}
144
145static int intel_dsm(struct intel_host *intel_host, struct device *dev,
146 unsigned int fn, u32 *result)
147{
148 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
149 return -EOPNOTSUPP;
150
151 return __intel_dsm(intel_host, dev, fn, result);
152}
153
154static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
155 struct mmc_host *mmc)
156{
157 int err;
158
159 intel_host->hs_caps = ~0;
160
161 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
162 if (err) {
163 pr_debug("%s: DSM not supported, error %d\n",
164 mmc_hostname(mmc), err);
165 return;
166 }
167
168 pr_debug("%s: DSM function mask %#x\n",
169 mmc_hostname(mmc), intel_host->dsm_fns);
170
171 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
172}
173
174static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
175 struct mmc_ios *ios)
176{
177 struct device *dev = mmc_dev(mmc);
178 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
179 struct intel_host *intel_host = sdhci_acpi_priv(c);
180 unsigned int fn;
181 u32 result = 0;
182 int err;
183
184 err = sdhci_start_signal_voltage_switch(mmc, ios);
185 if (err)
186 return err;
187
188 switch (ios->signal_voltage) {
189 case MMC_SIGNAL_VOLTAGE_330:
190 fn = INTEL_DSM_V33_SWITCH;
191 break;
192 case MMC_SIGNAL_VOLTAGE_180:
193 fn = INTEL_DSM_V18_SWITCH;
194 break;
195 default:
196 return 0;
197 }
198
199 err = intel_dsm(intel_host, dev, fn, &result);
200 pr_debug("%s: %s DSM fn %u error %d result %u\n",
201 mmc_hostname(mmc), __func__, fn, err, result);
202
203 return 0;
204}
205
206static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
207{
208 u8 reg;
209
210 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
211 reg |= 0x10;
212 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
213
214 udelay(9);
215 reg &= ~0x10;
216 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
217
218 usleep_range(300, 1000);
219}
220
221static const struct sdhci_ops sdhci_acpi_ops_dflt = {
222 .set_clock = sdhci_set_clock,
223 .set_bus_width = sdhci_set_bus_width,
224 .reset = sdhci_reset,
225 .set_uhs_signaling = sdhci_set_uhs_signaling,
226};
227
228static const struct sdhci_ops sdhci_acpi_ops_int = {
229 .set_clock = sdhci_set_clock,
230 .set_bus_width = sdhci_set_bus_width,
231 .reset = sdhci_reset,
232 .set_uhs_signaling = sdhci_set_uhs_signaling,
233 .hw_reset = sdhci_acpi_int_hw_reset,
234};
235
236static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
237 .ops = &sdhci_acpi_ops_int,
238};
239
240#ifdef CONFIG_X86
241
242static bool sdhci_acpi_byt(void)
243{
244 static const struct x86_cpu_id byt[] = {
245 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
246 {}
247 };
248
249 return x86_match_cpu(byt);
250}
251
252static bool sdhci_acpi_cht(void)
253{
254 static const struct x86_cpu_id cht[] = {
255 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
256 {}
257 };
258
259 return x86_match_cpu(cht);
260}
261
262#define BYT_IOSF_SCCEP 0x63
263#define BYT_IOSF_OCP_NETCTRL0 0x1078
264#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
265
266static void sdhci_acpi_byt_setting(struct device *dev)
267{
268 u32 val = 0;
269
270 if (!sdhci_acpi_byt())
271 return;
272
273 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
274 &val)) {
275 dev_err(dev, "%s read error\n", __func__);
276 return;
277 }
278
279 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
280 return;
281
282 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
283
284 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
285 val)) {
286 dev_err(dev, "%s write error\n", __func__);
287 return;
288 }
289
290 dev_dbg(dev, "%s completed\n", __func__);
291}
292
293static bool sdhci_acpi_byt_defer(struct device *dev)
294{
295 if (!sdhci_acpi_byt())
296 return false;
297
298 if (!iosf_mbi_available())
299 return true;
300
301 sdhci_acpi_byt_setting(dev);
302
303 return false;
304}
305
306static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
307 unsigned int slot, unsigned int parent_slot)
308{
309 struct pci_dev *dev, *parent, *from = NULL;
310
311 while (1) {
312 dev = pci_get_device(vendor, device, from);
313 pci_dev_put(from);
314 if (!dev)
315 break;
316 parent = pci_upstream_bridge(dev);
317 if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
318 parent && PCI_SLOT(parent->devfn) == parent_slot &&
319 !pci_upstream_bridge(parent)) {
320 pci_dev_put(dev);
321 return true;
322 }
323 from = dev;
324 }
325
326 return false;
327}
328
329
330
331
332
333
334
335
336static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
337{
338 return sdhci_acpi_cht() &&
339 acpi_dev_hid_uid_match(adev, "80860F14", "2") &&
340 sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
341}
342
343#else
344
345static inline void sdhci_acpi_byt_setting(struct device *dev)
346{
347}
348
349static inline bool sdhci_acpi_byt_defer(struct device *dev)
350{
351 return false;
352}
353
354static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
355{
356 return false;
357}
358
359#endif
360
361static int bxt_get_cd(struct mmc_host *mmc)
362{
363 int gpio_cd = mmc_gpio_get_cd(mmc);
364 struct sdhci_host *host = mmc_priv(mmc);
365 unsigned long flags;
366 int ret = 0;
367
368 if (!gpio_cd)
369 return 0;
370
371 spin_lock_irqsave(&host->lock, flags);
372
373 if (host->flags & SDHCI_DEVICE_DEAD)
374 goto out;
375
376 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
377out:
378 spin_unlock_irqrestore(&host->lock, flags);
379
380 return ret;
381}
382
383static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
384{
385 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
386 struct intel_host *intel_host = sdhci_acpi_priv(c);
387 struct sdhci_host *host = c->host;
388
389 if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
390 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
391 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
392 host->timeout_clk = 1000;
393
394 if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
395 host->mmc_host_ops.get_cd = bxt_get_cd;
396
397 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
398
399 host->mmc_host_ops.start_signal_voltage_switch =
400 intel_start_signal_voltage_switch;
401
402 c->is_intel = true;
403
404 return 0;
405}
406
407static int intel_setup_host(struct platform_device *pdev)
408{
409 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
410 struct intel_host *intel_host = sdhci_acpi_priv(c);
411
412 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
413 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
414
415 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
416 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
417
418 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
419 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
420
421 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
422 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
423
424 return 0;
425}
426
427static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
428 .chip = &sdhci_acpi_chip_int,
429 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
430 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
431 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
432 .flags = SDHCI_ACPI_RUNTIME_PM,
433 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
434 SDHCI_QUIRK_NO_LED,
435 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
436 SDHCI_QUIRK2_STOP_WITH_TC |
437 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
438 .probe_slot = intel_probe_slot,
439 .setup_host = intel_setup_host,
440 .priv_size = sizeof(struct intel_host),
441};
442
443static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
444 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
445 SDHCI_QUIRK_NO_LED |
446 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
447 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
448 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
449 MMC_CAP_WAIT_WHILE_BUSY,
450 .flags = SDHCI_ACPI_RUNTIME_PM,
451 .pm_caps = MMC_PM_KEEP_POWER,
452 .probe_slot = intel_probe_slot,
453 .setup_host = intel_setup_host,
454 .priv_size = sizeof(struct intel_host),
455};
456
457static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
458 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
459 SDHCI_ACPI_RUNTIME_PM,
460 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
461 SDHCI_QUIRK_NO_LED,
462 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
463 SDHCI_QUIRK2_STOP_WITH_TC,
464 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
465 .probe_slot = intel_probe_slot,
466 .setup_host = intel_setup_host,
467 .priv_size = sizeof(struct intel_host),
468};
469
470#define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
471#define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
472static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
473{
474 struct sdhci_host *host = ptr;
475
476 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
477 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
478
479 return IRQ_HANDLED;
480}
481
482static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
483{
484 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
485 struct sdhci_host *host = c->host;
486 int *irq = sdhci_acpi_priv(c);
487
488 *irq = -EINVAL;
489
490 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
491 return 0;
492
493 *irq = platform_get_irq(pdev, 1);
494 if (*irq < 0)
495 return 0;
496
497 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
498 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
499 "sdhci_qcom", host);
500}
501
502static int qcom_free_slot(struct platform_device *pdev)
503{
504 struct device *dev = &pdev->dev;
505 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
506 struct sdhci_host *host = c->host;
507 struct acpi_device *adev;
508 int *irq = sdhci_acpi_priv(c);
509
510 adev = ACPI_COMPANION(dev);
511 if (!adev)
512 return -ENODEV;
513
514 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
515 return 0;
516
517 if (*irq < 0)
518 return 0;
519
520 free_irq(*irq, host);
521 return 0;
522}
523
524static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
525 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
526 .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
527 .caps = MMC_CAP_NONREMOVABLE,
528 .priv_size = sizeof(int),
529 .probe_slot = qcom_probe_slot,
530 .free_slot = qcom_free_slot,
531};
532
533static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
534 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
535 .caps = MMC_CAP_NONREMOVABLE,
536};
537
538struct amd_sdhci_host {
539 bool tuned_clock;
540 bool dll_enabled;
541};
542
543
544#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
545
546static int amd_select_drive_strength(struct mmc_card *card,
547 unsigned int max_dtr, int host_drv,
548 int card_drv, int *drv_type)
549{
550 *drv_type = MMC_SET_DRIVER_TYPE_A;
551 return MMC_SET_DRIVER_TYPE_A;
552}
553
554static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
555{
556 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
557 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
558
559
560 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
561 usleep_range(10, 20);
562 if (enable)
563 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
564
565 amd_host->dll_enabled = enable;
566}
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
582{
583 struct sdhci_host *host = mmc_priv(mmc);
584 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
585 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
586 unsigned int old_timing = host->timing;
587 u16 val;
588
589 sdhci_set_ios(mmc, ios);
590
591 if (old_timing != host->timing && amd_host->tuned_clock) {
592 if (host->timing == MMC_TIMING_MMC_HS400 ||
593 host->timing == MMC_TIMING_MMC_HS200) {
594 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
595 val |= SDHCI_CTRL_TUNED_CLK;
596 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
597 } else {
598 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
599 val &= ~SDHCI_CTRL_TUNED_CLK;
600 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
601 }
602
603
604 if (host->timing == MMC_TIMING_MMC_HS400 &&
605 !amd_host->dll_enabled)
606 sdhci_acpi_amd_hs400_dll(host, true);
607 }
608}
609
610static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
611{
612 int err;
613 struct sdhci_host *host = mmc_priv(mmc);
614 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
615 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
616
617 amd_host->tuned_clock = false;
618
619 err = sdhci_execute_tuning(mmc, opcode);
620
621 if (!err && !host->tuning_err)
622 amd_host->tuned_clock = true;
623
624 return err;
625}
626
627static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
628{
629 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
630 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
631
632 if (mask & SDHCI_RESET_ALL) {
633 amd_host->tuned_clock = false;
634 sdhci_acpi_amd_hs400_dll(host, false);
635 }
636
637 sdhci_reset(host, mask);
638}
639
640static const struct sdhci_ops sdhci_acpi_ops_amd = {
641 .set_clock = sdhci_set_clock,
642 .set_bus_width = sdhci_set_bus_width,
643 .reset = amd_sdhci_reset,
644 .set_uhs_signaling = sdhci_set_uhs_signaling,
645};
646
647static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
648 .ops = &sdhci_acpi_ops_amd,
649};
650
651static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
652 struct acpi_device *adev)
653{
654 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
655 struct sdhci_host *host = c->host;
656
657 sdhci_read_caps(host);
658 if (host->caps1 & SDHCI_SUPPORT_DDR50)
659 host->mmc->caps = MMC_CAP_1_8V_DDR;
660
661 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
662 (host->mmc->caps & MMC_CAP_1_8V_DDR))
663 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
664
665 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
666 host->mmc_host_ops.set_ios = amd_set_ios;
667 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
668 return 0;
669}
670
671static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
672 .chip = &sdhci_acpi_chip_amd,
673 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
674 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
675 SDHCI_QUIRK_32BIT_DMA_SIZE |
676 SDHCI_QUIRK_32BIT_ADMA_SIZE,
677 .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
678 .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
679 .priv_size = sizeof(struct amd_sdhci_host),
680};
681
682struct sdhci_acpi_uid_slot {
683 const char *hid;
684 const char *uid;
685 const struct sdhci_acpi_slot *slot;
686};
687
688static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
689 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
690 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
691 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
692 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
693 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
694 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
695 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
696 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
697 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
698 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
699 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
700 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
701 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
702 { "PNP0D40" },
703 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
704 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
705 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
706 { },
707};
708
709static const struct acpi_device_id sdhci_acpi_ids[] = {
710 { "80865ACA" },
711 { "80865ACC" },
712 { "80865AD0" },
713 { "80860F14" },
714 { "80860F16" },
715 { "INT33BB" },
716 { "INT33C6" },
717 { "INT3436" },
718 { "INT344D" },
719 { "PNP0D40" },
720 { "QCOM8051" },
721 { "QCOM8052" },
722 { "AMDI0040" },
723 { },
724};
725MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
726
727static const struct dmi_system_id sdhci_acpi_quirks[] = {
728 {
729
730
731
732
733
734
735
736 .matches = {
737 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
738 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
739 },
740 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
741 },
742 {
743
744
745
746
747
748 .matches = {
749 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
750 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
751 },
752 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
753 },
754 {}
755};
756
757static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
758{
759 const struct sdhci_acpi_uid_slot *u;
760
761 for (u = sdhci_acpi_uids; u->hid; u++) {
762 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
763 return u->slot;
764 }
765 return NULL;
766}
767
768static int sdhci_acpi_probe(struct platform_device *pdev)
769{
770 struct device *dev = &pdev->dev;
771 const struct sdhci_acpi_slot *slot;
772 struct acpi_device *device, *child;
773 const struct dmi_system_id *id;
774 struct sdhci_acpi_host *c;
775 struct sdhci_host *host;
776 struct resource *iomem;
777 resource_size_t len;
778 size_t priv_size;
779 int quirks = 0;
780 int err;
781
782 device = ACPI_COMPANION(dev);
783 if (!device)
784 return -ENODEV;
785
786 id = dmi_first_match(sdhci_acpi_quirks);
787 if (id)
788 quirks = (long)id->driver_data;
789
790 slot = sdhci_acpi_get_slot(device);
791
792
793 acpi_device_fix_up_power(device);
794 if (!sdhci_acpi_no_fixup_child_power(device)) {
795 list_for_each_entry(child, &device->children, node)
796 if (child->status.present && child->status.enabled)
797 acpi_device_fix_up_power(child);
798 }
799
800 if (sdhci_acpi_byt_defer(dev))
801 return -EPROBE_DEFER;
802
803 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
804 if (!iomem)
805 return -ENOMEM;
806
807 len = resource_size(iomem);
808 if (len < 0x100)
809 dev_err(dev, "Invalid iomem size!\n");
810
811 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
812 return -ENOMEM;
813
814 priv_size = slot ? slot->priv_size : 0;
815 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
816 if (IS_ERR(host))
817 return PTR_ERR(host);
818
819 c = sdhci_priv(host);
820 c->host = host;
821 c->slot = slot;
822 c->pdev = pdev;
823 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
824
825 platform_set_drvdata(pdev, c);
826
827 host->hw_name = "ACPI";
828 host->ops = &sdhci_acpi_ops_dflt;
829 host->irq = platform_get_irq(pdev, 0);
830 if (host->irq < 0) {
831 err = -EINVAL;
832 goto err_free;
833 }
834
835 host->ioaddr = devm_ioremap(dev, iomem->start,
836 resource_size(iomem));
837 if (host->ioaddr == NULL) {
838 err = -ENOMEM;
839 goto err_free;
840 }
841
842 if (c->slot) {
843 if (c->slot->probe_slot) {
844 err = c->slot->probe_slot(pdev, device);
845 if (err)
846 goto err_free;
847 }
848 if (c->slot->chip) {
849 host->ops = c->slot->chip->ops;
850 host->quirks |= c->slot->chip->quirks;
851 host->quirks2 |= c->slot->chip->quirks2;
852 host->mmc->caps |= c->slot->chip->caps;
853 host->mmc->caps2 |= c->slot->chip->caps2;
854 host->mmc->pm_caps |= c->slot->chip->pm_caps;
855 }
856 host->quirks |= c->slot->quirks;
857 host->quirks2 |= c->slot->quirks2;
858 host->mmc->caps |= c->slot->caps;
859 host->mmc->caps2 |= c->slot->caps2;
860 host->mmc->pm_caps |= c->slot->pm_caps;
861 }
862
863 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
864
865 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
866 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
867
868 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
869 if (err) {
870 if (err == -EPROBE_DEFER)
871 goto err_free;
872 dev_warn(dev, "failed to setup card detect gpio\n");
873 c->use_runtime_pm = false;
874 }
875
876 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
877 c->reset_signal_volt_on_suspend = true;
878
879 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
880 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
881 }
882
883 err = sdhci_setup_host(host);
884 if (err)
885 goto err_free;
886
887 if (c->slot && c->slot->setup_host) {
888 err = c->slot->setup_host(pdev);
889 if (err)
890 goto err_cleanup;
891 }
892
893 err = __sdhci_add_host(host);
894 if (err)
895 goto err_cleanup;
896
897 if (c->use_runtime_pm) {
898 pm_runtime_set_active(dev);
899 pm_suspend_ignore_children(dev, 1);
900 pm_runtime_set_autosuspend_delay(dev, 50);
901 pm_runtime_use_autosuspend(dev);
902 pm_runtime_enable(dev);
903 }
904
905 device_enable_async_suspend(dev);
906
907 return 0;
908
909err_cleanup:
910 sdhci_cleanup_host(c->host);
911err_free:
912 if (c->slot && c->slot->free_slot)
913 c->slot->free_slot(pdev);
914
915 sdhci_free_host(c->host);
916 return err;
917}
918
919static int sdhci_acpi_remove(struct platform_device *pdev)
920{
921 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
922 struct device *dev = &pdev->dev;
923 int dead;
924
925 if (c->use_runtime_pm) {
926 pm_runtime_get_sync(dev);
927 pm_runtime_disable(dev);
928 pm_runtime_put_noidle(dev);
929 }
930
931 if (c->slot && c->slot->remove_slot)
932 c->slot->remove_slot(pdev);
933
934 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
935 sdhci_remove_host(c->host, dead);
936
937 if (c->slot && c->slot->free_slot)
938 c->slot->free_slot(pdev);
939
940 sdhci_free_host(c->host);
941
942 return 0;
943}
944
945static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
946 struct device *dev)
947{
948 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
949 struct sdhci_host *host = c->host;
950
951 if (c->is_intel && c->reset_signal_volt_on_suspend &&
952 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
953 struct intel_host *intel_host = sdhci_acpi_priv(c);
954 unsigned int fn = INTEL_DSM_V33_SWITCH;
955 u32 result = 0;
956
957 intel_dsm(intel_host, dev, fn, &result);
958 }
959}
960
961#ifdef CONFIG_PM_SLEEP
962
963static int sdhci_acpi_suspend(struct device *dev)
964{
965 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
966 struct sdhci_host *host = c->host;
967 int ret;
968
969 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
970 mmc_retune_needed(host->mmc);
971
972 ret = sdhci_suspend_host(host);
973 if (ret)
974 return ret;
975
976 sdhci_acpi_reset_signal_voltage_if_needed(dev);
977 return 0;
978}
979
980static int sdhci_acpi_resume(struct device *dev)
981{
982 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
983
984 sdhci_acpi_byt_setting(&c->pdev->dev);
985
986 return sdhci_resume_host(c->host);
987}
988
989#endif
990
991#ifdef CONFIG_PM
992
993static int sdhci_acpi_runtime_suspend(struct device *dev)
994{
995 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
996 struct sdhci_host *host = c->host;
997 int ret;
998
999 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1000 mmc_retune_needed(host->mmc);
1001
1002 ret = sdhci_runtime_suspend_host(host);
1003 if (ret)
1004 return ret;
1005
1006 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1007 return 0;
1008}
1009
1010static int sdhci_acpi_runtime_resume(struct device *dev)
1011{
1012 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1013
1014 sdhci_acpi_byt_setting(&c->pdev->dev);
1015
1016 return sdhci_runtime_resume_host(c->host, 0);
1017}
1018
1019#endif
1020
1021static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1022 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1023 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1024 sdhci_acpi_runtime_resume, NULL)
1025};
1026
1027static struct platform_driver sdhci_acpi_driver = {
1028 .driver = {
1029 .name = "sdhci-acpi",
1030 .acpi_match_table = sdhci_acpi_ids,
1031 .pm = &sdhci_acpi_pm_ops,
1032 },
1033 .probe = sdhci_acpi_probe,
1034 .remove = sdhci_acpi_remove,
1035};
1036
1037module_platform_driver(sdhci_acpi_driver);
1038
1039MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1040MODULE_AUTHOR("Adrian Hunter");
1041MODULE_LICENSE("GPL v2");
1042
