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11#include <linux/bitfield.h>
12#include <linux/io.h>
13#include <linux/iopoll.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/pm_qos.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/mmc.h>
22#include <linux/mmc/sdio.h>
23#include <linux/mmc/slot-gpio.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/platform_data/mmc-esdhc-imx.h>
28#include <linux/pm_runtime.h>
29#include "sdhci-pltfm.h"
30#include "sdhci-esdhc.h"
31#include "cqhci.h"
32
33#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
34#define ESDHC_CTRL_D3CD 0x08
35#define ESDHC_BURST_LEN_EN_INCR (1 << 27)
36
37#define ESDHC_VENDOR_SPEC 0xc0
38#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
39#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
40#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
41#define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
42#define ESDHC_DEBUG_SEL_REG 0xc3
43#define ESDHC_DEBUG_SEL_MASK 0xf
44#define ESDHC_DEBUG_SEL_CMD_STATE 1
45#define ESDHC_DEBUG_SEL_DATA_STATE 2
46#define ESDHC_DEBUG_SEL_TRANS_STATE 3
47#define ESDHC_DEBUG_SEL_DMA_STATE 4
48#define ESDHC_DEBUG_SEL_ADMA_STATE 5
49#define ESDHC_DEBUG_SEL_FIFO_STATE 6
50#define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
51#define ESDHC_WTMK_LVL 0x44
52#define ESDHC_WTMK_DEFAULT_VAL 0x10401040
53#define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
54#define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
55#define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
56#define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
57#define ESDHC_WTMK_LVL_WML_VAL_DEF 64
58#define ESDHC_WTMK_LVL_WML_VAL_MAX 128
59#define ESDHC_MIX_CTRL 0x48
60#define ESDHC_MIX_CTRL_DDREN (1 << 3)
61#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
62#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
63#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
64#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
65#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
66#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
67#define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
68
69#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
70
71#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
72
73
74#define ESDHC_DLL_CTRL 0x60
75#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
76#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
77
78
79#define ESDHC_TUNE_CTRL_STATUS 0x68
80#define ESDHC_TUNE_CTRL_STEP 1
81#define ESDHC_TUNE_CTRL_MIN 0
82#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
83
84
85#define ESDHC_STROBE_DLL_CTRL 0x70
86#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
87#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
88#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
89#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
90#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
91
92#define ESDHC_STROBE_DLL_STATUS 0x74
93#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
94#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
95
96#define ESDHC_VEND_SPEC2 0xc8
97#define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
98
99#define ESDHC_TUNING_CTRL 0xcc
100#define ESDHC_STD_TUNING_EN (1 << 24)
101
102#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
103#define ESDHC_TUNING_START_TAP_MASK 0x7f
104#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
105#define ESDHC_TUNING_STEP_MASK 0x00070000
106#define ESDHC_TUNING_STEP_SHIFT 16
107
108
109#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
110#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
111
112
113
114
115#define ESDHC_CTRL_4BITBUS (0x1 << 1)
116#define ESDHC_CTRL_8BITBUS (0x2 << 1)
117#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
118
119
120
121
122
123
124
125#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
126
127
128#define ESDHC_CQHCI_ADDR_OFFSET 0x100
129
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137
138
139
140
141#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
142
143
144
145
146#define ESDHC_FLAG_USDHC BIT(3)
147
148#define ESDHC_FLAG_MAN_TUNING BIT(4)
149
150#define ESDHC_FLAG_STD_TUNING BIT(5)
151
152#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
153
154
155
156
157
158
159
160#define ESDHC_FLAG_ERR004536 BIT(7)
161
162#define ESDHC_FLAG_HS200 BIT(8)
163
164#define ESDHC_FLAG_HS400 BIT(9)
165
166
167
168
169
170#define ESDHC_FLAG_ERR010450 BIT(10)
171
172#define ESDHC_FLAG_HS400_ES BIT(11)
173
174#define ESDHC_FLAG_CQHCI BIT(12)
175
176#define ESDHC_FLAG_PMQOS BIT(13)
177
178#define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
179
180#define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
181
182
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188
189
190
191
192#define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
193
194struct esdhc_soc_data {
195 u32 flags;
196};
197
198static const struct esdhc_soc_data esdhc_imx25_data = {
199 .flags = ESDHC_FLAG_ERR004536,
200};
201
202static const struct esdhc_soc_data esdhc_imx35_data = {
203 .flags = ESDHC_FLAG_ERR004536,
204};
205
206static const struct esdhc_soc_data esdhc_imx51_data = {
207 .flags = 0,
208};
209
210static const struct esdhc_soc_data esdhc_imx53_data = {
211 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
212};
213
214static const struct esdhc_soc_data usdhc_imx6q_data = {
215 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
216 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
217};
218
219static const struct esdhc_soc_data usdhc_imx6sl_data = {
220 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
221 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
222 | ESDHC_FLAG_HS200
223 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
224};
225
226static const struct esdhc_soc_data usdhc_imx6sll_data = {
227 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
228 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
229 | ESDHC_FLAG_HS400
230 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
231};
232
233static const struct esdhc_soc_data usdhc_imx6sx_data = {
234 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
235 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
236 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
237 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
238};
239
240static const struct esdhc_soc_data usdhc_imx6ull_data = {
241 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
242 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
243 | ESDHC_FLAG_ERR010450
244 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
245};
246
247static const struct esdhc_soc_data usdhc_imx7d_data = {
248 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
249 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
250 | ESDHC_FLAG_HS400
251 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
252 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
253};
254
255static struct esdhc_soc_data usdhc_imx7ulp_data = {
256 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
257 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
258 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
259 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
260};
261
262static struct esdhc_soc_data usdhc_imx8qxp_data = {
263 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
264 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
265 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
266 | ESDHC_FLAG_CQHCI
267 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
268 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
269};
270
271static struct esdhc_soc_data usdhc_imx8mm_data = {
272 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
273 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
274 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
275 | ESDHC_FLAG_CQHCI
276 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
277};
278
279struct pltfm_imx_data {
280 u32 scratchpad;
281 struct pinctrl *pinctrl;
282 struct pinctrl_state *pins_100mhz;
283 struct pinctrl_state *pins_200mhz;
284 const struct esdhc_soc_data *socdata;
285 struct esdhc_platform_data boarddata;
286 struct clk *clk_ipg;
287 struct clk *clk_ahb;
288 struct clk *clk_per;
289 unsigned int actual_clock;
290 enum {
291 NO_CMD_PENDING,
292 MULTIBLK_IN_PROCESS,
293 WAIT_FOR_INT,
294 } multiblock_status;
295 u32 is_ddr;
296 struct pm_qos_request pm_qos_req;
297};
298
299static const struct platform_device_id imx_esdhc_devtype[] = {
300 {
301 .name = "sdhci-esdhc-imx25",
302 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
303 }, {
304 .name = "sdhci-esdhc-imx35",
305 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
306 }, {
307 .name = "sdhci-esdhc-imx51",
308 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
309 }, {
310
311 }
312};
313MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
314
315static const struct of_device_id imx_esdhc_dt_ids[] = {
316 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
317 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
318 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
319 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
320 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
321 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
322 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
323 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
324 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
325 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
326 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
327 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
328 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
329 { }
330};
331MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
332
333static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
334{
335 return data->socdata == &esdhc_imx25_data;
336}
337
338static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
339{
340 return data->socdata == &esdhc_imx53_data;
341}
342
343static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
344{
345 return data->socdata == &usdhc_imx6q_data;
346}
347
348static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
349{
350 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
351}
352
353static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
354{
355 void __iomem *base = host->ioaddr + (reg & ~0x3);
356 u32 shift = (reg & 0x3) * 8;
357
358 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
359}
360
361#define DRIVER_NAME "sdhci-esdhc-imx"
362#define ESDHC_IMX_DUMP(f, x...) \
363 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
364static void esdhc_dump_debug_regs(struct sdhci_host *host)
365{
366 int i;
367 char *debug_status[7] = {
368 "cmd debug status",
369 "data debug status",
370 "trans debug status",
371 "dma debug status",
372 "adma debug status",
373 "fifo debug status",
374 "async fifo debug status"
375 };
376
377 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
378 for (i = 0; i < 7; i++) {
379 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
380 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
381 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
382 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
383 }
384
385 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
386
387}
388
389static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
390{
391 u32 present_state;
392 int ret;
393
394 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
395 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
396 if (ret == -ETIMEDOUT)
397 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
398}
399
400static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
401{
402 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
403 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
404 u32 val = readl(host->ioaddr + reg);
405
406 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
407 u32 fsl_prss = val;
408
409 val = fsl_prss & 0x000FFFFF;
410
411 val |= (fsl_prss & 0x0F000000) >> 4;
412
413 val |= (fsl_prss & 0x00800000) << 1;
414 }
415
416 if (unlikely(reg == SDHCI_CAPABILITIES)) {
417
418 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
419 val &= 0xffff0000;
420
421
422
423
424
425
426
427
428 if (val & SDHCI_CAN_DO_ADMA1) {
429 val &= ~SDHCI_CAN_DO_ADMA1;
430 val |= SDHCI_CAN_DO_ADMA2;
431 }
432 }
433
434 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
435 if (esdhc_is_usdhc(imx_data)) {
436 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
437 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
438 else
439
440 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
441 | SDHCI_SUPPORT_SDR50
442 | SDHCI_USE_SDR50_TUNING
443 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
444 SDHCI_TUNING_MODE_3);
445
446 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
447 val |= SDHCI_SUPPORT_HS400;
448
449
450
451
452
453 if (IS_ERR_OR_NULL(imx_data->pins_100mhz) ||
454 IS_ERR_OR_NULL(imx_data->pins_200mhz))
455 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50
456 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
457 }
458 }
459
460 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
461 val = 0;
462 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
463 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
464 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
465 }
466
467 if (unlikely(reg == SDHCI_INT_STATUS)) {
468 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
469 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
470 val |= SDHCI_INT_ADMA_ERROR;
471 }
472
473
474
475
476
477 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
478 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
479 val &= ~SDHCI_INT_RESPONSE;
480 writel(SDHCI_INT_RESPONSE, host->ioaddr +
481 SDHCI_INT_STATUS);
482 imx_data->multiblock_status = NO_CMD_PENDING;
483 }
484 }
485
486 return val;
487}
488
489static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
490{
491 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
492 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
493 u32 data;
494
495 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
496 reg == SDHCI_INT_STATUS)) {
497 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
498
499
500
501
502
503
504
505
506 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
507 data &= ~ESDHC_CTRL_D3CD;
508 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
509 data |= ESDHC_CTRL_D3CD;
510 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
511 }
512
513 if (val & SDHCI_INT_ADMA_ERROR) {
514 val &= ~SDHCI_INT_ADMA_ERROR;
515 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
516 }
517 }
518
519 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
520 && (reg == SDHCI_INT_STATUS)
521 && (val & SDHCI_INT_DATA_END))) {
522 u32 v;
523 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
524 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
525 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
526
527 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
528 {
529
530 data = MMC_STOP_TRANSMISSION << 24 |
531 SDHCI_CMD_ABORTCMD << 16;
532 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
533 imx_data->multiblock_status = WAIT_FOR_INT;
534 }
535 }
536
537 writel(val, host->ioaddr + reg);
538}
539
540static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
541{
542 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
543 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
544 u16 ret = 0;
545 u32 val;
546
547 if (unlikely(reg == SDHCI_HOST_VERSION)) {
548 reg ^= 2;
549 if (esdhc_is_usdhc(imx_data)) {
550
551
552
553
554 return SDHCI_SPEC_300;
555 }
556 }
557
558 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
559 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
560 if (val & ESDHC_VENDOR_SPEC_VSELECT)
561 ret |= SDHCI_CTRL_VDD_180;
562
563 if (esdhc_is_usdhc(imx_data)) {
564 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
565 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
566 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
567
568 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
569 }
570
571 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
572 ret |= SDHCI_CTRL_EXEC_TUNING;
573 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
574 ret |= SDHCI_CTRL_TUNED_CLK;
575
576 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
577
578 return ret;
579 }
580
581 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
582 if (esdhc_is_usdhc(imx_data)) {
583 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
584 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
585
586 if (m & ESDHC_MIX_CTRL_AC23EN) {
587 ret &= ~ESDHC_MIX_CTRL_AC23EN;
588 ret |= SDHCI_TRNS_AUTO_CMD23;
589 }
590 } else {
591 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
592 }
593
594 return ret;
595 }
596
597 return readw(host->ioaddr + reg);
598}
599
600static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
601{
602 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
603 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
604 u32 new_val = 0;
605
606 switch (reg) {
607 case SDHCI_CLOCK_CONTROL:
608 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
609 if (val & SDHCI_CLOCK_CARD_EN)
610 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
611 else
612 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
613 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
614 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
615 esdhc_wait_for_card_clock_gate_off(host);
616 return;
617 case SDHCI_HOST_CONTROL2:
618 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
619 if (val & SDHCI_CTRL_VDD_180)
620 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
621 else
622 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
623 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
624 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
625 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
626 if (val & SDHCI_CTRL_TUNED_CLK) {
627 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
628 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
629 } else {
630 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
631 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
632 }
633 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
634 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
635 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
636 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
637 if (val & SDHCI_CTRL_TUNED_CLK) {
638 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
639 } else {
640 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
641 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
642 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
643 }
644
645 if (val & SDHCI_CTRL_EXEC_TUNING) {
646 v |= ESDHC_MIX_CTRL_EXE_TUNE;
647 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
648 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
649 } else {
650 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
651 }
652
653 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
654 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
655 }
656 return;
657 case SDHCI_TRANSFER_MODE:
658 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
659 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
660 && (host->cmd->data->blocks > 1)
661 && (host->cmd->data->flags & MMC_DATA_READ)) {
662 u32 v;
663 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
664 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
665 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
666 }
667
668 if (esdhc_is_usdhc(imx_data)) {
669 u32 wml;
670 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
671
672 if (val & SDHCI_TRNS_AUTO_CMD23) {
673 val &= ~SDHCI_TRNS_AUTO_CMD23;
674 val |= ESDHC_MIX_CTRL_AC23EN;
675 }
676 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
677 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
678
679
680
681
682
683 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
684 if (val & SDHCI_TRNS_DMA) {
685 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
686 } else {
687 u8 ctrl;
688 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
689
690
691
692
693
694
695
696
697
698 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
699 ctrl &= ~SDHCI_CTRL_DMA_MASK;
700 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
701 }
702 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
703 ESDHC_WTMK_LVL_WR_WML_MASK);
704 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
705 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
706 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
707 } else {
708
709
710
711
712 imx_data->scratchpad = val;
713 }
714 return;
715 case SDHCI_COMMAND:
716 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
717 val |= SDHCI_CMD_ABORTCMD;
718
719 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
720 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
721 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
722
723 if (esdhc_is_usdhc(imx_data))
724 writel(val << 16,
725 host->ioaddr + SDHCI_TRANSFER_MODE);
726 else
727 writel(val << 16 | imx_data->scratchpad,
728 host->ioaddr + SDHCI_TRANSFER_MODE);
729 return;
730 case SDHCI_BLOCK_SIZE:
731 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
732 break;
733 }
734 esdhc_clrset_le(host, 0xffff, val, reg);
735}
736
737static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
738{
739 u8 ret;
740 u32 val;
741
742 switch (reg) {
743 case SDHCI_HOST_CONTROL:
744 val = readl(host->ioaddr + reg);
745
746 ret = val & SDHCI_CTRL_LED;
747 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
748 ret |= (val & ESDHC_CTRL_4BITBUS);
749 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
750 return ret;
751 }
752
753 return readb(host->ioaddr + reg);
754}
755
756static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
757{
758 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
759 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
760 u32 new_val = 0;
761 u32 mask;
762
763 switch (reg) {
764 case SDHCI_POWER_CONTROL:
765
766
767
768
769 return;
770 case SDHCI_HOST_CONTROL:
771
772 new_val = val & SDHCI_CTRL_LED;
773
774 new_val |= ESDHC_HOST_CONTROL_LE;
775
776 if (!is_imx25_esdhc(imx_data)) {
777
778 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
779 }
780
781
782
783
784
785
786
787 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
788
789 esdhc_clrset_le(host, mask, new_val, reg);
790 return;
791 case SDHCI_SOFTWARE_RESET:
792 if (val & SDHCI_RESET_DATA)
793 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
794 break;
795 }
796 esdhc_clrset_le(host, 0xff, val, reg);
797
798 if (reg == SDHCI_SOFTWARE_RESET) {
799 if (val & SDHCI_RESET_ALL) {
800
801
802
803
804
805
806
807
808
809 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
810
811
812
813
814 if (esdhc_is_usdhc(imx_data)) {
815
816
817
818 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
819 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
820 host->ioaddr + ESDHC_MIX_CTRL);
821 imx_data->is_ddr = 0;
822 }
823 } else if (val & SDHCI_RESET_DATA) {
824
825
826
827
828
829 esdhc_clrset_le(host, 0xff, new_val,
830 SDHCI_HOST_CONTROL);
831 }
832 }
833}
834
835static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
836{
837 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
838
839 return pltfm_host->clock;
840}
841
842static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
843{
844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845
846 return pltfm_host->clock / 256 / 16;
847}
848
849static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
850 unsigned int clock)
851{
852 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
853 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
854 unsigned int host_clock = pltfm_host->clock;
855 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
856 int pre_div = 1;
857 int div = 1;
858 int ret;
859 u32 temp, val;
860
861 if (esdhc_is_usdhc(imx_data)) {
862 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
863 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
864 host->ioaddr + ESDHC_VENDOR_SPEC);
865 esdhc_wait_for_card_clock_gate_off(host);
866 }
867
868 if (clock == 0) {
869 host->mmc->actual_clock = 0;
870 return;
871 }
872
873
874 if (is_imx53_esdhc(imx_data)) {
875
876
877
878
879 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
880 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
881 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
882 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
883 if (temp & BIT(10))
884 pre_div = 2;
885 }
886
887 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
888 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
889 | ESDHC_CLOCK_MASK);
890 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
891
892 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
893 unsigned int max_clock;
894
895 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
896
897 clock = min(clock, max_clock);
898 }
899
900 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
901 pre_div < 256)
902 pre_div *= 2;
903
904 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
905 div++;
906
907 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
908 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
909 clock, host->mmc->actual_clock);
910
911 pre_div >>= 1;
912 div--;
913
914 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
915 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
916 | (div << ESDHC_DIVIDER_SHIFT)
917 | (pre_div << ESDHC_PREDIV_SHIFT));
918 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
919
920
921 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
922 (temp & ESDHC_CLOCK_STABLE), 2, 100);
923 if (ret == -ETIMEDOUT)
924 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
925
926 if (esdhc_is_usdhc(imx_data)) {
927 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
928 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
929 host->ioaddr + ESDHC_VENDOR_SPEC);
930 }
931
932}
933
934static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
935{
936 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
937 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
938 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
939
940 switch (boarddata->wp_type) {
941 case ESDHC_WP_GPIO:
942 return mmc_gpio_get_ro(host->mmc);
943 case ESDHC_WP_CONTROLLER:
944 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
945 SDHCI_WRITE_PROTECT);
946 case ESDHC_WP_NONE:
947 break;
948 }
949
950 return -ENOSYS;
951}
952
953static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
954{
955 u32 ctrl;
956
957 switch (width) {
958 case MMC_BUS_WIDTH_8:
959 ctrl = ESDHC_CTRL_8BITBUS;
960 break;
961 case MMC_BUS_WIDTH_4:
962 ctrl = ESDHC_CTRL_4BITBUS;
963 break;
964 default:
965 ctrl = 0;
966 break;
967 }
968
969 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
970 SDHCI_HOST_CONTROL);
971}
972
973static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
974{
975 struct sdhci_host *host = mmc_priv(mmc);
976
977
978
979
980
981 if (host->timing == MMC_TIMING_UHS_DDR50)
982 return 0;
983
984 return sdhci_execute_tuning(mmc, opcode);
985}
986
987static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
988{
989 u32 reg;
990
991
992 mdelay(1);
993
994 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
995 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
996 ESDHC_MIX_CTRL_FBCLK_SEL;
997 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
998 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
999 dev_dbg(mmc_dev(host->mmc),
1000 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1001 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1002}
1003
1004static void esdhc_post_tuning(struct sdhci_host *host)
1005{
1006 u32 reg;
1007
1008 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1009 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1010 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1011 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1012}
1013
1014static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1015{
1016 int min, max, avg, ret;
1017
1018
1019 min = ESDHC_TUNE_CTRL_MIN;
1020 while (min < ESDHC_TUNE_CTRL_MAX) {
1021 esdhc_prepare_tuning(host, min);
1022 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1023 break;
1024 min += ESDHC_TUNE_CTRL_STEP;
1025 }
1026
1027
1028 max = min + ESDHC_TUNE_CTRL_STEP;
1029 while (max < ESDHC_TUNE_CTRL_MAX) {
1030 esdhc_prepare_tuning(host, max);
1031 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1032 max -= ESDHC_TUNE_CTRL_STEP;
1033 break;
1034 }
1035 max += ESDHC_TUNE_CTRL_STEP;
1036 }
1037
1038
1039 avg = (min + max) / 2;
1040 esdhc_prepare_tuning(host, avg);
1041 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1042 esdhc_post_tuning(host);
1043
1044 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1045 ret ? "failed" : "passed", avg, ret);
1046
1047 return ret;
1048}
1049
1050static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1051{
1052 struct sdhci_host *host = mmc_priv(mmc);
1053 u32 m;
1054
1055 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1056 if (ios->enhanced_strobe)
1057 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1058 else
1059 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1060 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1061}
1062
1063static int esdhc_change_pinstate(struct sdhci_host *host,
1064 unsigned int uhs)
1065{
1066 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1067 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1068 struct pinctrl_state *pinctrl;
1069
1070 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1071
1072 if (IS_ERR(imx_data->pinctrl) ||
1073 IS_ERR(imx_data->pins_100mhz) ||
1074 IS_ERR(imx_data->pins_200mhz))
1075 return -EINVAL;
1076
1077 switch (uhs) {
1078 case MMC_TIMING_UHS_SDR50:
1079 case MMC_TIMING_UHS_DDR50:
1080 pinctrl = imx_data->pins_100mhz;
1081 break;
1082 case MMC_TIMING_UHS_SDR104:
1083 case MMC_TIMING_MMC_HS200:
1084 case MMC_TIMING_MMC_HS400:
1085 pinctrl = imx_data->pins_200mhz;
1086 break;
1087 default:
1088
1089 return pinctrl_select_default_state(mmc_dev(host->mmc));
1090 }
1091
1092 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1093}
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104static void esdhc_set_strobe_dll(struct sdhci_host *host)
1105{
1106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1107 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1108 u32 strobe_delay;
1109 u32 v;
1110 int ret;
1111
1112
1113 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1114 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1115 host->ioaddr + ESDHC_VENDOR_SPEC);
1116 esdhc_wait_for_card_clock_gate_off(host);
1117
1118
1119 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1120 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1121
1122 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1123
1124
1125
1126
1127
1128 if (imx_data->boarddata.strobe_dll_delay_target)
1129 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1130 else
1131 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1132 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1133 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1134 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1135 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1136
1137
1138 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1139 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1140 if (ret == -ETIMEDOUT)
1141 dev_warn(mmc_dev(host->mmc),
1142 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1143}
1144
1145static void esdhc_reset_tuning(struct sdhci_host *host)
1146{
1147 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1148 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1149 u32 ctrl;
1150
1151
1152 if (esdhc_is_usdhc(imx_data)) {
1153 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1154 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1155 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1156 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1157 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1158 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1159 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1160 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1161 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1162 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1163 }
1164 }
1165}
1166
1167static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1168{
1169 u32 m;
1170 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1171 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1172 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1173
1174
1175 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1176 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1177 imx_data->is_ddr = 0;
1178
1179 switch (timing) {
1180 case MMC_TIMING_UHS_SDR12:
1181 case MMC_TIMING_UHS_SDR25:
1182 case MMC_TIMING_UHS_SDR50:
1183 case MMC_TIMING_UHS_SDR104:
1184 case MMC_TIMING_MMC_HS:
1185 case MMC_TIMING_MMC_HS200:
1186 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1187 break;
1188 case MMC_TIMING_UHS_DDR50:
1189 case MMC_TIMING_MMC_DDR52:
1190 m |= ESDHC_MIX_CTRL_DDREN;
1191 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1192 imx_data->is_ddr = 1;
1193 if (boarddata->delay_line) {
1194 u32 v;
1195 v = boarddata->delay_line <<
1196 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1197 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1198 if (is_imx53_esdhc(imx_data))
1199 v <<= 1;
1200 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1201 }
1202 break;
1203 case MMC_TIMING_MMC_HS400:
1204 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1205 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1206 imx_data->is_ddr = 1;
1207
1208 host->ops->set_clock(host, host->clock);
1209 esdhc_set_strobe_dll(host);
1210 break;
1211 case MMC_TIMING_LEGACY:
1212 default:
1213 esdhc_reset_tuning(host);
1214 break;
1215 }
1216
1217 esdhc_change_pinstate(host, timing);
1218}
1219
1220static void esdhc_reset(struct sdhci_host *host, u8 mask)
1221{
1222 sdhci_reset(host, mask);
1223
1224 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1225 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1226}
1227
1228static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1229{
1230 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1231 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1232
1233
1234 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1235}
1236
1237static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1238{
1239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1240 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1241
1242
1243 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1244 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1245 SDHCI_TIMEOUT_CONTROL);
1246}
1247
1248static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1249{
1250 int cmd_error = 0;
1251 int data_error = 0;
1252
1253 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1254 return intmask;
1255
1256 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1257
1258 return 0;
1259}
1260
1261static struct sdhci_ops sdhci_esdhc_ops = {
1262 .read_l = esdhc_readl_le,
1263 .read_w = esdhc_readw_le,
1264 .read_b = esdhc_readb_le,
1265 .write_l = esdhc_writel_le,
1266 .write_w = esdhc_writew_le,
1267 .write_b = esdhc_writeb_le,
1268 .set_clock = esdhc_pltfm_set_clock,
1269 .get_max_clock = esdhc_pltfm_get_max_clock,
1270 .get_min_clock = esdhc_pltfm_get_min_clock,
1271 .get_max_timeout_count = esdhc_get_max_timeout_count,
1272 .get_ro = esdhc_pltfm_get_ro,
1273 .set_timeout = esdhc_set_timeout,
1274 .set_bus_width = esdhc_pltfm_set_bus_width,
1275 .set_uhs_signaling = esdhc_set_uhs_signaling,
1276 .reset = esdhc_reset,
1277 .irq = esdhc_cqhci_irq,
1278 .dump_vendor_regs = esdhc_dump_debug_regs,
1279};
1280
1281static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1282 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1283 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1284 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1285 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1286 .ops = &sdhci_esdhc_ops,
1287};
1288
1289static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1290{
1291 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1292 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1293 struct cqhci_host *cq_host = host->mmc->cqe_private;
1294 int tmp;
1295
1296 if (esdhc_is_usdhc(imx_data)) {
1297
1298
1299
1300
1301 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1315 | ESDHC_BURST_LEN_EN_INCR,
1316 host->ioaddr + SDHCI_HOST_CONTROL);
1317
1318
1319
1320
1321
1322 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1323 host->ioaddr + 0x6c);
1324
1325
1326 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1338 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1339 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1340 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1341
1342 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1343 }
1344
1345 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1346 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1347 tmp |= ESDHC_STD_TUNING_EN |
1348 ESDHC_TUNING_START_TAP_DEFAULT;
1349 if (imx_data->boarddata.tuning_start_tap) {
1350 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1351 tmp |= imx_data->boarddata.tuning_start_tap;
1352 }
1353
1354 if (imx_data->boarddata.tuning_step) {
1355 tmp &= ~ESDHC_TUNING_STEP_MASK;
1356 tmp |= imx_data->boarddata.tuning_step
1357 << ESDHC_TUNING_STEP_SHIFT;
1358 }
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1371 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1372 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1373
1374
1375
1376
1377
1378 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1379 tmp &= ~ESDHC_STD_TUNING_EN;
1380 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1381 }
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392 if (cq_host) {
1393 tmp = cqhci_readl(cq_host, CQHCI_IS);
1394 cqhci_writel(cq_host, tmp, CQHCI_IS);
1395 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1396 }
1397 }
1398}
1399
1400static void esdhc_cqe_enable(struct mmc_host *mmc)
1401{
1402 struct sdhci_host *host = mmc_priv(mmc);
1403 struct cqhci_host *cq_host = mmc->cqe_private;
1404 u32 reg;
1405 u16 mode;
1406 int count = 10;
1407
1408
1409
1410
1411
1412 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1413 while (reg & SDHCI_DATA_AVAILABLE) {
1414 sdhci_readl(host, SDHCI_BUFFER);
1415 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1416 if (count-- == 0) {
1417 dev_warn(mmc_dev(host->mmc),
1418 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1419 break;
1420 }
1421 mdelay(1);
1422 }
1423
1424
1425
1426
1427
1428
1429 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1430 if (host->flags & SDHCI_REQ_USE_DMA)
1431 mode |= SDHCI_TRNS_DMA;
1432 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1433 mode |= SDHCI_TRNS_BLK_CNT_EN;
1434 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1435
1436
1437
1438
1439
1440
1441
1442 cqhci_writel(cq_host, 0, CQHCI_CTL);
1443 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1444 dev_err(mmc_dev(host->mmc),
1445 "failed to exit halt state when enable CQE\n");
1446
1447
1448 sdhci_cqe_enable(mmc);
1449}
1450
1451static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1452{
1453 sdhci_dumpregs(mmc_priv(mmc));
1454}
1455
1456static const struct cqhci_host_ops esdhc_cqhci_ops = {
1457 .enable = esdhc_cqe_enable,
1458 .disable = sdhci_cqe_disable,
1459 .dumpregs = esdhc_sdhci_dumpregs,
1460};
1461
1462#ifdef CONFIG_OF
1463static int
1464sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1465 struct sdhci_host *host,
1466 struct pltfm_imx_data *imx_data)
1467{
1468 struct device_node *np = pdev->dev.of_node;
1469 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1470 int ret;
1471
1472 if (of_get_property(np, "fsl,wp-controller", NULL))
1473 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1474
1475
1476
1477
1478
1479
1480 if (of_property_read_bool(np, "wp-gpios"))
1481 boarddata->wp_type = ESDHC_WP_GPIO;
1482
1483 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1484 of_property_read_u32(np, "fsl,tuning-start-tap",
1485 &boarddata->tuning_start_tap);
1486
1487 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1488 &boarddata->strobe_dll_delay_target);
1489 if (of_find_property(np, "no-1-8-v", NULL))
1490 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1491
1492 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1493 boarddata->delay_line = 0;
1494
1495 mmc_of_parse_voltage(np, &host->ocr_mask);
1496
1497 if (esdhc_is_usdhc(imx_data)) {
1498 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1499 ESDHC_PINCTRL_STATE_100MHZ);
1500 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1501 ESDHC_PINCTRL_STATE_200MHZ);
1502 }
1503
1504
1505 ret = mmc_of_parse(host->mmc);
1506 if (ret)
1507 return ret;
1508
1509 if (mmc_gpio_get_cd(host->mmc) >= 0)
1510 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1511
1512 return 0;
1513}
1514#else
1515static inline int
1516sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1517 struct sdhci_host *host,
1518 struct pltfm_imx_data *imx_data)
1519{
1520 return -ENODEV;
1521}
1522#endif
1523
1524static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1525 struct sdhci_host *host,
1526 struct pltfm_imx_data *imx_data)
1527{
1528 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1529 int err;
1530
1531 if (!host->mmc->parent->platform_data) {
1532 dev_err(mmc_dev(host->mmc), "no board data!\n");
1533 return -EINVAL;
1534 }
1535
1536 imx_data->boarddata = *((struct esdhc_platform_data *)
1537 host->mmc->parent->platform_data);
1538
1539 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1540 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1541
1542 err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1543 if (err) {
1544 dev_err(mmc_dev(host->mmc),
1545 "failed to request write-protect gpio!\n");
1546 return err;
1547 }
1548 }
1549
1550
1551 switch (boarddata->cd_type) {
1552 case ESDHC_CD_GPIO:
1553 err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
1554 if (err) {
1555 dev_err(mmc_dev(host->mmc),
1556 "failed to request card-detect gpio!\n");
1557 return err;
1558 }
1559 fallthrough;
1560
1561 case ESDHC_CD_CONTROLLER:
1562
1563 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1564 break;
1565
1566 case ESDHC_CD_PERMANENT:
1567 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1568 break;
1569
1570 case ESDHC_CD_NONE:
1571 break;
1572 }
1573
1574 switch (boarddata->max_bus_width) {
1575 case 8:
1576 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1577 break;
1578 case 4:
1579 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1580 break;
1581 case 1:
1582 default:
1583 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1584 break;
1585 }
1586
1587 return 0;
1588}
1589
1590static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1591{
1592 const struct of_device_id *of_id =
1593 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1594 struct sdhci_pltfm_host *pltfm_host;
1595 struct sdhci_host *host;
1596 struct cqhci_host *cq_host;
1597 int err;
1598 struct pltfm_imx_data *imx_data;
1599
1600 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1601 sizeof(*imx_data));
1602 if (IS_ERR(host))
1603 return PTR_ERR(host);
1604
1605 pltfm_host = sdhci_priv(host);
1606
1607 imx_data = sdhci_pltfm_priv(pltfm_host);
1608
1609 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1610 pdev->id_entry->driver_data;
1611
1612 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1613 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1614
1615 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1616 if (IS_ERR(imx_data->clk_ipg)) {
1617 err = PTR_ERR(imx_data->clk_ipg);
1618 goto free_sdhci;
1619 }
1620
1621 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1622 if (IS_ERR(imx_data->clk_ahb)) {
1623 err = PTR_ERR(imx_data->clk_ahb);
1624 goto free_sdhci;
1625 }
1626
1627 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1628 if (IS_ERR(imx_data->clk_per)) {
1629 err = PTR_ERR(imx_data->clk_per);
1630 goto free_sdhci;
1631 }
1632
1633 pltfm_host->clk = imx_data->clk_per;
1634 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1635 err = clk_prepare_enable(imx_data->clk_per);
1636 if (err)
1637 goto free_sdhci;
1638 err = clk_prepare_enable(imx_data->clk_ipg);
1639 if (err)
1640 goto disable_per_clk;
1641 err = clk_prepare_enable(imx_data->clk_ahb);
1642 if (err)
1643 goto disable_ipg_clk;
1644
1645 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1646 if (IS_ERR(imx_data->pinctrl)) {
1647 err = PTR_ERR(imx_data->pinctrl);
1648 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1649 }
1650
1651 if (esdhc_is_usdhc(imx_data)) {
1652 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1653 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1654
1655
1656 host->mmc->caps |= MMC_CAP_CD_WAKE;
1657
1658 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1659 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1660
1661
1662 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1663 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1664 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1665
1666
1667
1668
1669
1670 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1671 }
1672
1673 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1674 sdhci_esdhc_ops.platform_execute_tuning =
1675 esdhc_executing_tuning;
1676
1677 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1678 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1679
1680 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1681 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1682
1683 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1684 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1685
1686 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1687 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1688 host->mmc_host_ops.hs400_enhanced_strobe =
1689 esdhc_hs400_enhanced_strobe;
1690 }
1691
1692 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1693 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1694 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1695 if (!cq_host) {
1696 err = -ENOMEM;
1697 goto disable_ahb_clk;
1698 }
1699
1700 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1701 cq_host->ops = &esdhc_cqhci_ops;
1702
1703 err = cqhci_init(cq_host, host->mmc, false);
1704 if (err)
1705 goto disable_ahb_clk;
1706 }
1707
1708 if (of_id)
1709 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1710 else
1711 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1712 if (err)
1713 goto disable_ahb_clk;
1714
1715 sdhci_esdhc_imx_hwinit(host);
1716
1717 err = sdhci_add_host(host);
1718 if (err)
1719 goto disable_ahb_clk;
1720
1721 pm_runtime_set_active(&pdev->dev);
1722 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1723 pm_runtime_use_autosuspend(&pdev->dev);
1724 pm_suspend_ignore_children(&pdev->dev, 1);
1725 pm_runtime_enable(&pdev->dev);
1726
1727 return 0;
1728
1729disable_ahb_clk:
1730 clk_disable_unprepare(imx_data->clk_ahb);
1731disable_ipg_clk:
1732 clk_disable_unprepare(imx_data->clk_ipg);
1733disable_per_clk:
1734 clk_disable_unprepare(imx_data->clk_per);
1735free_sdhci:
1736 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1737 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1738 sdhci_pltfm_free(pdev);
1739 return err;
1740}
1741
1742static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1743{
1744 struct sdhci_host *host = platform_get_drvdata(pdev);
1745 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1746 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1747 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1748
1749 pm_runtime_get_sync(&pdev->dev);
1750 pm_runtime_disable(&pdev->dev);
1751 pm_runtime_put_noidle(&pdev->dev);
1752
1753 sdhci_remove_host(host, dead);
1754
1755 clk_disable_unprepare(imx_data->clk_per);
1756 clk_disable_unprepare(imx_data->clk_ipg);
1757 clk_disable_unprepare(imx_data->clk_ahb);
1758
1759 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1760 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1761
1762 sdhci_pltfm_free(pdev);
1763
1764 return 0;
1765}
1766
1767#ifdef CONFIG_PM_SLEEP
1768static int sdhci_esdhc_suspend(struct device *dev)
1769{
1770 struct sdhci_host *host = dev_get_drvdata(dev);
1771 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1772 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1773 int ret;
1774
1775 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1776 ret = cqhci_suspend(host->mmc);
1777 if (ret)
1778 return ret;
1779 }
1780
1781 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1782 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1783 mmc_retune_timer_stop(host->mmc);
1784 mmc_retune_needed(host->mmc);
1785 }
1786
1787 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1788 mmc_retune_needed(host->mmc);
1789
1790 ret = sdhci_suspend_host(host);
1791 if (ret)
1792 return ret;
1793
1794 ret = pinctrl_pm_select_sleep_state(dev);
1795 if (ret)
1796 return ret;
1797
1798 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1799
1800 return ret;
1801}
1802
1803static int sdhci_esdhc_resume(struct device *dev)
1804{
1805 struct sdhci_host *host = dev_get_drvdata(dev);
1806 int ret;
1807
1808 ret = pinctrl_pm_select_default_state(dev);
1809 if (ret)
1810 return ret;
1811
1812
1813 sdhci_esdhc_imx_hwinit(host);
1814
1815 ret = sdhci_resume_host(host);
1816 if (ret)
1817 return ret;
1818
1819 if (host->mmc->caps2 & MMC_CAP2_CQE)
1820 ret = cqhci_resume(host->mmc);
1821
1822 if (!ret)
1823 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1824
1825 return ret;
1826}
1827#endif
1828
1829#ifdef CONFIG_PM
1830static int sdhci_esdhc_runtime_suspend(struct device *dev)
1831{
1832 struct sdhci_host *host = dev_get_drvdata(dev);
1833 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1834 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1835 int ret;
1836
1837 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1838 ret = cqhci_suspend(host->mmc);
1839 if (ret)
1840 return ret;
1841 }
1842
1843 ret = sdhci_runtime_suspend_host(host);
1844 if (ret)
1845 return ret;
1846
1847 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1848 mmc_retune_needed(host->mmc);
1849
1850 imx_data->actual_clock = host->mmc->actual_clock;
1851 esdhc_pltfm_set_clock(host, 0);
1852 clk_disable_unprepare(imx_data->clk_per);
1853 clk_disable_unprepare(imx_data->clk_ipg);
1854 clk_disable_unprepare(imx_data->clk_ahb);
1855
1856 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1857 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1858
1859 return ret;
1860}
1861
1862static int sdhci_esdhc_runtime_resume(struct device *dev)
1863{
1864 struct sdhci_host *host = dev_get_drvdata(dev);
1865 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1866 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1867 int err;
1868
1869 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1870 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1871
1872 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1873 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1874
1875 err = clk_prepare_enable(imx_data->clk_ahb);
1876 if (err)
1877 goto remove_pm_qos_request;
1878
1879 err = clk_prepare_enable(imx_data->clk_per);
1880 if (err)
1881 goto disable_ahb_clk;
1882
1883 err = clk_prepare_enable(imx_data->clk_ipg);
1884 if (err)
1885 goto disable_per_clk;
1886
1887 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1888
1889 err = sdhci_runtime_resume_host(host, 0);
1890 if (err)
1891 goto disable_ipg_clk;
1892
1893 if (host->mmc->caps2 & MMC_CAP2_CQE)
1894 err = cqhci_resume(host->mmc);
1895
1896 return err;
1897
1898disable_ipg_clk:
1899 clk_disable_unprepare(imx_data->clk_ipg);
1900disable_per_clk:
1901 clk_disable_unprepare(imx_data->clk_per);
1902disable_ahb_clk:
1903 clk_disable_unprepare(imx_data->clk_ahb);
1904remove_pm_qos_request:
1905 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1906 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1907 return err;
1908}
1909#endif
1910
1911static const struct dev_pm_ops sdhci_esdhc_pmops = {
1912 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1913 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1914 sdhci_esdhc_runtime_resume, NULL)
1915};
1916
1917static struct platform_driver sdhci_esdhc_imx_driver = {
1918 .driver = {
1919 .name = "sdhci-esdhc-imx",
1920 .of_match_table = imx_esdhc_dt_ids,
1921 .pm = &sdhci_esdhc_pmops,
1922 },
1923 .id_table = imx_esdhc_devtype,
1924 .probe = sdhci_esdhc_imx_probe,
1925 .remove = sdhci_esdhc_imx_remove,
1926};
1927
1928module_platform_driver(sdhci_esdhc_imx_driver);
1929
1930MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1931MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1932MODULE_LICENSE("GPL v2");
1933