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12#include <linux/spinlock.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/mmc-sdhci-s3c.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_gpio.h>
24#include <linux/pm.h>
25#include <linux/pm_runtime.h>
26
27#include <linux/mmc/host.h>
28
29#include "sdhci.h"
30
31#define MAX_BUS_CLK (4)
32
33#define S3C_SDHCI_CONTROL2 (0x80)
34#define S3C_SDHCI_CONTROL3 (0x84)
35#define S3C64XX_SDHCI_CONTROL4 (0x8C)
36
37#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
38#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
39#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
40#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
41
42#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
43#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
44#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
45
46#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
47#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
48#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
49
50#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
51#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
52#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
53#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
54#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
55
56#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
57#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
58#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
59#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
60#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
61#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
62
63#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
64#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
65#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
66
67#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
68#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
69#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
70#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
71#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
72
73#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
74#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
75#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
76#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
77
78#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
79#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
80#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
81
82#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
83#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
84#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
85
86#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
89
90#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
91#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
92#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
93
94#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
98#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
99#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
100
101#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
102
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115
116struct sdhci_s3c {
117 struct sdhci_host *host;
118 struct platform_device *pdev;
119 struct resource *ioarea;
120 struct s3c_sdhci_platdata *pdata;
121 int cur_clk;
122 int ext_cd_irq;
123
124 struct clk *clk_io;
125 struct clk *clk_bus[MAX_BUS_CLK];
126 unsigned long clk_rates[MAX_BUS_CLK];
127
128 bool no_divider;
129};
130
131
132
133
134
135
136
137
138
139
140struct sdhci_s3c_drv_data {
141 unsigned int sdhci_quirks;
142 bool no_divider;
143};
144
145static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
146{
147 return sdhci_priv(host);
148}
149
150
151
152
153
154
155
156static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
157{
158 struct sdhci_s3c *ourhost = to_s3c(host);
159 unsigned long rate, max = 0;
160 int src;
161
162 for (src = 0; src < MAX_BUS_CLK; src++) {
163 rate = ourhost->clk_rates[src];
164 if (rate > max)
165 max = rate;
166 }
167
168 return max;
169}
170
171
172
173
174
175
176
177static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
178 unsigned int src,
179 unsigned int wanted)
180{
181 unsigned long rate;
182 struct clk *clksrc = ourhost->clk_bus[src];
183 int shift;
184
185 if (IS_ERR(clksrc))
186 return UINT_MAX;
187
188
189
190
191
192 if (ourhost->no_divider) {
193 rate = clk_round_rate(clksrc, wanted);
194 return wanted - rate;
195 }
196
197 rate = ourhost->clk_rates[src];
198
199 for (shift = 0; shift <= 8; ++shift) {
200 if ((rate >> shift) <= wanted)
201 break;
202 }
203
204 if (shift > 8) {
205 dev_dbg(&ourhost->pdev->dev,
206 "clk %d: rate %ld, min rate %lu > wanted %u\n",
207 src, rate, rate / 256, wanted);
208 return UINT_MAX;
209 }
210
211 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
212 src, rate, wanted, rate >> shift);
213
214 return wanted - (rate >> shift);
215}
216
217
218
219
220
221
222
223
224
225static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
226{
227 struct sdhci_s3c *ourhost = to_s3c(host);
228 unsigned int best = UINT_MAX;
229 unsigned int delta;
230 int best_src = 0;
231 int src;
232 u32 ctrl;
233
234 host->mmc->actual_clock = 0;
235
236
237 if (clock == 0) {
238 sdhci_set_clock(host, clock);
239 return;
240 }
241
242 for (src = 0; src < MAX_BUS_CLK; src++) {
243 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
244 if (delta < best) {
245 best = delta;
246 best_src = src;
247 }
248 }
249
250 dev_dbg(&ourhost->pdev->dev,
251 "selected source %d, clock %d, delta %d\n",
252 best_src, clock, best);
253
254
255 if (ourhost->cur_clk != best_src) {
256 struct clk *clk = ourhost->clk_bus[best_src];
257
258 clk_prepare_enable(clk);
259 if (ourhost->cur_clk >= 0)
260 clk_disable_unprepare(
261 ourhost->clk_bus[ourhost->cur_clk]);
262
263 ourhost->cur_clk = best_src;
264 host->max_clk = ourhost->clk_rates[best_src];
265 }
266
267
268 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
269
270 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
271 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
272 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
273 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
274
275
276 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
277 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
278
279 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
280 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
281 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
282 S3C_SDHCI_CTRL2_ENFBCLKRX |
283 S3C_SDHCI_CTRL2_DFCNT_NONE |
284 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
285 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
286
287
288 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
289 if (clock < 25 * 1000000)
290 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
291 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
292
293 sdhci_set_clock(host, clock);
294}
295
296
297
298
299
300
301
302
303
304
305static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
306{
307 struct sdhci_s3c *ourhost = to_s3c(host);
308 unsigned long rate, min = ULONG_MAX;
309 int src;
310
311 for (src = 0; src < MAX_BUS_CLK; src++) {
312 rate = ourhost->clk_rates[src] / 256;
313 if (!rate)
314 continue;
315 if (rate < min)
316 min = rate;
317 }
318
319 return min;
320}
321
322
323static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
324{
325 struct sdhci_s3c *ourhost = to_s3c(host);
326 unsigned long rate, max = 0;
327 int src;
328
329 for (src = 0; src < MAX_BUS_CLK; src++) {
330 struct clk *clk;
331
332 clk = ourhost->clk_bus[src];
333 if (IS_ERR(clk))
334 continue;
335
336 rate = clk_round_rate(clk, ULONG_MAX);
337 if (rate > max)
338 max = rate;
339 }
340
341 return max;
342}
343
344
345static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
346{
347 struct sdhci_s3c *ourhost = to_s3c(host);
348 unsigned long rate, min = ULONG_MAX;
349 int src;
350
351 for (src = 0; src < MAX_BUS_CLK; src++) {
352 struct clk *clk;
353
354 clk = ourhost->clk_bus[src];
355 if (IS_ERR(clk))
356 continue;
357
358 rate = clk_round_rate(clk, 0);
359 if (rate < min)
360 min = rate;
361 }
362
363 return min;
364}
365
366
367static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
368{
369 struct sdhci_s3c *ourhost = to_s3c(host);
370 struct device *dev = &ourhost->pdev->dev;
371 unsigned long timeout;
372 u16 clk = 0;
373 int ret;
374
375 host->mmc->actual_clock = 0;
376
377
378 if (clock == 0) {
379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
380 return;
381 }
382
383 sdhci_s3c_set_clock(host, clock);
384
385
386 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
387 clk &= ~SDHCI_CLOCK_CARD_EN;
388 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
389
390 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
391 if (ret != 0) {
392 dev_err(dev, "%s: failed to set clock rate %uHz\n",
393 mmc_hostname(host->mmc), clock);
394 return;
395 }
396
397 clk = SDHCI_CLOCK_INT_EN;
398 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
399
400
401 timeout = 20;
402 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
403 & SDHCI_CLOCK_INT_STABLE)) {
404 if (timeout == 0) {
405 dev_err(dev, "%s: Internal clock never stabilised.\n",
406 mmc_hostname(host->mmc));
407 return;
408 }
409 timeout--;
410 mdelay(1);
411 }
412
413 clk |= SDHCI_CLOCK_CARD_EN;
414 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
415}
416
417static struct sdhci_ops sdhci_s3c_ops = {
418 .get_max_clock = sdhci_s3c_get_max_clk,
419 .set_clock = sdhci_s3c_set_clock,
420 .get_min_clock = sdhci_s3c_get_min_clock,
421 .set_bus_width = sdhci_set_bus_width,
422 .reset = sdhci_reset,
423 .set_uhs_signaling = sdhci_set_uhs_signaling,
424};
425
426#ifdef CONFIG_OF
427static int sdhci_s3c_parse_dt(struct device *dev,
428 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
429{
430 struct device_node *node = dev->of_node;
431 u32 max_width;
432
433
434 if (of_property_read_u32(node, "bus-width", &max_width))
435 max_width = 1;
436 pdata->max_width = max_width;
437
438
439 if (of_get_property(node, "broken-cd", NULL)) {
440 pdata->cd_type = S3C_SDHCI_CD_NONE;
441 return 0;
442 }
443
444 if (of_get_property(node, "non-removable", NULL)) {
445 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
446 return 0;
447 }
448
449 if (of_get_named_gpio(node, "cd-gpios", 0))
450 return 0;
451
452
453 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
454 return 0;
455}
456#else
457static int sdhci_s3c_parse_dt(struct device *dev,
458 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
459{
460 return -EINVAL;
461}
462#endif
463
464static const struct of_device_id sdhci_s3c_dt_match[];
465
466static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
467 struct platform_device *pdev)
468{
469#ifdef CONFIG_OF
470 if (pdev->dev.of_node) {
471 const struct of_device_id *match;
472 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
473 return (struct sdhci_s3c_drv_data *)match->data;
474 }
475#endif
476 return (struct sdhci_s3c_drv_data *)
477 platform_get_device_id(pdev)->driver_data;
478}
479
480static int sdhci_s3c_probe(struct platform_device *pdev)
481{
482 struct s3c_sdhci_platdata *pdata;
483 struct sdhci_s3c_drv_data *drv_data;
484 struct device *dev = &pdev->dev;
485 struct sdhci_host *host;
486 struct sdhci_s3c *sc;
487 int ret, irq, ptr, clks;
488
489 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
490 dev_err(dev, "no device data specified\n");
491 return -ENOENT;
492 }
493
494 irq = platform_get_irq(pdev, 0);
495 if (irq < 0)
496 return irq;
497
498 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
499 if (IS_ERR(host)) {
500 dev_err(dev, "sdhci_alloc_host() failed\n");
501 return PTR_ERR(host);
502 }
503 sc = sdhci_priv(host);
504
505 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
506 if (!pdata) {
507 ret = -ENOMEM;
508 goto err_pdata_io_clk;
509 }
510
511 if (pdev->dev.of_node) {
512 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
513 if (ret)
514 goto err_pdata_io_clk;
515 } else {
516 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
517 }
518
519 drv_data = sdhci_s3c_get_driver_data(pdev);
520
521 sc->host = host;
522 sc->pdev = pdev;
523 sc->pdata = pdata;
524 sc->cur_clk = -1;
525
526 platform_set_drvdata(pdev, host);
527
528 sc->clk_io = devm_clk_get(dev, "hsmmc");
529 if (IS_ERR(sc->clk_io)) {
530 dev_err(dev, "failed to get io clock\n");
531 ret = PTR_ERR(sc->clk_io);
532 goto err_pdata_io_clk;
533 }
534
535
536 clk_prepare_enable(sc->clk_io);
537
538 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
539 char name[14];
540
541 snprintf(name, 14, "mmc_busclk.%d", ptr);
542 sc->clk_bus[ptr] = devm_clk_get(dev, name);
543 if (IS_ERR(sc->clk_bus[ptr]))
544 continue;
545
546 clks++;
547 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
548
549 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
550 ptr, name, sc->clk_rates[ptr]);
551 }
552
553 if (clks == 0) {
554 dev_err(dev, "failed to find any bus clocks\n");
555 ret = -ENOENT;
556 goto err_no_busclks;
557 }
558
559 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
560 if (IS_ERR(host->ioaddr)) {
561 ret = PTR_ERR(host->ioaddr);
562 goto err_req_regs;
563 }
564
565
566 if (pdata->cfg_gpio)
567 pdata->cfg_gpio(pdev, pdata->max_width);
568
569 host->hw_name = "samsung-hsmmc";
570 host->ops = &sdhci_s3c_ops;
571 host->quirks = 0;
572 host->quirks2 = 0;
573 host->irq = irq;
574
575
576 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
577 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
578 if (drv_data) {
579 host->quirks |= drv_data->sdhci_quirks;
580 sc->no_divider = drv_data->no_divider;
581 }
582
583#ifndef CONFIG_MMC_SDHCI_S3C_DMA
584
585
586
587 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
588
589#endif
590
591
592
593
594 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
595
596
597 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
598
599
600 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
601
602 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
603 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
604 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
605
606 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
607 host->mmc->caps = MMC_CAP_NONREMOVABLE;
608
609 switch (pdata->max_width) {
610 case 8:
611 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
612 fallthrough;
613 case 4:
614 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
615 break;
616 }
617
618 if (pdata->pm_caps)
619 host->mmc->pm_caps |= pdata->pm_caps;
620
621 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
622 SDHCI_QUIRK_32BIT_DMA_SIZE);
623
624
625 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
626
627
628
629
630
631 if (sc->no_divider) {
632 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
633 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
634 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
635 }
636
637
638 if (pdata->host_caps)
639 host->mmc->caps |= pdata->host_caps;
640
641 if (pdata->host_caps2)
642 host->mmc->caps2 |= pdata->host_caps2;
643
644 pm_runtime_enable(&pdev->dev);
645 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
646 pm_runtime_use_autosuspend(&pdev->dev);
647 pm_suspend_ignore_children(&pdev->dev, 1);
648
649 ret = mmc_of_parse(host->mmc);
650 if (ret)
651 goto err_req_regs;
652
653 ret = sdhci_add_host(host);
654 if (ret)
655 goto err_req_regs;
656
657#ifdef CONFIG_PM
658 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
659 clk_disable_unprepare(sc->clk_io);
660#endif
661 return 0;
662
663 err_req_regs:
664 pm_runtime_disable(&pdev->dev);
665
666 err_no_busclks:
667 clk_disable_unprepare(sc->clk_io);
668
669 err_pdata_io_clk:
670 sdhci_free_host(host);
671
672 return ret;
673}
674
675static int sdhci_s3c_remove(struct platform_device *pdev)
676{
677 struct sdhci_host *host = platform_get_drvdata(pdev);
678 struct sdhci_s3c *sc = sdhci_priv(host);
679
680 if (sc->ext_cd_irq)
681 free_irq(sc->ext_cd_irq, sc);
682
683#ifdef CONFIG_PM
684 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
685 clk_prepare_enable(sc->clk_io);
686#endif
687 sdhci_remove_host(host, 1);
688
689 pm_runtime_dont_use_autosuspend(&pdev->dev);
690 pm_runtime_disable(&pdev->dev);
691
692 clk_disable_unprepare(sc->clk_io);
693
694 sdhci_free_host(host);
695
696 return 0;
697}
698
699#ifdef CONFIG_PM_SLEEP
700static int sdhci_s3c_suspend(struct device *dev)
701{
702 struct sdhci_host *host = dev_get_drvdata(dev);
703
704 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
705 mmc_retune_needed(host->mmc);
706
707 return sdhci_suspend_host(host);
708}
709
710static int sdhci_s3c_resume(struct device *dev)
711{
712 struct sdhci_host *host = dev_get_drvdata(dev);
713
714 return sdhci_resume_host(host);
715}
716#endif
717
718#ifdef CONFIG_PM
719static int sdhci_s3c_runtime_suspend(struct device *dev)
720{
721 struct sdhci_host *host = dev_get_drvdata(dev);
722 struct sdhci_s3c *ourhost = to_s3c(host);
723 struct clk *busclk = ourhost->clk_io;
724 int ret;
725
726 ret = sdhci_runtime_suspend_host(host);
727
728 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
729 mmc_retune_needed(host->mmc);
730
731 if (ourhost->cur_clk >= 0)
732 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
733 clk_disable_unprepare(busclk);
734 return ret;
735}
736
737static int sdhci_s3c_runtime_resume(struct device *dev)
738{
739 struct sdhci_host *host = dev_get_drvdata(dev);
740 struct sdhci_s3c *ourhost = to_s3c(host);
741 struct clk *busclk = ourhost->clk_io;
742 int ret;
743
744 clk_prepare_enable(busclk);
745 if (ourhost->cur_clk >= 0)
746 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
747 ret = sdhci_runtime_resume_host(host, 0);
748 return ret;
749}
750#endif
751
752static const struct dev_pm_ops sdhci_s3c_pmops = {
753 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
754 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
755 NULL)
756};
757
758static const struct platform_device_id sdhci_s3c_driver_ids[] = {
759 {
760 .name = "s3c-sdhci",
761 .driver_data = (kernel_ulong_t)NULL,
762 },
763 { }
764};
765MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
766
767#ifdef CONFIG_OF
768static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
769 .no_divider = true,
770};
771
772static const struct of_device_id sdhci_s3c_dt_match[] = {
773 { .compatible = "samsung,s3c6410-sdhci", },
774 { .compatible = "samsung,exynos4210-sdhci",
775 .data = &exynos4_sdhci_drv_data },
776 {},
777};
778MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
779#endif
780
781static struct platform_driver sdhci_s3c_driver = {
782 .probe = sdhci_s3c_probe,
783 .remove = sdhci_s3c_remove,
784 .id_table = sdhci_s3c_driver_ids,
785 .driver = {
786 .name = "s3c-sdhci",
787 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
788 .pm = &sdhci_s3c_pmops,
789 },
790};
791
792module_platform_driver(sdhci_s3c_driver);
793
794MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
795MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
796MODULE_LICENSE("GPL v2");
797MODULE_ALIAS("platform:s3c-sdhci");
798