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8
9
10#define pr_fmt(fmt) "nand-s3c2410: " fmt
11
12#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
13#define DEBUG
14#endif
15
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/kernel.h>
19#include <linux/string.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/platform_device.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/slab.h>
26#include <linux/clk.h>
27#include <linux/cpufreq.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30
31#include <linux/mtd/mtd.h>
32#include <linux/mtd/rawnand.h>
33#include <linux/mtd/nand_ecc.h>
34#include <linux/mtd/partitions.h>
35
36#include <linux/platform_data/mtd-nand-s3c2410.h>
37
38#define S3C2410_NFREG(x) (x)
39
40#define S3C2410_NFCONF S3C2410_NFREG(0x00)
41#define S3C2410_NFCMD S3C2410_NFREG(0x04)
42#define S3C2410_NFADDR S3C2410_NFREG(0x08)
43#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
44#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
45#define S3C2410_NFECC S3C2410_NFREG(0x14)
46#define S3C2440_NFCONT S3C2410_NFREG(0x04)
47#define S3C2440_NFCMD S3C2410_NFREG(0x08)
48#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
49#define S3C2440_NFDATA S3C2410_NFREG(0x10)
50#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
51#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
52#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
53#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
54#define S3C2410_NFCONF_EN (1<<15)
55#define S3C2410_NFCONF_INITECC (1<<12)
56#define S3C2410_NFCONF_nFCE (1<<11)
57#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
58#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
59#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
60#define S3C2410_NFSTAT_BUSY (1<<0)
61#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
62#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
63#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
64#define S3C2440_NFCONT_INITECC (1<<4)
65#define S3C2440_NFCONT_nFCE (1<<1)
66#define S3C2440_NFCONT_ENABLE (1<<0)
67#define S3C2440_NFSTAT_READY (1<<0)
68#define S3C2412_NFCONF_NANDBOOT (1<<31)
69#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
70#define S3C2412_NFCONT_nFCE0 (1<<1)
71#define S3C2412_NFSTAT_READY (1<<0)
72
73
74
75static int s3c2410_ooblayout_ecc(struct mtd_info *mtd, int section,
76 struct mtd_oob_region *oobregion)
77{
78 if (section)
79 return -ERANGE;
80
81 oobregion->offset = 0;
82 oobregion->length = 3;
83
84 return 0;
85}
86
87static int s3c2410_ooblayout_free(struct mtd_info *mtd, int section,
88 struct mtd_oob_region *oobregion)
89{
90 if (section)
91 return -ERANGE;
92
93 oobregion->offset = 8;
94 oobregion->length = 8;
95
96 return 0;
97}
98
99static const struct mtd_ooblayout_ops s3c2410_ooblayout_ops = {
100 .ecc = s3c2410_ooblayout_ecc,
101 .free = s3c2410_ooblayout_free,
102};
103
104
105
106struct s3c2410_nand_info;
107
108
109
110
111
112
113
114
115struct s3c2410_nand_mtd {
116 struct nand_chip chip;
117 struct s3c2410_nand_set *set;
118 struct s3c2410_nand_info *info;
119};
120
121enum s3c_cpu_type {
122 TYPE_S3C2410,
123 TYPE_S3C2412,
124 TYPE_S3C2440,
125};
126
127enum s3c_nand_clk_state {
128 CLOCK_DISABLE = 0,
129 CLOCK_ENABLE,
130 CLOCK_SUSPEND,
131};
132
133
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147
148
149
150struct s3c2410_nand_info {
151
152 struct nand_controller controller;
153 struct s3c2410_nand_mtd *mtds;
154 struct s3c2410_platform_nand *platform;
155
156
157 struct device *device;
158 struct clk *clk;
159 void __iomem *regs;
160 void __iomem *sel_reg;
161 int sel_bit;
162 int mtd_count;
163 unsigned long save_sel;
164 unsigned long clk_rate;
165 enum s3c_nand_clk_state clk_state;
166
167 enum s3c_cpu_type cpu_type;
168
169#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
170 struct notifier_block freq_transition;
171#endif
172};
173
174struct s3c24XX_nand_devtype_data {
175 enum s3c_cpu_type type;
176};
177
178static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
179 .type = TYPE_S3C2410,
180};
181
182static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
183 .type = TYPE_S3C2412,
184};
185
186static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
187 .type = TYPE_S3C2440,
188};
189
190
191
192static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
193{
194 return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd,
195 chip);
196}
197
198static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
199{
200 return s3c2410_nand_mtd_toours(mtd)->info;
201}
202
203static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
204{
205 return platform_get_drvdata(dev);
206}
207
208static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
209{
210 return dev_get_platdata(&dev->dev);
211}
212
213static inline int allow_clk_suspend(struct s3c2410_nand_info *info)
214{
215#ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
216 return 1;
217#else
218 return 0;
219#endif
220}
221
222
223
224
225
226
227static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info,
228 enum s3c_nand_clk_state new_state)
229{
230 if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND)
231 return;
232
233 if (info->clk_state == CLOCK_ENABLE) {
234 if (new_state != CLOCK_ENABLE)
235 clk_disable_unprepare(info->clk);
236 } else {
237 if (new_state == CLOCK_ENABLE)
238 clk_prepare_enable(info->clk);
239 }
240
241 info->clk_state = new_state;
242}
243
244
245
246#define NS_IN_KHZ 1000000
247
248
249
250
251
252
253
254
255
256static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
257{
258 int result;
259
260 result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ);
261
262 pr_debug("result %d from %ld, %d\n", result, clk, wanted);
263
264 if (result > max) {
265 pr_err("%d ns is too big for current clock rate %ld\n",
266 wanted, clk);
267 return -1;
268 }
269
270 if (result < 1)
271 result = 1;
272
273 return result;
274}
275
276#define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
277
278
279
280
281
282
283
284
285
286
287
288static int s3c2410_nand_setrate(struct s3c2410_nand_info *info)
289{
290 struct s3c2410_platform_nand *plat = info->platform;
291 int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
292 int tacls, twrph0, twrph1;
293 unsigned long clkrate = clk_get_rate(info->clk);
294 unsigned long set, cfg, mask;
295 unsigned long flags;
296
297
298
299 info->clk_rate = clkrate;
300 clkrate /= 1000;
301
302 if (plat != NULL) {
303 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
304 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
305 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
306 } else {
307
308 tacls = tacls_max;
309 twrph0 = 8;
310 twrph1 = 8;
311 }
312
313 if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
314 dev_err(info->device, "cannot get suitable timings\n");
315 return -EINVAL;
316 }
317
318 dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
319 tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
320 twrph1, to_ns(twrph1, clkrate));
321
322 switch (info->cpu_type) {
323 case TYPE_S3C2410:
324 mask = (S3C2410_NFCONF_TACLS(3) |
325 S3C2410_NFCONF_TWRPH0(7) |
326 S3C2410_NFCONF_TWRPH1(7));
327 set = S3C2410_NFCONF_EN;
328 set |= S3C2410_NFCONF_TACLS(tacls - 1);
329 set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
330 set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
331 break;
332
333 case TYPE_S3C2440:
334 case TYPE_S3C2412:
335 mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) |
336 S3C2440_NFCONF_TWRPH0(7) |
337 S3C2440_NFCONF_TWRPH1(7));
338
339 set = S3C2440_NFCONF_TACLS(tacls - 1);
340 set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
341 set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
342 break;
343
344 default:
345 BUG();
346 }
347
348 local_irq_save(flags);
349
350 cfg = readl(info->regs + S3C2410_NFCONF);
351 cfg &= ~mask;
352 cfg |= set;
353 writel(cfg, info->regs + S3C2410_NFCONF);
354
355 local_irq_restore(flags);
356
357 dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
358
359 return 0;
360}
361
362
363
364
365
366
367
368
369static int s3c2410_nand_inithw(struct s3c2410_nand_info *info)
370{
371 int ret;
372
373 ret = s3c2410_nand_setrate(info);
374 if (ret < 0)
375 return ret;
376
377 switch (info->cpu_type) {
378 case TYPE_S3C2410:
379 default:
380 break;
381
382 case TYPE_S3C2440:
383 case TYPE_S3C2412:
384
385
386 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
387 }
388
389 return 0;
390}
391
392
393
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395
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397
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400
401
402
403
404
405static void s3c2410_nand_select_chip(struct nand_chip *this, int chip)
406{
407 struct s3c2410_nand_info *info;
408 struct s3c2410_nand_mtd *nmtd;
409 unsigned long cur;
410
411 nmtd = nand_get_controller_data(this);
412 info = nmtd->info;
413
414 if (chip != -1)
415 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
416
417 cur = readl(info->sel_reg);
418
419 if (chip == -1) {
420 cur |= info->sel_bit;
421 } else {
422 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
423 dev_err(info->device, "invalid chip %d\n", chip);
424 return;
425 }
426
427 if (info->platform != NULL) {
428 if (info->platform->select_chip != NULL)
429 (info->platform->select_chip) (nmtd->set, chip);
430 }
431
432 cur &= ~info->sel_bit;
433 }
434
435 writel(cur, info->sel_reg);
436
437 if (chip == -1)
438 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
439}
440
441
442
443
444
445
446static void s3c2410_nand_hwcontrol(struct nand_chip *chip, int cmd,
447 unsigned int ctrl)
448{
449 struct mtd_info *mtd = nand_to_mtd(chip);
450 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
451
452 if (cmd == NAND_CMD_NONE)
453 return;
454
455 if (ctrl & NAND_CLE)
456 writeb(cmd, info->regs + S3C2410_NFCMD);
457 else
458 writeb(cmd, info->regs + S3C2410_NFADDR);
459}
460
461
462
463static void s3c2440_nand_hwcontrol(struct nand_chip *chip, int cmd,
464 unsigned int ctrl)
465{
466 struct mtd_info *mtd = nand_to_mtd(chip);
467 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
468
469 if (cmd == NAND_CMD_NONE)
470 return;
471
472 if (ctrl & NAND_CLE)
473 writeb(cmd, info->regs + S3C2440_NFCMD);
474 else
475 writeb(cmd, info->regs + S3C2440_NFADDR);
476}
477
478
479
480
481
482
483static int s3c2410_nand_devready(struct nand_chip *chip)
484{
485 struct mtd_info *mtd = nand_to_mtd(chip);
486 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
487 return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
488}
489
490static int s3c2440_nand_devready(struct nand_chip *chip)
491{
492 struct mtd_info *mtd = nand_to_mtd(chip);
493 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
494 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
495}
496
497static int s3c2412_nand_devready(struct nand_chip *chip)
498{
499 struct mtd_info *mtd = nand_to_mtd(chip);
500 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
501 return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
502}
503
504
505
506static int s3c2410_nand_correct_data(struct nand_chip *chip, u_char *dat,
507 u_char *read_ecc, u_char *calc_ecc)
508{
509 struct mtd_info *mtd = nand_to_mtd(chip);
510 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
511 unsigned int diff0, diff1, diff2;
512 unsigned int bit, byte;
513
514 pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
515
516 diff0 = read_ecc[0] ^ calc_ecc[0];
517 diff1 = read_ecc[1] ^ calc_ecc[1];
518 diff2 = read_ecc[2] ^ calc_ecc[2];
519
520 pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n",
521 __func__, 3, read_ecc, 3, calc_ecc,
522 diff0, diff1, diff2);
523
524 if (diff0 == 0 && diff1 == 0 && diff2 == 0)
525 return 0;
526
527
528
529
530
531 if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff
532 && info->platform->ignore_unset_ecc)
533 return 0;
534
535
536
537
538 if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
539 ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
540 ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
541
542
543 bit = ((diff2 >> 3) & 1) |
544 ((diff2 >> 4) & 2) |
545 ((diff2 >> 5) & 4);
546
547
548
549 byte = ((diff2 << 7) & 0x100) |
550 ((diff1 << 0) & 0x80) |
551 ((diff1 << 1) & 0x40) |
552 ((diff1 << 2) & 0x20) |
553 ((diff1 << 3) & 0x10) |
554 ((diff0 >> 4) & 0x08) |
555 ((diff0 >> 3) & 0x04) |
556 ((diff0 >> 2) & 0x02) |
557 ((diff0 >> 1) & 0x01);
558
559 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
560 bit, byte);
561
562 dat[byte] ^= (1 << bit);
563 return 1;
564 }
565
566
567
568
569
570 diff0 |= (diff1 << 8);
571 diff0 |= (diff2 << 16);
572
573
574 if ((diff0 & (diff0 - 1)) == 0)
575 return 1;
576
577 return -1;
578}
579
580
581
582
583
584
585
586static void s3c2410_nand_enable_hwecc(struct nand_chip *chip, int mode)
587{
588 struct s3c2410_nand_info *info;
589 unsigned long ctrl;
590
591 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
592 ctrl = readl(info->regs + S3C2410_NFCONF);
593 ctrl |= S3C2410_NFCONF_INITECC;
594 writel(ctrl, info->regs + S3C2410_NFCONF);
595}
596
597static void s3c2412_nand_enable_hwecc(struct nand_chip *chip, int mode)
598{
599 struct s3c2410_nand_info *info;
600 unsigned long ctrl;
601
602 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
603 ctrl = readl(info->regs + S3C2440_NFCONT);
604 writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC,
605 info->regs + S3C2440_NFCONT);
606}
607
608static void s3c2440_nand_enable_hwecc(struct nand_chip *chip, int mode)
609{
610 struct s3c2410_nand_info *info;
611 unsigned long ctrl;
612
613 info = s3c2410_nand_mtd_toinfo(nand_to_mtd(chip));
614 ctrl = readl(info->regs + S3C2440_NFCONT);
615 writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
616}
617
618static int s3c2410_nand_calculate_ecc(struct nand_chip *chip,
619 const u_char *dat, u_char *ecc_code)
620{
621 struct mtd_info *mtd = nand_to_mtd(chip);
622 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
623
624 ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
625 ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
626 ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
627
628 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
629
630 return 0;
631}
632
633static int s3c2412_nand_calculate_ecc(struct nand_chip *chip,
634 const u_char *dat, u_char *ecc_code)
635{
636 struct mtd_info *mtd = nand_to_mtd(chip);
637 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
638 unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
639
640 ecc_code[0] = ecc;
641 ecc_code[1] = ecc >> 8;
642 ecc_code[2] = ecc >> 16;
643
644 pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code);
645
646 return 0;
647}
648
649static int s3c2440_nand_calculate_ecc(struct nand_chip *chip,
650 const u_char *dat, u_char *ecc_code)
651{
652 struct mtd_info *mtd = nand_to_mtd(chip);
653 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
654 unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
655
656 ecc_code[0] = ecc;
657 ecc_code[1] = ecc >> 8;
658 ecc_code[2] = ecc >> 16;
659
660 pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff);
661
662 return 0;
663}
664
665
666
667
668
669static void s3c2410_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
670{
671 readsb(this->legacy.IO_ADDR_R, buf, len);
672}
673
674static void s3c2440_nand_read_buf(struct nand_chip *this, u_char *buf, int len)
675{
676 struct mtd_info *mtd = nand_to_mtd(this);
677 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
678
679 readsl(info->regs + S3C2440_NFDATA, buf, len >> 2);
680
681
682 if (len & 3) {
683 buf += len & ~3;
684
685 for (; len & 3; len--)
686 *buf++ = readb(info->regs + S3C2440_NFDATA);
687 }
688}
689
690static void s3c2410_nand_write_buf(struct nand_chip *this, const u_char *buf,
691 int len)
692{
693 writesb(this->legacy.IO_ADDR_W, buf, len);
694}
695
696static void s3c2440_nand_write_buf(struct nand_chip *this, const u_char *buf,
697 int len)
698{
699 struct mtd_info *mtd = nand_to_mtd(this);
700 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
701
702 writesl(info->regs + S3C2440_NFDATA, buf, len >> 2);
703
704
705 if (len & 3) {
706 buf += len & ~3;
707
708 for (; len & 3; len--, buf++)
709 writeb(*buf, info->regs + S3C2440_NFDATA);
710 }
711}
712
713
714
715#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
716
717static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb,
718 unsigned long val, void *data)
719{
720 struct s3c2410_nand_info *info;
721 unsigned long newclk;
722
723 info = container_of(nb, struct s3c2410_nand_info, freq_transition);
724 newclk = clk_get_rate(info->clk);
725
726 if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) ||
727 (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) {
728 s3c2410_nand_setrate(info);
729 }
730
731 return 0;
732}
733
734static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
735{
736 info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition;
737
738 return cpufreq_register_notifier(&info->freq_transition,
739 CPUFREQ_TRANSITION_NOTIFIER);
740}
741
742static inline void
743s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
744{
745 cpufreq_unregister_notifier(&info->freq_transition,
746 CPUFREQ_TRANSITION_NOTIFIER);
747}
748
749#else
750static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info)
751{
752 return 0;
753}
754
755static inline void
756s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info)
757{
758}
759#endif
760
761
762
763static int s3c24xx_nand_remove(struct platform_device *pdev)
764{
765 struct s3c2410_nand_info *info = to_nand_info(pdev);
766
767 if (info == NULL)
768 return 0;
769
770 s3c2410_nand_cpufreq_deregister(info);
771
772
773
774
775
776 if (info->mtds != NULL) {
777 struct s3c2410_nand_mtd *ptr = info->mtds;
778 int mtdno;
779
780 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
781 pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
782 WARN_ON(mtd_device_unregister(nand_to_mtd(&ptr->chip)));
783 nand_cleanup(&ptr->chip);
784 }
785 }
786
787
788
789 if (!IS_ERR(info->clk))
790 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
791
792 return 0;
793}
794
795static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
796 struct s3c2410_nand_mtd *mtd,
797 struct s3c2410_nand_set *set)
798{
799 if (set) {
800 struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip);
801
802 mtdinfo->name = set->name;
803
804 return mtd_device_register(mtdinfo, set->partitions,
805 set->nr_partitions);
806 }
807
808 return -ENODEV;
809}
810
811static int s3c2410_nand_setup_interface(struct nand_chip *chip, int csline,
812 const struct nand_interface_config *conf)
813{
814 struct mtd_info *mtd = nand_to_mtd(chip);
815 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
816 struct s3c2410_platform_nand *pdata = info->platform;
817 const struct nand_sdr_timings *timings;
818 int tacls;
819
820 timings = nand_get_sdr_timings(conf);
821 if (IS_ERR(timings))
822 return -ENOTSUPP;
823
824 tacls = timings->tCLS_min - timings->tWP_min;
825 if (tacls < 0)
826 tacls = 0;
827
828 pdata->tacls = DIV_ROUND_UP(tacls, 1000);
829 pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
830 pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
831
832 return s3c2410_nand_setrate(info);
833}
834
835
836
837
838
839
840
841
842
843
844
845static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
846 struct s3c2410_nand_mtd *nmtd,
847 struct s3c2410_nand_set *set)
848{
849 struct device_node *np = info->device->of_node;
850 struct nand_chip *chip = &nmtd->chip;
851 void __iomem *regs = info->regs;
852
853 nand_set_flash_node(chip, set->of_node);
854
855 chip->legacy.write_buf = s3c2410_nand_write_buf;
856 chip->legacy.read_buf = s3c2410_nand_read_buf;
857 chip->legacy.select_chip = s3c2410_nand_select_chip;
858 chip->legacy.chip_delay = 50;
859 nand_set_controller_data(chip, nmtd);
860 chip->options = set->options;
861 chip->controller = &info->controller;
862
863
864
865
866
867 if (!np)
868 chip->options |= NAND_KEEP_TIMINGS;
869
870 switch (info->cpu_type) {
871 case TYPE_S3C2410:
872 chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
873 info->sel_reg = regs + S3C2410_NFCONF;
874 info->sel_bit = S3C2410_NFCONF_nFCE;
875 chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol;
876 chip->legacy.dev_ready = s3c2410_nand_devready;
877 break;
878
879 case TYPE_S3C2440:
880 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
881 info->sel_reg = regs + S3C2440_NFCONT;
882 info->sel_bit = S3C2440_NFCONT_nFCE;
883 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
884 chip->legacy.dev_ready = s3c2440_nand_devready;
885 chip->legacy.read_buf = s3c2440_nand_read_buf;
886 chip->legacy.write_buf = s3c2440_nand_write_buf;
887 break;
888
889 case TYPE_S3C2412:
890 chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
891 info->sel_reg = regs + S3C2440_NFCONT;
892 info->sel_bit = S3C2412_NFCONT_nFCE0;
893 chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
894 chip->legacy.dev_ready = s3c2412_nand_devready;
895
896 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
897 dev_info(info->device, "System booted from NAND\n");
898
899 break;
900 }
901
902 chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
903
904 nmtd->info = info;
905 nmtd->set = set;
906
907 chip->ecc.mode = info->platform->ecc_mode;
908
909
910
911
912
913 if (set->flash_bbt)
914 chip->bbt_options |= NAND_BBT_USE_FLASH;
915}
916
917
918
919
920
921
922
923
924
925
926
927static int s3c2410_nand_attach_chip(struct nand_chip *chip)
928{
929 struct mtd_info *mtd = nand_to_mtd(chip);
930 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
931
932 switch (chip->ecc.mode) {
933
934 case NAND_ECC_NONE:
935 dev_info(info->device, "ECC disabled\n");
936 break;
937
938 case NAND_ECC_SOFT:
939
940
941
942
943
944
945 chip->ecc.algo = NAND_ECC_HAMMING;
946 dev_info(info->device, "soft ECC\n");
947 break;
948
949 case NAND_ECC_HW:
950 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
951 chip->ecc.correct = s3c2410_nand_correct_data;
952 chip->ecc.strength = 1;
953
954 switch (info->cpu_type) {
955 case TYPE_S3C2410:
956 chip->ecc.hwctl = s3c2410_nand_enable_hwecc;
957 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
958 break;
959
960 case TYPE_S3C2412:
961 chip->ecc.hwctl = s3c2412_nand_enable_hwecc;
962 chip->ecc.calculate = s3c2412_nand_calculate_ecc;
963 break;
964
965 case TYPE_S3C2440:
966 chip->ecc.hwctl = s3c2440_nand_enable_hwecc;
967 chip->ecc.calculate = s3c2440_nand_calculate_ecc;
968 break;
969 }
970
971 dev_dbg(info->device, "chip %p => page shift %d\n",
972 chip, chip->page_shift);
973
974
975
976 if (chip->page_shift > 10) {
977 chip->ecc.size = 256;
978 chip->ecc.bytes = 3;
979 } else {
980 chip->ecc.size = 512;
981 chip->ecc.bytes = 3;
982 mtd_set_ooblayout(nand_to_mtd(chip),
983 &s3c2410_ooblayout_ops);
984 }
985
986 dev_info(info->device, "hardware ECC\n");
987 break;
988
989 default:
990 dev_err(info->device, "invalid ECC mode!\n");
991 return -EINVAL;
992 }
993
994 if (chip->bbt_options & NAND_BBT_USE_FLASH)
995 chip->options |= NAND_SKIP_BBTSCAN;
996
997 return 0;
998}
999
1000static const struct nand_controller_ops s3c24xx_nand_controller_ops = {
1001 .attach_chip = s3c2410_nand_attach_chip,
1002 .setup_interface = s3c2410_nand_setup_interface,
1003};
1004
1005static const struct of_device_id s3c24xx_nand_dt_ids[] = {
1006 {
1007 .compatible = "samsung,s3c2410-nand",
1008 .data = &s3c2410_nand_devtype_data,
1009 }, {
1010
1011 .compatible = "samsung,s3c2412-nand",
1012 .data = &s3c2412_nand_devtype_data,
1013 }, {
1014 .compatible = "samsung,s3c2440-nand",
1015 .data = &s3c2440_nand_devtype_data,
1016 },
1017 { }
1018};
1019MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
1020
1021static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
1022{
1023 const struct s3c24XX_nand_devtype_data *devtype_data;
1024 struct s3c2410_platform_nand *pdata;
1025 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1026 struct device_node *np = pdev->dev.of_node, *child;
1027 struct s3c2410_nand_set *sets;
1028
1029 devtype_data = of_device_get_match_data(&pdev->dev);
1030 if (!devtype_data)
1031 return -ENODEV;
1032
1033 info->cpu_type = devtype_data->type;
1034
1035 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1036 if (!pdata)
1037 return -ENOMEM;
1038
1039 pdev->dev.platform_data = pdata;
1040
1041 pdata->nr_sets = of_get_child_count(np);
1042 if (!pdata->nr_sets)
1043 return 0;
1044
1045 sets = devm_kcalloc(&pdev->dev, pdata->nr_sets, sizeof(*sets),
1046 GFP_KERNEL);
1047 if (!sets)
1048 return -ENOMEM;
1049
1050 pdata->sets = sets;
1051
1052 for_each_available_child_of_node(np, child) {
1053 sets->name = (char *)child->name;
1054 sets->of_node = child;
1055 sets->nr_chips = 1;
1056
1057 of_node_get(child);
1058
1059 sets++;
1060 }
1061
1062 return 0;
1063}
1064
1065static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
1066{
1067 struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
1068
1069 info->cpu_type = platform_get_device_id(pdev)->driver_data;
1070
1071 return 0;
1072}
1073
1074
1075
1076
1077
1078
1079
1080
1081static int s3c24xx_nand_probe(struct platform_device *pdev)
1082{
1083 struct s3c2410_platform_nand *plat;
1084 struct s3c2410_nand_info *info;
1085 struct s3c2410_nand_mtd *nmtd;
1086 struct s3c2410_nand_set *sets;
1087 struct resource *res;
1088 int err = 0;
1089 int size;
1090 int nr_sets;
1091 int setno;
1092
1093 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1094 if (info == NULL) {
1095 err = -ENOMEM;
1096 goto exit_error;
1097 }
1098
1099 platform_set_drvdata(pdev, info);
1100
1101 nand_controller_init(&info->controller);
1102 info->controller.ops = &s3c24xx_nand_controller_ops;
1103
1104
1105
1106 info->clk = devm_clk_get(&pdev->dev, "nand");
1107 if (IS_ERR(info->clk)) {
1108 dev_err(&pdev->dev, "failed to get clock\n");
1109 err = -ENOENT;
1110 goto exit_error;
1111 }
1112
1113 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1114
1115 if (pdev->dev.of_node)
1116 err = s3c24xx_nand_probe_dt(pdev);
1117 else
1118 err = s3c24xx_nand_probe_pdata(pdev);
1119
1120 if (err)
1121 goto exit_error;
1122
1123 plat = to_nand_plat(pdev);
1124
1125
1126
1127
1128 res = pdev->resource;
1129 size = resource_size(res);
1130
1131 info->device = &pdev->dev;
1132 info->platform = plat;
1133
1134 info->regs = devm_ioremap_resource(&pdev->dev, res);
1135 if (IS_ERR(info->regs)) {
1136 err = PTR_ERR(info->regs);
1137 goto exit_error;
1138 }
1139
1140 dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
1141
1142 if (!plat->sets || plat->nr_sets < 1) {
1143 err = -EINVAL;
1144 goto exit_error;
1145 }
1146
1147 sets = plat->sets;
1148 nr_sets = plat->nr_sets;
1149
1150 info->mtd_count = nr_sets;
1151
1152
1153
1154 size = nr_sets * sizeof(*info->mtds);
1155 info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1156 if (info->mtds == NULL) {
1157 err = -ENOMEM;
1158 goto exit_error;
1159 }
1160
1161
1162
1163 nmtd = info->mtds;
1164
1165 for (setno = 0; setno < nr_sets; setno++, nmtd++, sets++) {
1166 struct mtd_info *mtd = nand_to_mtd(&nmtd->chip);
1167
1168 pr_debug("initialising set %d (%p, info %p)\n",
1169 setno, nmtd, info);
1170
1171 mtd->dev.parent = &pdev->dev;
1172 s3c2410_nand_init_chip(info, nmtd, sets);
1173
1174 err = nand_scan(&nmtd->chip, sets ? sets->nr_chips : 1);
1175 if (err)
1176 goto exit_error;
1177
1178 s3c2410_nand_add_partition(info, nmtd, sets);
1179 }
1180
1181
1182 err = s3c2410_nand_inithw(info);
1183 if (err != 0)
1184 goto exit_error;
1185
1186 err = s3c2410_nand_cpufreq_register(info);
1187 if (err < 0) {
1188 dev_err(&pdev->dev, "failed to init cpufreq support\n");
1189 goto exit_error;
1190 }
1191
1192 if (allow_clk_suspend(info)) {
1193 dev_info(&pdev->dev, "clock idle support enabled\n");
1194 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1195 }
1196
1197 return 0;
1198
1199 exit_error:
1200 s3c24xx_nand_remove(pdev);
1201
1202 if (err == 0)
1203 err = -EINVAL;
1204 return err;
1205}
1206
1207
1208#ifdef CONFIG_PM
1209
1210static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
1211{
1212 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1213
1214 if (info) {
1215 info->save_sel = readl(info->sel_reg);
1216
1217
1218
1219
1220
1221
1222 writel(info->save_sel | info->sel_bit, info->sel_reg);
1223
1224 s3c2410_nand_clk_set_state(info, CLOCK_DISABLE);
1225 }
1226
1227 return 0;
1228}
1229
1230static int s3c24xx_nand_resume(struct platform_device *dev)
1231{
1232 struct s3c2410_nand_info *info = platform_get_drvdata(dev);
1233 unsigned long sel;
1234
1235 if (info) {
1236 s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
1237 s3c2410_nand_inithw(info);
1238
1239
1240
1241 sel = readl(info->sel_reg);
1242 sel &= ~info->sel_bit;
1243 sel |= info->save_sel & info->sel_bit;
1244 writel(sel, info->sel_reg);
1245
1246 s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND);
1247 }
1248
1249 return 0;
1250}
1251
1252#else
1253#define s3c24xx_nand_suspend NULL
1254#define s3c24xx_nand_resume NULL
1255#endif
1256
1257
1258
1259static const struct platform_device_id s3c24xx_driver_ids[] = {
1260 {
1261 .name = "s3c2410-nand",
1262 .driver_data = TYPE_S3C2410,
1263 }, {
1264 .name = "s3c2440-nand",
1265 .driver_data = TYPE_S3C2440,
1266 }, {
1267 .name = "s3c2412-nand",
1268 .driver_data = TYPE_S3C2412,
1269 }, {
1270 .name = "s3c6400-nand",
1271 .driver_data = TYPE_S3C2412,
1272 },
1273 { }
1274};
1275
1276MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1277
1278static struct platform_driver s3c24xx_nand_driver = {
1279 .probe = s3c24xx_nand_probe,
1280 .remove = s3c24xx_nand_remove,
1281 .suspend = s3c24xx_nand_suspend,
1282 .resume = s3c24xx_nand_resume,
1283 .id_table = s3c24xx_driver_ids,
1284 .driver = {
1285 .name = "s3c24xx-nand",
1286 .of_match_table = s3c24xx_nand_dt_ids,
1287 },
1288};
1289
1290module_platform_driver(s3c24xx_nand_driver);
1291
1292MODULE_LICENSE("GPL");
1293MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1294MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
1295