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22#include <linux/module.h>
23#include <linux/bitops.h>
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/rawnand.h>
31#include <linux/mtd/partitions.h>
32#include <linux/of_device.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/swab.h>
36
37#define DRV_NAME "vf610_nfc"
38
39
40#define NFC_FLASH_CMD1 0x3F00
41#define NFC_FLASH_CMD2 0x3F04
42#define NFC_COL_ADDR 0x3F08
43#define NFC_ROW_ADDR 0x3F0c
44#define NFC_ROW_ADDR_INC 0x3F14
45#define NFC_FLASH_STATUS1 0x3F18
46#define NFC_FLASH_STATUS2 0x3F1c
47#define NFC_CACHE_SWAP 0x3F28
48#define NFC_SECTOR_SIZE 0x3F2c
49#define NFC_FLASH_CONFIG 0x3F30
50#define NFC_IRQ_STATUS 0x3F38
51
52
53#define NFC_MAIN_AREA(n) ((n) * 0x1000)
54
55#define PAGE_2K 0x0800
56#define OOB_64 0x0040
57#define OOB_MAX 0x0100
58
59
60#define COMMAND_CMD_BYTE1 BIT(14)
61#define COMMAND_CAR_BYTE1 BIT(13)
62#define COMMAND_CAR_BYTE2 BIT(12)
63#define COMMAND_RAR_BYTE1 BIT(11)
64#define COMMAND_RAR_BYTE2 BIT(10)
65#define COMMAND_RAR_BYTE3 BIT(9)
66#define COMMAND_NADDR_BYTES(x) GENMASK(13, 13 - (x) + 1)
67#define COMMAND_WRITE_DATA BIT(8)
68#define COMMAND_CMD_BYTE2 BIT(7)
69#define COMMAND_RB_HANDSHAKE BIT(6)
70#define COMMAND_READ_DATA BIT(5)
71#define COMMAND_CMD_BYTE3 BIT(4)
72#define COMMAND_READ_STATUS BIT(3)
73#define COMMAND_READ_ID BIT(2)
74
75
76#define ECC_BYPASS 0
77#define ECC_45_BYTE 6
78#define ECC_60_BYTE 7
79
80
81
82
83#define CMD_BYTE2_MASK 0xFF000000
84#define CMD_BYTE2_SHIFT 24
85
86
87#define CMD_BYTE1_MASK 0xFF000000
88#define CMD_BYTE1_SHIFT 24
89#define CMD_CODE_MASK 0x00FFFF00
90#define CMD_CODE_SHIFT 8
91#define BUFNO_MASK 0x00000006
92#define BUFNO_SHIFT 1
93#define START_BIT BIT(0)
94
95
96#define COL_ADDR_MASK 0x0000FFFF
97#define COL_ADDR_SHIFT 0
98#define COL_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos)))
99
100
101#define ROW_ADDR_MASK 0x00FFFFFF
102#define ROW_ADDR_SHIFT 0
103#define ROW_ADDR(pos, val) (((val) & 0xFF) << (8 * (pos)))
104
105#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000
106#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28
107#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000
108#define ROW_ADDR_CHIP_SEL_SHIFT 24
109
110
111#define STATUS_BYTE1_MASK 0x000000FF
112
113
114#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000
115#define CONFIG_ECC_SRAM_ADDR_SHIFT 22
116#define CONFIG_ECC_SRAM_REQ_BIT BIT(21)
117#define CONFIG_DMA_REQ_BIT BIT(20)
118#define CONFIG_ECC_MODE_MASK 0x000E0000
119#define CONFIG_ECC_MODE_SHIFT 17
120#define CONFIG_FAST_FLASH_BIT BIT(16)
121#define CONFIG_16BIT BIT(7)
122#define CONFIG_BOOT_MODE_BIT BIT(6)
123#define CONFIG_ADDR_AUTO_INCR_BIT BIT(5)
124#define CONFIG_BUFNO_AUTO_INCR_BIT BIT(4)
125#define CONFIG_PAGE_CNT_MASK 0xF
126#define CONFIG_PAGE_CNT_SHIFT 0
127
128
129#define IDLE_IRQ_BIT BIT(29)
130#define IDLE_EN_BIT BIT(20)
131#define CMD_DONE_CLEAR_BIT BIT(18)
132#define IDLE_CLEAR_BIT BIT(17)
133
134
135
136
137
138
139
140#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8)
141
142#define ECC_STATUS 0x4
143#define ECC_STATUS_MASK 0x80
144#define ECC_STATUS_ERR_COUNT 0x3F
145
146enum vf610_nfc_variant {
147 NFC_VFC610 = 1,
148};
149
150struct vf610_nfc {
151 struct nand_controller base;
152 struct nand_chip chip;
153 struct device *dev;
154 void __iomem *regs;
155 struct completion cmd_done;
156
157 enum vf610_nfc_variant variant;
158 struct clk *clk;
159
160
161
162
163
164 bool data_access;
165 u32 ecc_mode;
166};
167
168static inline struct vf610_nfc *chip_to_nfc(struct nand_chip *chip)
169{
170 return container_of(chip, struct vf610_nfc, chip);
171}
172
173static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg)
174{
175 return readl(nfc->regs + reg);
176}
177
178static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val)
179{
180 writel(val, nfc->regs + reg);
181}
182
183static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits)
184{
185 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits);
186}
187
188static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits)
189{
190 vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits);
191}
192
193static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg,
194 u32 mask, u32 shift, u32 val)
195{
196 vf610_nfc_write(nfc, reg,
197 (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift);
198}
199
200static inline bool vf610_nfc_kernel_is_little_endian(void)
201{
202#ifdef __LITTLE_ENDIAN
203 return true;
204#else
205 return false;
206#endif
207}
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227
228static inline void vf610_nfc_rd_from_sram(void *dst, const void __iomem *src,
229 size_t len, bool fix_endian)
230{
231 if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
232 unsigned int i;
233
234 for (i = 0; i < len; i += 4) {
235 u32 val = swab32(__raw_readl(src + i));
236
237 memcpy(dst + i, &val, min(sizeof(val), len - i));
238 }
239 } else {
240 memcpy_fromio(dst, src, len);
241 }
242}
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263static inline void vf610_nfc_wr_to_sram(void __iomem *dst, const void *src,
264 size_t len, bool fix_endian)
265{
266 if (vf610_nfc_kernel_is_little_endian() && fix_endian) {
267 unsigned int i;
268
269 for (i = 0; i < len; i += 4) {
270 u32 val;
271
272 memcpy(&val, src + i, min(sizeof(val), len - i));
273 __raw_writel(swab32(val), dst + i);
274 }
275 } else {
276 memcpy_toio(dst, src, len);
277 }
278}
279
280
281static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc)
282{
283 u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS);
284
285 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
286 vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp);
287}
288
289static void vf610_nfc_done(struct vf610_nfc *nfc)
290{
291 unsigned long timeout = msecs_to_jiffies(100);
292
293
294
295
296
297
298
299
300 vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
301 vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT);
302
303 if (!wait_for_completion_timeout(&nfc->cmd_done, timeout))
304 dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n");
305
306 vf610_nfc_clear_status(nfc);
307}
308
309static irqreturn_t vf610_nfc_irq(int irq, void *data)
310{
311 struct vf610_nfc *nfc = data;
312
313 vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT);
314 complete(&nfc->cmd_done);
315
316 return IRQ_HANDLED;
317}
318
319static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode)
320{
321 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
322 CONFIG_ECC_MODE_MASK,
323 CONFIG_ECC_MODE_SHIFT, ecc_mode);
324}
325
326static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size)
327{
328 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size);
329}
330
331static inline void vf610_nfc_run(struct vf610_nfc *nfc, u32 col, u32 row,
332 u32 cmd1, u32 cmd2, u32 trfr_sz)
333{
334 vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK,
335 COL_ADDR_SHIFT, col);
336
337 vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK,
338 ROW_ADDR_SHIFT, row);
339
340 vf610_nfc_write(nfc, NFC_SECTOR_SIZE, trfr_sz);
341 vf610_nfc_write(nfc, NFC_FLASH_CMD1, cmd1);
342 vf610_nfc_write(nfc, NFC_FLASH_CMD2, cmd2);
343
344 dev_dbg(nfc->dev,
345 "col 0x%04x, row 0x%08x, cmd1 0x%08x, cmd2 0x%08x, len %d\n",
346 col, row, cmd1, cmd2, trfr_sz);
347
348 vf610_nfc_done(nfc);
349}
350
351static inline const struct nand_op_instr *
352vf610_get_next_instr(const struct nand_subop *subop, int *op_id)
353{
354 if (*op_id + 1 >= subop->ninstrs)
355 return NULL;
356
357 (*op_id)++;
358
359 return &subop->instrs[*op_id];
360}
361
362static int vf610_nfc_cmd(struct nand_chip *chip,
363 const struct nand_subop *subop)
364{
365 const struct nand_op_instr *instr;
366 struct vf610_nfc *nfc = chip_to_nfc(chip);
367 int op_id = -1, trfr_sz = 0, offset = 0;
368 u32 col = 0, row = 0, cmd1 = 0, cmd2 = 0, code = 0;
369 bool force8bit = false;
370
371
372
373
374
375
376
377 instr = vf610_get_next_instr(subop, &op_id);
378 if (!instr)
379 return -EINVAL;
380
381 if (instr && instr->type == NAND_OP_CMD_INSTR) {
382 cmd2 |= instr->ctx.cmd.opcode << CMD_BYTE1_SHIFT;
383 code |= COMMAND_CMD_BYTE1;
384
385 instr = vf610_get_next_instr(subop, &op_id);
386 }
387
388 if (instr && instr->type == NAND_OP_ADDR_INSTR) {
389 int naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
390 int i = nand_subop_get_addr_start_off(subop, op_id);
391
392 for (; i < naddrs; i++) {
393 u8 val = instr->ctx.addr.addrs[i];
394
395 if (i < 2)
396 col |= COL_ADDR(i, val);
397 else
398 row |= ROW_ADDR(i - 2, val);
399 }
400 code |= COMMAND_NADDR_BYTES(naddrs);
401
402 instr = vf610_get_next_instr(subop, &op_id);
403 }
404
405 if (instr && instr->type == NAND_OP_DATA_OUT_INSTR) {
406 trfr_sz = nand_subop_get_data_len(subop, op_id);
407 offset = nand_subop_get_data_start_off(subop, op_id);
408 force8bit = instr->ctx.data.force_8bit;
409
410
411
412
413
414 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0) + offset,
415 instr->ctx.data.buf.out + offset,
416 trfr_sz, !nfc->data_access);
417 code |= COMMAND_WRITE_DATA;
418
419 instr = vf610_get_next_instr(subop, &op_id);
420 }
421
422 if (instr && instr->type == NAND_OP_CMD_INSTR) {
423 cmd1 |= instr->ctx.cmd.opcode << CMD_BYTE2_SHIFT;
424 code |= COMMAND_CMD_BYTE2;
425
426 instr = vf610_get_next_instr(subop, &op_id);
427 }
428
429 if (instr && instr->type == NAND_OP_WAITRDY_INSTR) {
430 code |= COMMAND_RB_HANDSHAKE;
431
432 instr = vf610_get_next_instr(subop, &op_id);
433 }
434
435 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
436 trfr_sz = nand_subop_get_data_len(subop, op_id);
437 offset = nand_subop_get_data_start_off(subop, op_id);
438 force8bit = instr->ctx.data.force_8bit;
439
440 code |= COMMAND_READ_DATA;
441 }
442
443 if (force8bit && (chip->options & NAND_BUSWIDTH_16))
444 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
445
446 cmd2 |= code << CMD_CODE_SHIFT;
447
448 vf610_nfc_run(nfc, col, row, cmd1, cmd2, trfr_sz);
449
450 if (instr && instr->type == NAND_OP_DATA_IN_INSTR) {
451
452
453
454
455 vf610_nfc_rd_from_sram(instr->ctx.data.buf.in + offset,
456 nfc->regs + NFC_MAIN_AREA(0) + offset,
457 trfr_sz, !nfc->data_access);
458 }
459
460 if (force8bit && (chip->options & NAND_BUSWIDTH_16))
461 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
462
463 return 0;
464}
465
466static const struct nand_op_parser vf610_nfc_op_parser = NAND_OP_PARSER(
467 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
468 NAND_OP_PARSER_PAT_CMD_ELEM(true),
469 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
470 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(true, PAGE_2K + OOB_MAX),
471 NAND_OP_PARSER_PAT_CMD_ELEM(true),
472 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
473 NAND_OP_PARSER_PATTERN(vf610_nfc_cmd,
474 NAND_OP_PARSER_PAT_CMD_ELEM(true),
475 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
476 NAND_OP_PARSER_PAT_CMD_ELEM(true),
477 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
478 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, PAGE_2K + OOB_MAX)),
479 );
480
481
482
483
484static void vf610_nfc_select_target(struct nand_chip *chip, unsigned int cs)
485{
486 struct vf610_nfc *nfc = chip_to_nfc(chip);
487 u32 tmp;
488
489
490 if (nfc->variant != NFC_VFC610)
491 return;
492
493 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR);
494 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
495 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
496 tmp |= BIT(cs) << ROW_ADDR_CHIP_SEL_SHIFT;
497
498 vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp);
499}
500
501static int vf610_nfc_exec_op(struct nand_chip *chip,
502 const struct nand_operation *op,
503 bool check_only)
504{
505 if (!check_only)
506 vf610_nfc_select_target(chip, op->cs);
507
508 return nand_op_parser_exec_op(chip, &vf610_nfc_op_parser, op,
509 check_only);
510}
511
512static inline int vf610_nfc_correct_data(struct nand_chip *chip, uint8_t *dat,
513 uint8_t *oob, int page)
514{
515 struct vf610_nfc *nfc = chip_to_nfc(chip);
516 struct mtd_info *mtd = nand_to_mtd(chip);
517 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
518 u8 ecc_status;
519 u8 ecc_count;
520 int flips_threshold = nfc->chip.ecc.strength / 2;
521
522 ecc_status = vf610_nfc_read(nfc, ecc_status_off) & 0xff;
523 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
524
525 if (!(ecc_status & ECC_STATUS_MASK))
526 return ecc_count;
527
528 nfc->data_access = true;
529 nand_read_oob_op(&nfc->chip, page, 0, oob, mtd->oobsize);
530 nfc->data_access = false;
531
532
533
534
535
536 return nand_check_erased_ecc_chunk(dat, nfc->chip.ecc.size, oob,
537 mtd->oobsize, NULL, 0,
538 flips_threshold);
539}
540
541static void vf610_nfc_fill_row(struct nand_chip *chip, int page, u32 *code,
542 u32 *row)
543{
544 *row = ROW_ADDR(0, page & 0xff) | ROW_ADDR(1, page >> 8);
545 *code |= COMMAND_RAR_BYTE1 | COMMAND_RAR_BYTE2;
546
547 if (chip->options & NAND_ROW_ADDR_3) {
548 *row |= ROW_ADDR(2, page >> 16);
549 *code |= COMMAND_RAR_BYTE3;
550 }
551}
552
553static int vf610_nfc_read_page(struct nand_chip *chip, uint8_t *buf,
554 int oob_required, int page)
555{
556 struct vf610_nfc *nfc = chip_to_nfc(chip);
557 struct mtd_info *mtd = nand_to_mtd(chip);
558 int trfr_sz = mtd->writesize + mtd->oobsize;
559 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
560 int stat;
561
562 vf610_nfc_select_target(chip, chip->cur_cs);
563
564 cmd2 |= NAND_CMD_READ0 << CMD_BYTE1_SHIFT;
565 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
566
567 vf610_nfc_fill_row(chip, page, &code, &row);
568
569 cmd1 |= NAND_CMD_READSTART << CMD_BYTE2_SHIFT;
570 code |= COMMAND_CMD_BYTE2 | COMMAND_RB_HANDSHAKE | COMMAND_READ_DATA;
571
572 cmd2 |= code << CMD_CODE_SHIFT;
573
574 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
575 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
576 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
577
578
579
580
581
582 vf610_nfc_rd_from_sram(buf, nfc->regs + NFC_MAIN_AREA(0),
583 mtd->writesize, false);
584 if (oob_required)
585 vf610_nfc_rd_from_sram(chip->oob_poi,
586 nfc->regs + NFC_MAIN_AREA(0) +
587 mtd->writesize,
588 mtd->oobsize, false);
589
590 stat = vf610_nfc_correct_data(chip, buf, chip->oob_poi, page);
591
592 if (stat < 0) {
593 mtd->ecc_stats.failed++;
594 return 0;
595 } else {
596 mtd->ecc_stats.corrected += stat;
597 return stat;
598 }
599}
600
601static int vf610_nfc_write_page(struct nand_chip *chip, const uint8_t *buf,
602 int oob_required, int page)
603{
604 struct vf610_nfc *nfc = chip_to_nfc(chip);
605 struct mtd_info *mtd = nand_to_mtd(chip);
606 int trfr_sz = mtd->writesize + mtd->oobsize;
607 u32 row = 0, cmd1 = 0, cmd2 = 0, code = 0;
608 u8 status;
609 int ret;
610
611 vf610_nfc_select_target(chip, chip->cur_cs);
612
613 cmd2 |= NAND_CMD_SEQIN << CMD_BYTE1_SHIFT;
614 code |= COMMAND_CMD_BYTE1 | COMMAND_CAR_BYTE1 | COMMAND_CAR_BYTE2;
615
616 vf610_nfc_fill_row(chip, page, &code, &row);
617
618 cmd1 |= NAND_CMD_PAGEPROG << CMD_BYTE2_SHIFT;
619 code |= COMMAND_CMD_BYTE2 | COMMAND_WRITE_DATA;
620
621
622
623
624
625 vf610_nfc_wr_to_sram(nfc->regs + NFC_MAIN_AREA(0), buf,
626 mtd->writesize, false);
627
628 code |= COMMAND_RB_HANDSHAKE;
629 cmd2 |= code << CMD_CODE_SHIFT;
630
631 vf610_nfc_ecc_mode(nfc, nfc->ecc_mode);
632 vf610_nfc_run(nfc, 0, row, cmd1, cmd2, trfr_sz);
633 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
634
635 ret = nand_status_op(chip, &status);
636 if (ret)
637 return ret;
638
639 if (status & NAND_STATUS_FAIL)
640 return -EIO;
641
642 return 0;
643}
644
645static int vf610_nfc_read_page_raw(struct nand_chip *chip, u8 *buf,
646 int oob_required, int page)
647{
648 struct vf610_nfc *nfc = chip_to_nfc(chip);
649 int ret;
650
651 nfc->data_access = true;
652 ret = nand_read_page_raw(chip, buf, oob_required, page);
653 nfc->data_access = false;
654
655 return ret;
656}
657
658static int vf610_nfc_write_page_raw(struct nand_chip *chip, const u8 *buf,
659 int oob_required, int page)
660{
661 struct vf610_nfc *nfc = chip_to_nfc(chip);
662 struct mtd_info *mtd = nand_to_mtd(chip);
663 int ret;
664
665 nfc->data_access = true;
666 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
667 if (!ret && oob_required)
668 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
669 false);
670 nfc->data_access = false;
671
672 if (ret)
673 return ret;
674
675 return nand_prog_page_end_op(chip);
676}
677
678static int vf610_nfc_read_oob(struct nand_chip *chip, int page)
679{
680 struct vf610_nfc *nfc = chip_to_nfc(chip);
681 int ret;
682
683 nfc->data_access = true;
684 ret = nand_read_oob_std(chip, page);
685 nfc->data_access = false;
686
687 return ret;
688}
689
690static int vf610_nfc_write_oob(struct nand_chip *chip, int page)
691{
692 struct mtd_info *mtd = nand_to_mtd(chip);
693 struct vf610_nfc *nfc = chip_to_nfc(chip);
694 int ret;
695
696 nfc->data_access = true;
697 ret = nand_prog_page_begin_op(chip, page, mtd->writesize,
698 chip->oob_poi, mtd->oobsize);
699 nfc->data_access = false;
700
701 if (ret)
702 return ret;
703
704 return nand_prog_page_end_op(chip);
705}
706
707static const struct of_device_id vf610_nfc_dt_ids[] = {
708 { .compatible = "fsl,vf610-nfc", .data = (void *)NFC_VFC610 },
709 { }
710};
711MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids);
712
713static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc)
714{
715 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
716 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
717 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
718 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
719 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
720 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
721 vf610_nfc_ecc_mode(nfc, ECC_BYPASS);
722
723
724 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
725 CONFIG_PAGE_CNT_SHIFT, 1);
726}
727
728static void vf610_nfc_init_controller(struct vf610_nfc *nfc)
729{
730 if (nfc->chip.options & NAND_BUSWIDTH_16)
731 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
732 else
733 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT);
734
735 if (nfc->chip.ecc.mode == NAND_ECC_HW) {
736
737 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG,
738 CONFIG_ECC_SRAM_ADDR_MASK,
739 CONFIG_ECC_SRAM_ADDR_SHIFT,
740 ECC_SRAM_ADDR >> 3);
741
742
743 vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
744 }
745}
746
747static int vf610_nfc_attach_chip(struct nand_chip *chip)
748{
749 struct mtd_info *mtd = nand_to_mtd(chip);
750 struct vf610_nfc *nfc = chip_to_nfc(chip);
751
752 vf610_nfc_init_controller(nfc);
753
754
755 if (chip->bbt_options & NAND_BBT_USE_FLASH)
756 chip->bbt_options |= NAND_BBT_NO_OOB;
757
758
759 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
760 dev_err(nfc->dev, "Unsupported flash page size\n");
761 return -ENXIO;
762 }
763
764 if (chip->ecc.mode != NAND_ECC_HW)
765 return 0;
766
767 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
768 dev_err(nfc->dev, "Unsupported flash with hwecc\n");
769 return -ENXIO;
770 }
771
772 if (chip->ecc.size != mtd->writesize) {
773 dev_err(nfc->dev, "Step size needs to be page size\n");
774 return -ENXIO;
775 }
776
777
778 if (mtd->oobsize > 64)
779 mtd->oobsize = 64;
780
781
782 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
783 if (chip->ecc.strength == 32) {
784 nfc->ecc_mode = ECC_60_BYTE;
785 chip->ecc.bytes = 60;
786 } else if (chip->ecc.strength == 24) {
787 nfc->ecc_mode = ECC_45_BYTE;
788 chip->ecc.bytes = 45;
789 } else {
790 dev_err(nfc->dev, "Unsupported ECC strength\n");
791 return -ENXIO;
792 }
793
794 chip->ecc.read_page = vf610_nfc_read_page;
795 chip->ecc.write_page = vf610_nfc_write_page;
796 chip->ecc.read_page_raw = vf610_nfc_read_page_raw;
797 chip->ecc.write_page_raw = vf610_nfc_write_page_raw;
798 chip->ecc.read_oob = vf610_nfc_read_oob;
799 chip->ecc.write_oob = vf610_nfc_write_oob;
800
801 chip->ecc.size = PAGE_2K;
802
803 return 0;
804}
805
806static const struct nand_controller_ops vf610_nfc_controller_ops = {
807 .attach_chip = vf610_nfc_attach_chip,
808 .exec_op = vf610_nfc_exec_op,
809
810};
811
812static int vf610_nfc_probe(struct platform_device *pdev)
813{
814 struct vf610_nfc *nfc;
815 struct resource *res;
816 struct mtd_info *mtd;
817 struct nand_chip *chip;
818 struct device_node *child;
819 const struct of_device_id *of_id;
820 int err;
821 int irq;
822
823 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
824 if (!nfc)
825 return -ENOMEM;
826
827 nfc->dev = &pdev->dev;
828 chip = &nfc->chip;
829 mtd = nand_to_mtd(chip);
830
831 mtd->owner = THIS_MODULE;
832 mtd->dev.parent = nfc->dev;
833 mtd->name = DRV_NAME;
834
835 irq = platform_get_irq(pdev, 0);
836 if (irq <= 0)
837 return -EINVAL;
838
839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
840 nfc->regs = devm_ioremap_resource(nfc->dev, res);
841 if (IS_ERR(nfc->regs))
842 return PTR_ERR(nfc->regs);
843
844 nfc->clk = devm_clk_get(&pdev->dev, NULL);
845 if (IS_ERR(nfc->clk))
846 return PTR_ERR(nfc->clk);
847
848 err = clk_prepare_enable(nfc->clk);
849 if (err) {
850 dev_err(nfc->dev, "Unable to enable clock!\n");
851 return err;
852 }
853
854 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev);
855 if (!of_id)
856 return -ENODEV;
857
858 nfc->variant = (enum vf610_nfc_variant)of_id->data;
859
860 for_each_available_child_of_node(nfc->dev->of_node, child) {
861 if (of_device_is_compatible(child, "fsl,vf610-nfc-nandcs")) {
862
863 if (nand_get_flash_node(chip)) {
864 dev_err(nfc->dev,
865 "Only one NAND chip supported!\n");
866 err = -EINVAL;
867 of_node_put(child);
868 goto err_disable_clk;
869 }
870
871 nand_set_flash_node(chip, child);
872 }
873 }
874
875 if (!nand_get_flash_node(chip)) {
876 dev_err(nfc->dev, "NAND chip sub-node missing!\n");
877 err = -ENODEV;
878 goto err_disable_clk;
879 }
880
881 chip->options |= NAND_NO_SUBPAGE_WRITE;
882
883 init_completion(&nfc->cmd_done);
884
885 err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, nfc);
886 if (err) {
887 dev_err(nfc->dev, "Error requesting IRQ!\n");
888 goto err_disable_clk;
889 }
890
891 vf610_nfc_preinit_controller(nfc);
892
893 nand_controller_init(&nfc->base);
894 nfc->base.ops = &vf610_nfc_controller_ops;
895 chip->controller = &nfc->base;
896
897
898 err = nand_scan(chip, 1);
899 if (err)
900 goto err_disable_clk;
901
902 platform_set_drvdata(pdev, nfc);
903
904
905 err = mtd_device_register(mtd, NULL, 0);
906 if (err)
907 goto err_cleanup_nand;
908 return 0;
909
910err_cleanup_nand:
911 nand_cleanup(chip);
912err_disable_clk:
913 clk_disable_unprepare(nfc->clk);
914 return err;
915}
916
917static int vf610_nfc_remove(struct platform_device *pdev)
918{
919 struct vf610_nfc *nfc = platform_get_drvdata(pdev);
920 struct nand_chip *chip = &nfc->chip;
921 int ret;
922
923 ret = mtd_device_unregister(nand_to_mtd(chip));
924 WARN_ON(ret);
925 nand_cleanup(chip);
926 clk_disable_unprepare(nfc->clk);
927 return 0;
928}
929
930#ifdef CONFIG_PM_SLEEP
931static int vf610_nfc_suspend(struct device *dev)
932{
933 struct vf610_nfc *nfc = dev_get_drvdata(dev);
934
935 clk_disable_unprepare(nfc->clk);
936 return 0;
937}
938
939static int vf610_nfc_resume(struct device *dev)
940{
941 struct vf610_nfc *nfc = dev_get_drvdata(dev);
942 int err;
943
944 err = clk_prepare_enable(nfc->clk);
945 if (err)
946 return err;
947
948 vf610_nfc_preinit_controller(nfc);
949 vf610_nfc_init_controller(nfc);
950 return 0;
951}
952#endif
953
954static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume);
955
956static struct platform_driver vf610_nfc_driver = {
957 .driver = {
958 .name = DRV_NAME,
959 .of_match_table = vf610_nfc_dt_ids,
960 .pm = &vf610_nfc_pm_ops,
961 },
962 .probe = vf610_nfc_probe,
963 .remove = vf610_nfc_remove,
964};
965
966module_platform_driver(vf610_nfc_driver);
967
968MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
969MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver");
970MODULE_LICENSE("GPL");
971