1
2
3
4
5#include <linux/types.h>
6#include <soc/mscc/ocelot_vcap.h>
7#include <soc/mscc/ocelot_sys.h>
8#include <soc/mscc/ocelot.h>
9#include <linux/of_platform.h>
10#include <linux/packing.h>
11#include <linux/iopoll.h>
12#include "felix.h"
13
14#define VSC9953_VCAP_IS2_CNT 1024
15#define VSC9953_VCAP_IS2_ENTRY_WIDTH 376
16#define VSC9953_VCAP_PORT_CNT 10
17
18#define MSCC_MIIM_REG_STATUS 0x0
19#define MSCC_MIIM_STATUS_STAT_BUSY BIT(3)
20#define MSCC_MIIM_REG_CMD 0x8
21#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
22#define MSCC_MIIM_CMD_OPR_READ BIT(2)
23#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
24#define MSCC_MIIM_CMD_REGAD_SHIFT 20
25#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
26#define MSCC_MIIM_CMD_VLD BIT(31)
27#define MSCC_MIIM_REG_DATA 0xC
28#define MSCC_MIIM_DATA_ERROR (BIT(16) | BIT(17))
29
30#define MSCC_PHY_REG_PHY_CFG 0x0
31#define PHY_CFG_PHY_ENA (BIT(0) | BIT(1) | BIT(2) | BIT(3))
32#define PHY_CFG_PHY_COMMON_RESET BIT(4)
33#define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8))
34#define MSCC_PHY_REG_PHY_STATUS 0x4
35
36static const u32 vsc9953_ana_regmap[] = {
37 REG(ANA_ADVLEARN, 0x00b500),
38 REG(ANA_VLANMASK, 0x00b504),
39 REG_RESERVED(ANA_PORT_B_DOMAIN),
40 REG(ANA_ANAGEFIL, 0x00b50c),
41 REG(ANA_ANEVENTS, 0x00b510),
42 REG(ANA_STORMLIMIT_BURST, 0x00b514),
43 REG(ANA_STORMLIMIT_CFG, 0x00b518),
44 REG(ANA_ISOLATED_PORTS, 0x00b528),
45 REG(ANA_COMMUNITY_PORTS, 0x00b52c),
46 REG(ANA_AUTOAGE, 0x00b530),
47 REG(ANA_MACTOPTIONS, 0x00b534),
48 REG(ANA_LEARNDISC, 0x00b538),
49 REG(ANA_AGENCTRL, 0x00b53c),
50 REG(ANA_MIRRORPORTS, 0x00b540),
51 REG(ANA_EMIRRORPORTS, 0x00b544),
52 REG(ANA_FLOODING, 0x00b548),
53 REG(ANA_FLOODING_IPMC, 0x00b54c),
54 REG(ANA_SFLOW_CFG, 0x00b550),
55 REG(ANA_PORT_MODE, 0x00b57c),
56 REG_RESERVED(ANA_CUT_THRU_CFG),
57 REG(ANA_PGID_PGID, 0x00b600),
58 REG(ANA_TABLES_ANMOVED, 0x00b4ac),
59 REG(ANA_TABLES_MACHDATA, 0x00b4b0),
60 REG(ANA_TABLES_MACLDATA, 0x00b4b4),
61 REG_RESERVED(ANA_TABLES_STREAMDATA),
62 REG(ANA_TABLES_MACACCESS, 0x00b4b8),
63 REG(ANA_TABLES_MACTINDX, 0x00b4bc),
64 REG(ANA_TABLES_VLANACCESS, 0x00b4c0),
65 REG(ANA_TABLES_VLANTIDX, 0x00b4c4),
66 REG_RESERVED(ANA_TABLES_ISDXACCESS),
67 REG_RESERVED(ANA_TABLES_ISDXTIDX),
68 REG(ANA_TABLES_ENTRYLIM, 0x00b480),
69 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH),
70 REG_RESERVED(ANA_TABLES_PTP_ID_LOW),
71 REG_RESERVED(ANA_TABLES_STREAMACCESS),
72 REG_RESERVED(ANA_TABLES_STREAMTIDX),
73 REG_RESERVED(ANA_TABLES_SEQ_HISTORY),
74 REG_RESERVED(ANA_TABLES_SEQ_MASK),
75 REG_RESERVED(ANA_TABLES_SFID_MASK),
76 REG_RESERVED(ANA_TABLES_SFIDACCESS),
77 REG_RESERVED(ANA_TABLES_SFIDTIDX),
78 REG_RESERVED(ANA_MSTI_STATE),
79 REG_RESERVED(ANA_OAM_UPM_LM_CNT),
80 REG_RESERVED(ANA_SG_ACCESS_CTRL),
81 REG_RESERVED(ANA_SG_CONFIG_REG_1),
82 REG_RESERVED(ANA_SG_CONFIG_REG_2),
83 REG_RESERVED(ANA_SG_CONFIG_REG_3),
84 REG_RESERVED(ANA_SG_CONFIG_REG_4),
85 REG_RESERVED(ANA_SG_CONFIG_REG_5),
86 REG_RESERVED(ANA_SG_GCL_GS_CONFIG),
87 REG_RESERVED(ANA_SG_GCL_TI_CONFIG),
88 REG_RESERVED(ANA_SG_STATUS_REG_1),
89 REG_RESERVED(ANA_SG_STATUS_REG_2),
90 REG_RESERVED(ANA_SG_STATUS_REG_3),
91 REG(ANA_PORT_VLAN_CFG, 0x000000),
92 REG(ANA_PORT_DROP_CFG, 0x000004),
93 REG(ANA_PORT_QOS_CFG, 0x000008),
94 REG(ANA_PORT_VCAP_CFG, 0x00000c),
95 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010),
96 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c),
97 REG(ANA_PORT_PCP_DEI_MAP, 0x000020),
98 REG(ANA_PORT_CPU_FWD_CFG, 0x000060),
99 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064),
100 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068),
101 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c),
102 REG(ANA_PORT_PORT_CFG, 0x000070),
103 REG(ANA_PORT_POL_CFG, 0x000074),
104 REG_RESERVED(ANA_PORT_PTP_CFG),
105 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG),
106 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG),
107 REG_RESERVED(ANA_PORT_SFID_CFG),
108 REG(ANA_PFC_PFC_CFG, 0x00c000),
109 REG_RESERVED(ANA_PFC_PFC_TIMER),
110 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
111 REG_RESERVED(ANA_IPT_IPT),
112 REG_RESERVED(ANA_PPT_PPT),
113 REG_RESERVED(ANA_FID_MAP_FID_MAP),
114 REG(ANA_AGGR_CFG, 0x00c600),
115 REG(ANA_CPUQ_CFG, 0x00c604),
116 REG_RESERVED(ANA_CPUQ_CFG2),
117 REG(ANA_CPUQ_8021_CFG, 0x00c60c),
118 REG(ANA_DSCP_CFG, 0x00c64c),
119 REG(ANA_DSCP_REWR_CFG, 0x00c74c),
120 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c),
121 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac),
122 REG_RESERVED(ANA_VRAP_CFG),
123 REG_RESERVED(ANA_VRAP_HDR_DATA),
124 REG_RESERVED(ANA_VRAP_HDR_MASK),
125 REG(ANA_DISCARD_CFG, 0x00c7d8),
126 REG(ANA_FID_CFG, 0x00c7dc),
127 REG(ANA_POL_PIR_CFG, 0x00a000),
128 REG(ANA_POL_CIR_CFG, 0x00a004),
129 REG(ANA_POL_MODE_CFG, 0x00a008),
130 REG(ANA_POL_PIR_STATE, 0x00a00c),
131 REG(ANA_POL_CIR_STATE, 0x00a010),
132 REG_RESERVED(ANA_POL_STATE),
133 REG(ANA_POL_FLOWC, 0x00c280),
134 REG(ANA_POL_HYST, 0x00c2ec),
135 REG_RESERVED(ANA_POL_MISC_CFG),
136};
137
138static const u32 vsc9953_qs_regmap[] = {
139 REG(QS_XTR_GRP_CFG, 0x000000),
140 REG(QS_XTR_RD, 0x000008),
141 REG(QS_XTR_FRM_PRUNING, 0x000010),
142 REG(QS_XTR_FLUSH, 0x000018),
143 REG(QS_XTR_DATA_PRESENT, 0x00001c),
144 REG(QS_XTR_CFG, 0x000020),
145 REG(QS_INJ_GRP_CFG, 0x000024),
146 REG(QS_INJ_WR, 0x00002c),
147 REG(QS_INJ_CTRL, 0x000034),
148 REG(QS_INJ_STATUS, 0x00003c),
149 REG(QS_INJ_ERR, 0x000040),
150 REG_RESERVED(QS_INH_DBG),
151};
152
153static const u32 vsc9953_s2_regmap[] = {
154 REG(S2_CORE_UPDATE_CTRL, 0x000000),
155 REG(S2_CORE_MV_CFG, 0x000004),
156 REG(S2_CACHE_ENTRY_DAT, 0x000008),
157 REG(S2_CACHE_MASK_DAT, 0x000108),
158 REG(S2_CACHE_ACTION_DAT, 0x000208),
159 REG(S2_CACHE_CNT_DAT, 0x000308),
160 REG(S2_CACHE_TG_DAT, 0x000388),
161};
162
163static const u32 vsc9953_qsys_regmap[] = {
164 REG(QSYS_PORT_MODE, 0x003600),
165 REG(QSYS_SWITCH_PORT_MODE, 0x003630),
166 REG(QSYS_STAT_CNT_CFG, 0x00365c),
167 REG(QSYS_EEE_CFG, 0x003660),
168 REG(QSYS_EEE_THRES, 0x003688),
169 REG(QSYS_IGR_NO_SHARING, 0x00368c),
170 REG(QSYS_EGR_NO_SHARING, 0x003690),
171 REG(QSYS_SW_STATUS, 0x003694),
172 REG(QSYS_EXT_CPU_CFG, 0x0036c0),
173 REG_RESERVED(QSYS_PAD_CFG),
174 REG(QSYS_CPU_GROUP_MAP, 0x0036c8),
175 REG_RESERVED(QSYS_QMAP),
176 REG_RESERVED(QSYS_ISDX_SGRP),
177 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
178 REG_RESERVED(QSYS_TFRM_MISC),
179 REG_RESERVED(QSYS_TFRM_PORT_DLY),
180 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1),
181 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2),
182 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3),
183 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4),
184 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5),
185 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6),
186 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7),
187 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8),
188 REG(QSYS_RED_PROFILE, 0x003724),
189 REG(QSYS_RES_QOS_MODE, 0x003764),
190 REG(QSYS_RES_CFG, 0x004000),
191 REG(QSYS_RES_STAT, 0x004004),
192 REG(QSYS_EGR_DROP_MODE, 0x003768),
193 REG(QSYS_EQ_CTRL, 0x00376c),
194 REG_RESERVED(QSYS_EVENTS_CORE),
195 REG_RESERVED(QSYS_QMAXSDU_CFG_0),
196 REG_RESERVED(QSYS_QMAXSDU_CFG_1),
197 REG_RESERVED(QSYS_QMAXSDU_CFG_2),
198 REG_RESERVED(QSYS_QMAXSDU_CFG_3),
199 REG_RESERVED(QSYS_QMAXSDU_CFG_4),
200 REG_RESERVED(QSYS_QMAXSDU_CFG_5),
201 REG_RESERVED(QSYS_QMAXSDU_CFG_6),
202 REG_RESERVED(QSYS_QMAXSDU_CFG_7),
203 REG_RESERVED(QSYS_PREEMPTION_CFG),
204 REG(QSYS_CIR_CFG, 0x000000),
205 REG_RESERVED(QSYS_EIR_CFG),
206 REG(QSYS_SE_CFG, 0x000008),
207 REG(QSYS_SE_DWRR_CFG, 0x00000c),
208 REG_RESERVED(QSYS_SE_CONNECT),
209 REG_RESERVED(QSYS_SE_DLB_SENSE),
210 REG(QSYS_CIR_STATE, 0x000044),
211 REG_RESERVED(QSYS_EIR_STATE),
212 REG_RESERVED(QSYS_SE_STATE),
213 REG(QSYS_HSCH_MISC_CFG, 0x003774),
214 REG_RESERVED(QSYS_TAG_CONFIG),
215 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL),
216 REG_RESERVED(QSYS_PORT_MAX_SDU),
217 REG_RESERVED(QSYS_PARAM_CFG_REG_1),
218 REG_RESERVED(QSYS_PARAM_CFG_REG_2),
219 REG_RESERVED(QSYS_PARAM_CFG_REG_3),
220 REG_RESERVED(QSYS_PARAM_CFG_REG_4),
221 REG_RESERVED(QSYS_PARAM_CFG_REG_5),
222 REG_RESERVED(QSYS_GCL_CFG_REG_1),
223 REG_RESERVED(QSYS_GCL_CFG_REG_2),
224 REG_RESERVED(QSYS_PARAM_STATUS_REG_1),
225 REG_RESERVED(QSYS_PARAM_STATUS_REG_2),
226 REG_RESERVED(QSYS_PARAM_STATUS_REG_3),
227 REG_RESERVED(QSYS_PARAM_STATUS_REG_4),
228 REG_RESERVED(QSYS_PARAM_STATUS_REG_5),
229 REG_RESERVED(QSYS_PARAM_STATUS_REG_6),
230 REG_RESERVED(QSYS_PARAM_STATUS_REG_7),
231 REG_RESERVED(QSYS_PARAM_STATUS_REG_8),
232 REG_RESERVED(QSYS_PARAM_STATUS_REG_9),
233 REG_RESERVED(QSYS_GCL_STATUS_REG_1),
234 REG_RESERVED(QSYS_GCL_STATUS_REG_2),
235};
236
237static const u32 vsc9953_rew_regmap[] = {
238 REG(REW_PORT_VLAN_CFG, 0x000000),
239 REG(REW_TAG_CFG, 0x000004),
240 REG(REW_PORT_CFG, 0x000008),
241 REG(REW_DSCP_CFG, 0x00000c),
242 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
243 REG_RESERVED(REW_PTP_CFG),
244 REG_RESERVED(REW_PTP_DLY1_CFG),
245 REG_RESERVED(REW_RED_TAG_CFG),
246 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610),
247 REG(REW_DSCP_REMAP_CFG, 0x000710),
248 REG_RESERVED(REW_STAT_CFG),
249 REG_RESERVED(REW_REW_STICKY),
250 REG_RESERVED(REW_PPT),
251};
252
253static const u32 vsc9953_sys_regmap[] = {
254 REG(SYS_COUNT_RX_OCTETS, 0x000000),
255 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
256 REG(SYS_COUNT_RX_SHORTS, 0x000010),
257 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
258 REG(SYS_COUNT_RX_JABBERS, 0x000018),
259 REG(SYS_COUNT_RX_64, 0x000024),
260 REG(SYS_COUNT_RX_65_127, 0x000028),
261 REG(SYS_COUNT_RX_128_255, 0x00002c),
262 REG(SYS_COUNT_RX_256_1023, 0x000030),
263 REG(SYS_COUNT_RX_1024_1526, 0x000034),
264 REG(SYS_COUNT_RX_1527_MAX, 0x000038),
265 REG(SYS_COUNT_RX_LONGS, 0x000048),
266 REG(SYS_COUNT_TX_OCTETS, 0x000100),
267 REG(SYS_COUNT_TX_COLLISION, 0x000110),
268 REG(SYS_COUNT_TX_DROPS, 0x000114),
269 REG(SYS_COUNT_TX_64, 0x00011c),
270 REG(SYS_COUNT_TX_65_127, 0x000120),
271 REG(SYS_COUNT_TX_128_511, 0x000124),
272 REG(SYS_COUNT_TX_512_1023, 0x000128),
273 REG(SYS_COUNT_TX_1024_1526, 0x00012c),
274 REG(SYS_COUNT_TX_1527_MAX, 0x000130),
275 REG(SYS_COUNT_TX_AGING, 0x000178),
276 REG(SYS_RESET_CFG, 0x000318),
277 REG_RESERVED(SYS_SR_ETYPE_CFG),
278 REG(SYS_VLAN_ETYPE_CFG, 0x000320),
279 REG(SYS_PORT_MODE, 0x000324),
280 REG(SYS_FRONT_PORT_MODE, 0x000354),
281 REG(SYS_FRM_AGING, 0x00037c),
282 REG(SYS_STAT_CFG, 0x000380),
283 REG_RESERVED(SYS_SW_STATUS),
284 REG_RESERVED(SYS_MISC_CFG),
285 REG_RESERVED(SYS_REW_MAC_HIGH_CFG),
286 REG_RESERVED(SYS_REW_MAC_LOW_CFG),
287 REG_RESERVED(SYS_TIMESTAMP_OFFSET),
288 REG(SYS_PAUSE_CFG, 0x00044c),
289 REG(SYS_PAUSE_TOT_CFG, 0x000478),
290 REG(SYS_ATOP, 0x00047c),
291 REG(SYS_ATOP_TOT_CFG, 0x0004a8),
292 REG(SYS_MAC_FC_CFG, 0x0004ac),
293 REG(SYS_MMGT, 0x0004d4),
294 REG_RESERVED(SYS_MMGT_FAST),
295 REG_RESERVED(SYS_EVENTS_DIF),
296 REG_RESERVED(SYS_EVENTS_CORE),
297 REG_RESERVED(SYS_CNT),
298 REG_RESERVED(SYS_PTP_STATUS),
299 REG_RESERVED(SYS_PTP_TXSTAMP),
300 REG_RESERVED(SYS_PTP_NXT),
301 REG_RESERVED(SYS_PTP_CFG),
302 REG_RESERVED(SYS_RAM_INIT),
303 REG_RESERVED(SYS_CM_ADDR),
304 REG_RESERVED(SYS_CM_DATA_WR),
305 REG_RESERVED(SYS_CM_DATA_RD),
306 REG_RESERVED(SYS_CM_OP),
307 REG_RESERVED(SYS_CM_DATA),
308};
309
310static const u32 vsc9953_gcb_regmap[] = {
311 REG(GCB_SOFT_RST, 0x000008),
312 REG(GCB_MIIM_MII_STATUS, 0x0000ac),
313 REG(GCB_MIIM_MII_CMD, 0x0000b4),
314 REG(GCB_MIIM_MII_DATA, 0x0000b8),
315};
316
317static const u32 vsc9953_dev_gmii_regmap[] = {
318 REG(DEV_CLOCK_CFG, 0x0),
319 REG(DEV_PORT_MISC, 0x4),
320 REG_RESERVED(DEV_EVENTS),
321 REG(DEV_EEE_CFG, 0xc),
322 REG_RESERVED(DEV_RX_PATH_DELAY),
323 REG_RESERVED(DEV_TX_PATH_DELAY),
324 REG_RESERVED(DEV_PTP_PREDICT_CFG),
325 REG(DEV_MAC_ENA_CFG, 0x10),
326 REG(DEV_MAC_MODE_CFG, 0x14),
327 REG(DEV_MAC_MAXLEN_CFG, 0x18),
328 REG(DEV_MAC_TAGS_CFG, 0x1c),
329 REG(DEV_MAC_ADV_CHK_CFG, 0x20),
330 REG(DEV_MAC_IFG_CFG, 0x24),
331 REG(DEV_MAC_HDX_CFG, 0x28),
332 REG_RESERVED(DEV_MAC_DBG_CFG),
333 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30),
334 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34),
335 REG(DEV_MAC_STICKY, 0x38),
336 REG_RESERVED(PCS1G_CFG),
337 REG_RESERVED(PCS1G_MODE_CFG),
338 REG_RESERVED(PCS1G_SD_CFG),
339 REG_RESERVED(PCS1G_ANEG_CFG),
340 REG_RESERVED(PCS1G_ANEG_NP_CFG),
341 REG_RESERVED(PCS1G_LB_CFG),
342 REG_RESERVED(PCS1G_DBG_CFG),
343 REG_RESERVED(PCS1G_CDET_CFG),
344 REG_RESERVED(PCS1G_ANEG_STATUS),
345 REG_RESERVED(PCS1G_ANEG_NP_STATUS),
346 REG_RESERVED(PCS1G_LINK_STATUS),
347 REG_RESERVED(PCS1G_LINK_DOWN_CNT),
348 REG_RESERVED(PCS1G_STICKY),
349 REG_RESERVED(PCS1G_DEBUG_STATUS),
350 REG_RESERVED(PCS1G_LPI_CFG),
351 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
352 REG_RESERVED(PCS1G_LPI_STATUS),
353 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
354 REG_RESERVED(PCS1G_TSTPAT_STATUS),
355 REG_RESERVED(DEV_PCS_FX100_CFG),
356 REG_RESERVED(DEV_PCS_FX100_STATUS),
357};
358
359static const u32 *vsc9953_regmap[TARGET_MAX] = {
360 [ANA] = vsc9953_ana_regmap,
361 [QS] = vsc9953_qs_regmap,
362 [QSYS] = vsc9953_qsys_regmap,
363 [REW] = vsc9953_rew_regmap,
364 [SYS] = vsc9953_sys_regmap,
365 [S2] = vsc9953_s2_regmap,
366 [GCB] = vsc9953_gcb_regmap,
367 [DEV_GMII] = vsc9953_dev_gmii_regmap,
368};
369
370
371static const struct resource vsc9953_target_io_res[TARGET_MAX] = {
372 [ANA] = {
373 .start = 0x0280000,
374 .end = 0x028ffff,
375 .name = "ana",
376 },
377 [QS] = {
378 .start = 0x0080000,
379 .end = 0x00800ff,
380 .name = "qs",
381 },
382 [QSYS] = {
383 .start = 0x0200000,
384 .end = 0x021ffff,
385 .name = "qsys",
386 },
387 [REW] = {
388 .start = 0x0030000,
389 .end = 0x003ffff,
390 .name = "rew",
391 },
392 [SYS] = {
393 .start = 0x0010000,
394 .end = 0x001ffff,
395 .name = "sys",
396 },
397 [S2] = {
398 .start = 0x0060000,
399 .end = 0x00603ff,
400 .name = "s2",
401 },
402 [PTP] = {
403 .start = 0x0090000,
404 .end = 0x00900cb,
405 .name = "ptp",
406 },
407 [GCB] = {
408 .start = 0x0070000,
409 .end = 0x00701ff,
410 .name = "devcpu_gcb",
411 },
412};
413
414static const struct resource vsc9953_port_io_res[] = {
415 {
416 .start = 0x0100000,
417 .end = 0x010ffff,
418 .name = "port0",
419 },
420 {
421 .start = 0x0110000,
422 .end = 0x011ffff,
423 .name = "port1",
424 },
425 {
426 .start = 0x0120000,
427 .end = 0x012ffff,
428 .name = "port2",
429 },
430 {
431 .start = 0x0130000,
432 .end = 0x013ffff,
433 .name = "port3",
434 },
435 {
436 .start = 0x0140000,
437 .end = 0x014ffff,
438 .name = "port4",
439 },
440 {
441 .start = 0x0150000,
442 .end = 0x015ffff,
443 .name = "port5",
444 },
445 {
446 .start = 0x0160000,
447 .end = 0x016ffff,
448 .name = "port6",
449 },
450 {
451 .start = 0x0170000,
452 .end = 0x017ffff,
453 .name = "port7",
454 },
455 {
456 .start = 0x0180000,
457 .end = 0x018ffff,
458 .name = "port8",
459 },
460 {
461 .start = 0x0190000,
462 .end = 0x019ffff,
463 .name = "port9",
464 },
465};
466
467static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {
468 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10),
469 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9),
470 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
471 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
472 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
473 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
474 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
475 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
476 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
477 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
478 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
479 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
480 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
481 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
482 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
483 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
484 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
485 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
486 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
487 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
488 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
489 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
490 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
491 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
492 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
493 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
494 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
495 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
496 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7),
497 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6),
498 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5),
499 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
500 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2),
501 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3),
502
503 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4),
504 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4),
505 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4),
506 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4),
507 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4),
508 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4),
509 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4),
510 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4),
511 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4),
512 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4),
513 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4),
514};
515
516static const struct ocelot_stat_layout vsc9953_stats_layout[] = {
517 { .offset = 0x00, .name = "rx_octets", },
518 { .offset = 0x01, .name = "rx_unicast", },
519 { .offset = 0x02, .name = "rx_multicast", },
520 { .offset = 0x03, .name = "rx_broadcast", },
521 { .offset = 0x04, .name = "rx_shorts", },
522 { .offset = 0x05, .name = "rx_fragments", },
523 { .offset = 0x06, .name = "rx_jabbers", },
524 { .offset = 0x07, .name = "rx_crc_align_errs", },
525 { .offset = 0x08, .name = "rx_sym_errs", },
526 { .offset = 0x09, .name = "rx_frames_below_65_octets", },
527 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", },
528 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", },
529 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", },
530 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", },
531 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", },
532 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", },
533 { .offset = 0x10, .name = "rx_pause", },
534 { .offset = 0x11, .name = "rx_control", },
535 { .offset = 0x12, .name = "rx_longs", },
536 { .offset = 0x13, .name = "rx_classified_drops", },
537 { .offset = 0x14, .name = "rx_red_prio_0", },
538 { .offset = 0x15, .name = "rx_red_prio_1", },
539 { .offset = 0x16, .name = "rx_red_prio_2", },
540 { .offset = 0x17, .name = "rx_red_prio_3", },
541 { .offset = 0x18, .name = "rx_red_prio_4", },
542 { .offset = 0x19, .name = "rx_red_prio_5", },
543 { .offset = 0x1A, .name = "rx_red_prio_6", },
544 { .offset = 0x1B, .name = "rx_red_prio_7", },
545 { .offset = 0x1C, .name = "rx_yellow_prio_0", },
546 { .offset = 0x1D, .name = "rx_yellow_prio_1", },
547 { .offset = 0x1E, .name = "rx_yellow_prio_2", },
548 { .offset = 0x1F, .name = "rx_yellow_prio_3", },
549 { .offset = 0x20, .name = "rx_yellow_prio_4", },
550 { .offset = 0x21, .name = "rx_yellow_prio_5", },
551 { .offset = 0x22, .name = "rx_yellow_prio_6", },
552 { .offset = 0x23, .name = "rx_yellow_prio_7", },
553 { .offset = 0x24, .name = "rx_green_prio_0", },
554 { .offset = 0x25, .name = "rx_green_prio_1", },
555 { .offset = 0x26, .name = "rx_green_prio_2", },
556 { .offset = 0x27, .name = "rx_green_prio_3", },
557 { .offset = 0x28, .name = "rx_green_prio_4", },
558 { .offset = 0x29, .name = "rx_green_prio_5", },
559 { .offset = 0x2A, .name = "rx_green_prio_6", },
560 { .offset = 0x2B, .name = "rx_green_prio_7", },
561 { .offset = 0x40, .name = "tx_octets", },
562 { .offset = 0x41, .name = "tx_unicast", },
563 { .offset = 0x42, .name = "tx_multicast", },
564 { .offset = 0x43, .name = "tx_broadcast", },
565 { .offset = 0x44, .name = "tx_collision", },
566 { .offset = 0x45, .name = "tx_drops", },
567 { .offset = 0x46, .name = "tx_pause", },
568 { .offset = 0x47, .name = "tx_frames_below_65_octets", },
569 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", },
570 { .offset = 0x49, .name = "tx_frames_128_255_octets", },
571 { .offset = 0x4A, .name = "tx_frames_256_511_octets", },
572 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", },
573 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", },
574 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", },
575 { .offset = 0x4E, .name = "tx_yellow_prio_0", },
576 { .offset = 0x4F, .name = "tx_yellow_prio_1", },
577 { .offset = 0x50, .name = "tx_yellow_prio_2", },
578 { .offset = 0x51, .name = "tx_yellow_prio_3", },
579 { .offset = 0x52, .name = "tx_yellow_prio_4", },
580 { .offset = 0x53, .name = "tx_yellow_prio_5", },
581 { .offset = 0x54, .name = "tx_yellow_prio_6", },
582 { .offset = 0x55, .name = "tx_yellow_prio_7", },
583 { .offset = 0x56, .name = "tx_green_prio_0", },
584 { .offset = 0x57, .name = "tx_green_prio_1", },
585 { .offset = 0x58, .name = "tx_green_prio_2", },
586 { .offset = 0x59, .name = "tx_green_prio_3", },
587 { .offset = 0x5A, .name = "tx_green_prio_4", },
588 { .offset = 0x5B, .name = "tx_green_prio_5", },
589 { .offset = 0x5C, .name = "tx_green_prio_6", },
590 { .offset = 0x5D, .name = "tx_green_prio_7", },
591 { .offset = 0x5E, .name = "tx_aged", },
592 { .offset = 0x80, .name = "drop_local", },
593 { .offset = 0x81, .name = "drop_tail", },
594 { .offset = 0x82, .name = "drop_yellow_prio_0", },
595 { .offset = 0x83, .name = "drop_yellow_prio_1", },
596 { .offset = 0x84, .name = "drop_yellow_prio_2", },
597 { .offset = 0x85, .name = "drop_yellow_prio_3", },
598 { .offset = 0x86, .name = "drop_yellow_prio_4", },
599 { .offset = 0x87, .name = "drop_yellow_prio_5", },
600 { .offset = 0x88, .name = "drop_yellow_prio_6", },
601 { .offset = 0x89, .name = "drop_yellow_prio_7", },
602 { .offset = 0x8A, .name = "drop_green_prio_0", },
603 { .offset = 0x8B, .name = "drop_green_prio_1", },
604 { .offset = 0x8C, .name = "drop_green_prio_2", },
605 { .offset = 0x8D, .name = "drop_green_prio_3", },
606 { .offset = 0x8E, .name = "drop_green_prio_4", },
607 { .offset = 0x8F, .name = "drop_green_prio_5", },
608 { .offset = 0x90, .name = "drop_green_prio_6", },
609 { .offset = 0x91, .name = "drop_green_prio_7", },
610};
611
612static struct vcap_field vsc9953_vcap_is2_keys[] = {
613
614 [VCAP_IS2_TYPE] = { 0, 4},
615 [VCAP_IS2_HK_FIRST] = { 4, 1},
616 [VCAP_IS2_HK_PAG] = { 5, 8},
617 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11},
618 [VCAP_IS2_HK_RSV2] = { 24, 1},
619 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1},
620 [VCAP_IS2_HK_L2_MC] = { 26, 1},
621 [VCAP_IS2_HK_L2_BC] = { 27, 1},
622 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1},
623 [VCAP_IS2_HK_VID] = { 29, 12},
624 [VCAP_IS2_HK_DEI] = { 41, 1},
625 [VCAP_IS2_HK_PCP] = { 42, 3},
626
627 [VCAP_IS2_HK_L2_DMAC] = { 45, 48},
628 [VCAP_IS2_HK_L2_SMAC] = { 93, 48},
629
630 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16},
631 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16},
632 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8},
633 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3},
634
635 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40},
636
637 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40},
638
639 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48},
640 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1},
641 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1},
642 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1},
643 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1},
644 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1},
645 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1},
646 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2},
647 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32},
648 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32},
649 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1},
650
651 [VCAP_IS2_HK_IP4] = { 45, 1},
652 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1},
653 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1},
654 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1},
655 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1},
656 [VCAP_IS2_HK_L3_TOS] = { 50, 8},
657 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32},
658 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32},
659 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1},
660
661 [VCAP_IS2_HK_TCP] = {123, 1},
662 [VCAP_IS2_HK_L4_DPORT] = {124, 16},
663 [VCAP_IS2_HK_L4_SPORT] = {140, 16},
664 [VCAP_IS2_HK_L4_RNG] = {156, 8},
665 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1},
666 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1},
667 [VCAP_IS2_HK_L4_FIN] = {166, 1},
668 [VCAP_IS2_HK_L4_SYN] = {167, 1},
669 [VCAP_IS2_HK_L4_RST] = {168, 1},
670 [VCAP_IS2_HK_L4_PSH] = {169, 1},
671 [VCAP_IS2_HK_L4_ACK] = {170, 1},
672 [VCAP_IS2_HK_L4_URG] = {171, 1},
673
674 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8},
675 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56},
676
677 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1},
678 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128},
679 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8},
680};
681
682static struct vcap_field vsc9953_vcap_is2_actions[] = {
683 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
684 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
685 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
686 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
687 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
688 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
689 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
690 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8},
691 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1},
692 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10},
693 [VCAP_IS2_ACT_ACL_ID] = { 44, 6},
694 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32},
695};
696
697static const struct vcap_props vsc9953_vcap_props[] = {
698 [VCAP_IS2] = {
699 .tg_width = 2,
700 .sw_count = 4,
701 .entry_count = VSC9953_VCAP_IS2_CNT,
702 .entry_width = VSC9953_VCAP_IS2_ENTRY_WIDTH,
703 .action_count = VSC9953_VCAP_IS2_CNT +
704 VSC9953_VCAP_PORT_CNT + 2,
705 .action_width = 101,
706 .action_type_width = 1,
707 .action_table = {
708 [IS2_ACTION_TYPE_NORMAL] = {
709 .width = 50,
710 .count = 2
711 },
712 [IS2_ACTION_TYPE_SMAC_SIP] = {
713 .width = 6,
714 .count = 4
715 },
716 },
717 .counter_words = 4,
718 .counter_width = 32,
719 },
720};
721
722#define VSC9953_INIT_TIMEOUT 50000
723#define VSC9953_GCB_RST_SLEEP 100
724#define VSC9953_SYS_RAMINIT_SLEEP 80
725#define VCS9953_MII_TIMEOUT 10000
726
727static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
728{
729 int val;
730
731 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
732
733 return val;
734}
735
736static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
737{
738 int val;
739
740 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val);
741
742 return val;
743}
744
745static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot)
746{
747 int val;
748
749 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val);
750
751 return val;
752}
753
754static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot)
755{
756 int val;
757
758 ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val);
759
760 return val;
761}
762
763static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
764 u16 value)
765{
766 struct ocelot *ocelot = bus->priv;
767 int err, cmd, val;
768
769
770 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
771 val, !val, 10, VCS9953_MII_TIMEOUT);
772 if (err) {
773 dev_err(ocelot->dev, "MDIO write: pending timeout\n");
774 goto out;
775 }
776
777 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
778 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
779 (value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
780 MSCC_MIIM_CMD_OPR_WRITE;
781
782 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
783
784out:
785 return err;
786}
787
788static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
789{
790 struct ocelot *ocelot = bus->priv;
791 int err, cmd, val;
792
793
794 err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
795 val, !val, 10, VCS9953_MII_TIMEOUT);
796 if (err) {
797 dev_err(ocelot->dev, "MDIO read: pending timeout\n");
798 goto out;
799 }
800
801
802 cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
803 (regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ;
804
805 ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
806
807
808 err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot,
809 val, !val, 10, VCS9953_MII_TIMEOUT);
810 if (err) {
811 dev_err(ocelot->dev, "MDIO read: busy timeout\n");
812 goto out;
813 }
814
815 val = ocelot_read(ocelot, GCB_MIIM_MII_DATA);
816
817 err = val & 0xFFFF;
818out:
819 return err;
820}
821
822static int vsc9953_reset(struct ocelot *ocelot)
823{
824 int val, err;
825
826
827 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
828
829 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val,
830 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT);
831 if (err) {
832 dev_err(ocelot->dev, "timeout: switch core reset\n");
833 return err;
834 }
835
836
837 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1);
838 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
839
840 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val,
841 VSC9953_SYS_RAMINIT_SLEEP,
842 VSC9953_INIT_TIMEOUT);
843 if (err) {
844 dev_err(ocelot->dev, "timeout: switch sram init\n");
845 return err;
846 }
847
848
849 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
850 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
851
852 return 0;
853}
854
855static void vsc9953_phylink_validate(struct ocelot *ocelot, int port,
856 unsigned long *supported,
857 struct phylink_link_state *state)
858{
859 struct ocelot_port *ocelot_port = ocelot->ports[port];
860 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
861
862 if (state->interface != PHY_INTERFACE_MODE_NA &&
863 state->interface != ocelot_port->phy_mode) {
864 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
865 return;
866 }
867
868 phylink_set_port_modes(mask);
869 phylink_set(mask, Autoneg);
870 phylink_set(mask, Pause);
871 phylink_set(mask, Asym_Pause);
872 phylink_set(mask, 10baseT_Full);
873 phylink_set(mask, 10baseT_Half);
874 phylink_set(mask, 100baseT_Full);
875 phylink_set(mask, 100baseT_Half);
876 phylink_set(mask, 1000baseT_Full);
877
878 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
879 phylink_set(mask, 2500baseT_Full);
880 phylink_set(mask, 2500baseX_Full);
881 }
882
883 bitmap_and(supported, supported, mask,
884 __ETHTOOL_LINK_MODE_MASK_NBITS);
885 bitmap_and(state->advertising, state->advertising, mask,
886 __ETHTOOL_LINK_MODE_MASK_NBITS);
887}
888
889static int vsc9953_prevalidate_phy_mode(struct ocelot *ocelot, int port,
890 phy_interface_t phy_mode)
891{
892 switch (phy_mode) {
893 case PHY_INTERFACE_MODE_INTERNAL:
894 if (port != 8 && port != 9)
895 return -ENOTSUPP;
896 return 0;
897 case PHY_INTERFACE_MODE_SGMII:
898 case PHY_INTERFACE_MODE_QSGMII:
899
900 if (port == 8 || port == 9)
901 return -ENOTSUPP;
902 return 0;
903 default:
904 return -ENOTSUPP;
905 }
906}
907
908
909
910
911
912static u16 vsc9953_wm_enc(u16 value)
913{
914 WARN_ON(value >= 16 * BIT(9));
915
916 if (value >= BIT(9))
917 return BIT(9) | (value / 16);
918
919 return value;
920}
921
922static const struct ocelot_ops vsc9953_ops = {
923 .reset = vsc9953_reset,
924 .wm_enc = vsc9953_wm_enc,
925};
926
927static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
928{
929 struct felix *felix = ocelot_to_felix(ocelot);
930 struct device *dev = ocelot->dev;
931 struct mii_bus *bus;
932 int port;
933 int rc;
934
935 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
936 sizeof(struct phy_device *),
937 GFP_KERNEL);
938 if (!felix->pcs) {
939 dev_err(dev, "failed to allocate array for PCS PHYs\n");
940 return -ENOMEM;
941 }
942
943 bus = devm_mdiobus_alloc(dev);
944 if (!bus)
945 return -ENOMEM;
946
947 bus->name = "VSC9953 internal MDIO bus";
948 bus->read = vsc9953_mdio_read;
949 bus->write = vsc9953_mdio_write;
950 bus->parent = dev;
951 bus->priv = ocelot;
952 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
953
954
955 rc = mdiobus_register(bus);
956 if (rc < 0) {
957 dev_err(dev, "failed to register MDIO bus\n");
958 return rc;
959 }
960
961 felix->imdio = bus;
962
963 for (port = 0; port < felix->info->num_ports; port++) {
964 struct ocelot_port *ocelot_port = ocelot->ports[port];
965 struct phy_device *pcs;
966 int addr = port + 4;
967
968 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
969 continue;
970
971 pcs = get_phy_device(felix->imdio, addr, false);
972 if (IS_ERR(pcs))
973 continue;
974
975 pcs->interface = ocelot_port->phy_mode;
976 felix->pcs[port] = pcs;
977
978 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr);
979 }
980
981 return 0;
982}
983
984static void vsc9953_xmit_template_populate(struct ocelot *ocelot, int port)
985{
986 struct ocelot_port *ocelot_port = ocelot->ports[port];
987 u8 *template = ocelot_port->xmit_template;
988 u64 bypass, dest, src;
989
990
991
992
993 src = ocelot->num_phys_ports;
994 dest = BIT(port);
995 bypass = true;
996
997 packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0);
998 packing(template, &dest, 67, 57, OCELOT_TAG_LEN, PACK, 0);
999 packing(template, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0);
1000}
1001
1002static const struct felix_info seville_info_vsc9953 = {
1003 .target_io_res = vsc9953_target_io_res,
1004 .port_io_res = vsc9953_port_io_res,
1005 .regfields = vsc9953_regfields,
1006 .map = vsc9953_regmap,
1007 .ops = &vsc9953_ops,
1008 .stats_layout = vsc9953_stats_layout,
1009 .num_stats = ARRAY_SIZE(vsc9953_stats_layout),
1010 .vcap_is2_keys = vsc9953_vcap_is2_keys,
1011 .vcap_is2_actions = vsc9953_vcap_is2_actions,
1012 .vcap = vsc9953_vcap_props,
1013 .shared_queue_sz = 2048 * 1024,
1014 .num_mact_rows = 2048,
1015 .num_ports = 10,
1016 .mdio_bus_alloc = vsc9953_mdio_bus_alloc,
1017 .mdio_bus_free = vsc9959_mdio_bus_free,
1018 .pcs_config = vsc9959_pcs_config,
1019 .pcs_link_up = vsc9959_pcs_link_up,
1020 .pcs_link_state = vsc9959_pcs_link_state,
1021 .phylink_validate = vsc9953_phylink_validate,
1022 .prevalidate_phy_mode = vsc9953_prevalidate_phy_mode,
1023 .xmit_template_populate = vsc9953_xmit_template_populate,
1024};
1025
1026static int seville_probe(struct platform_device *pdev)
1027{
1028 struct dsa_switch *ds;
1029 struct ocelot *ocelot;
1030 struct resource *res;
1031 struct felix *felix;
1032 int err;
1033
1034 felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
1035 if (!felix) {
1036 err = -ENOMEM;
1037 dev_err(&pdev->dev, "Failed to allocate driver memory\n");
1038 goto err_alloc_felix;
1039 }
1040
1041 platform_set_drvdata(pdev, felix);
1042
1043 ocelot = &felix->ocelot;
1044 ocelot->dev = &pdev->dev;
1045 felix->info = &seville_info_vsc9953;
1046
1047 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1048 felix->switch_base = res->start;
1049
1050 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1051 if (!ds) {
1052 err = -ENOMEM;
1053 dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1054 goto err_alloc_ds;
1055 }
1056
1057 ds->dev = &pdev->dev;
1058 ds->num_ports = felix->info->num_ports;
1059 ds->ops = &felix_switch_ops;
1060 ds->priv = ocelot;
1061 felix->ds = ds;
1062
1063 err = dsa_register_switch(ds);
1064 if (err) {
1065 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1066 goto err_register_ds;
1067 }
1068
1069 return 0;
1070
1071err_register_ds:
1072 kfree(ds);
1073err_alloc_ds:
1074err_alloc_felix:
1075 kfree(felix);
1076 return err;
1077}
1078
1079static int seville_remove(struct platform_device *pdev)
1080{
1081 struct felix *felix;
1082
1083 felix = platform_get_drvdata(pdev);
1084
1085 dsa_unregister_switch(felix->ds);
1086
1087 kfree(felix->ds);
1088 kfree(felix);
1089
1090 return 0;
1091}
1092
1093static const struct of_device_id seville_of_match[] = {
1094 { .compatible = "mscc,vsc9953-switch" },
1095 { },
1096};
1097MODULE_DEVICE_TABLE(of, seville_of_match);
1098
1099struct platform_driver seville_vsc9953_driver = {
1100 .probe = seville_probe,
1101 .remove = seville_remove,
1102 .driver = {
1103 .name = "mscc_seville",
1104 .of_match_table = of_match_ptr(seville_of_match),
1105 },
1106};
1107
