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18#include <linux/pci.h>
19#include <linux/if_vlan.h>
20#include "liquidio_common.h"
21#include "octeon_droq.h"
22#include "octeon_iq.h"
23#include "response_manager.h"
24#include "octeon_device.h"
25#include "octeon_nic.h"
26#include "octeon_main.h"
27#include "octeon_network.h"
28
29
30#define LIO_OOM_POLL_INTERVAL_MS 250
31
32#define OCTNIC_MAX_SG MAX_SKB_FRAGS
33
34
35
36
37
38void lio_delete_glists(struct lio *lio)
39{
40 struct octnic_gather *g;
41 int i;
42
43 kfree(lio->glist_lock);
44 lio->glist_lock = NULL;
45
46 if (!lio->glist)
47 return;
48
49 for (i = 0; i < lio->oct_dev->num_iqs; i++) {
50 do {
51 g = (struct octnic_gather *)
52 lio_list_delete_head(&lio->glist[i]);
53 kfree(g);
54 } while (g);
55
56 if (lio->glists_virt_base && lio->glists_virt_base[i] &&
57 lio->glists_dma_base && lio->glists_dma_base[i]) {
58 lio_dma_free(lio->oct_dev,
59 lio->glist_entry_size * lio->tx_qsize,
60 lio->glists_virt_base[i],
61 lio->glists_dma_base[i]);
62 }
63 }
64
65 kfree(lio->glists_virt_base);
66 lio->glists_virt_base = NULL;
67
68 kfree(lio->glists_dma_base);
69 lio->glists_dma_base = NULL;
70
71 kfree(lio->glist);
72 lio->glist = NULL;
73}
74
75
76
77
78
79int lio_setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
80{
81 struct octnic_gather *g;
82 int i, j;
83
84 lio->glist_lock =
85 kcalloc(num_iqs, sizeof(*lio->glist_lock), GFP_KERNEL);
86 if (!lio->glist_lock)
87 return -ENOMEM;
88
89 lio->glist =
90 kcalloc(num_iqs, sizeof(*lio->glist), GFP_KERNEL);
91 if (!lio->glist) {
92 kfree(lio->glist_lock);
93 lio->glist_lock = NULL;
94 return -ENOMEM;
95 }
96
97 lio->glist_entry_size =
98 ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
99
100
101
102
103 lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
104 GFP_KERNEL);
105 lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
106 GFP_KERNEL);
107
108 if (!lio->glists_virt_base || !lio->glists_dma_base) {
109 lio_delete_glists(lio);
110 return -ENOMEM;
111 }
112
113 for (i = 0; i < num_iqs; i++) {
114 int numa_node = dev_to_node(&oct->pci_dev->dev);
115
116 spin_lock_init(&lio->glist_lock[i]);
117
118 INIT_LIST_HEAD(&lio->glist[i]);
119
120 lio->glists_virt_base[i] =
121 lio_dma_alloc(oct,
122 lio->glist_entry_size * lio->tx_qsize,
123 &lio->glists_dma_base[i]);
124
125 if (!lio->glists_virt_base[i]) {
126 lio_delete_glists(lio);
127 return -ENOMEM;
128 }
129
130 for (j = 0; j < lio->tx_qsize; j++) {
131 g = kzalloc_node(sizeof(*g), GFP_KERNEL,
132 numa_node);
133 if (!g)
134 g = kzalloc(sizeof(*g), GFP_KERNEL);
135 if (!g)
136 break;
137
138 g->sg = lio->glists_virt_base[i] +
139 (j * lio->glist_entry_size);
140
141 g->sg_dma_ptr = lio->glists_dma_base[i] +
142 (j * lio->glist_entry_size);
143
144 list_add_tail(&g->list, &lio->glist[i]);
145 }
146
147 if (j != lio->tx_qsize) {
148 lio_delete_glists(lio);
149 return -ENOMEM;
150 }
151 }
152
153 return 0;
154}
155
156int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1)
157{
158 struct lio *lio = GET_LIO(netdev);
159 struct octeon_device *oct = lio->oct_dev;
160 struct octnic_ctrl_pkt nctrl;
161 int ret = 0;
162
163 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
164
165 nctrl.ncmd.u64 = 0;
166 nctrl.ncmd.s.cmd = cmd;
167 nctrl.ncmd.s.param1 = param1;
168 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
169 nctrl.netpndev = (u64)netdev;
170 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
171
172 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
173 if (ret) {
174 dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
175 ret);
176 if (ret > 0)
177 ret = -EIO;
178 }
179 return ret;
180}
181
182void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
183 unsigned int bytes_compl)
184{
185 struct netdev_queue *netdev_queue = txq;
186
187 netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
188}
189
190void octeon_update_tx_completion_counters(void *buf, int reqtype,
191 unsigned int *pkts_compl,
192 unsigned int *bytes_compl)
193{
194 struct octnet_buf_free_info *finfo;
195 struct sk_buff *skb = NULL;
196 struct octeon_soft_command *sc;
197
198 switch (reqtype) {
199 case REQTYPE_NORESP_NET:
200 case REQTYPE_NORESP_NET_SG:
201 finfo = buf;
202 skb = finfo->skb;
203 break;
204
205 case REQTYPE_RESP_NET_SG:
206 case REQTYPE_RESP_NET:
207 sc = buf;
208 skb = sc->callback_arg;
209 break;
210
211 default:
212 return;
213 }
214
215 (*pkts_compl)++;
216 *bytes_compl += skb->len;
217}
218
219int octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
220{
221 struct octnet_buf_free_info *finfo;
222 struct sk_buff *skb;
223 struct octeon_soft_command *sc;
224 struct netdev_queue *txq;
225
226 switch (reqtype) {
227 case REQTYPE_NORESP_NET:
228 case REQTYPE_NORESP_NET_SG:
229 finfo = buf;
230 skb = finfo->skb;
231 break;
232
233 case REQTYPE_RESP_NET_SG:
234 case REQTYPE_RESP_NET:
235 sc = buf;
236 skb = sc->callback_arg;
237 break;
238
239 default:
240 return 0;
241 }
242
243 txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
244 netdev_tx_sent_queue(txq, skb->len);
245
246 return netif_xmit_stopped(txq);
247}
248
249void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
250{
251 struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
252 struct net_device *netdev = (struct net_device *)nctrl->netpndev;
253 struct lio *lio = GET_LIO(netdev);
254 struct octeon_device *oct = lio->oct_dev;
255 u8 *mac;
256
257 if (nctrl->sc_status)
258 return;
259
260 switch (nctrl->ncmd.s.cmd) {
261 case OCTNET_CMD_CHANGE_DEVFLAGS:
262 case OCTNET_CMD_SET_MULTI_LIST:
263 case OCTNET_CMD_SET_UC_LIST:
264 break;
265
266 case OCTNET_CMD_CHANGE_MACADDR:
267 mac = ((u8 *)&nctrl->udd[0]) + 2;
268 if (nctrl->ncmd.s.param1) {
269
270 int vfidx = nctrl->ncmd.s.param1 - 1;
271 bool mac_is_admin_assigned = nctrl->ncmd.s.param2;
272
273 if (mac_is_admin_assigned)
274 netif_info(lio, probe, lio->netdev,
275 "MAC Address %pM is configured for VF %d\n",
276 mac, vfidx);
277 } else {
278 netif_info(lio, probe, lio->netdev,
279 " MACAddr changed to %pM\n",
280 mac);
281 }
282 break;
283
284 case OCTNET_CMD_GPIO_ACCESS:
285 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
286
287 break;
288
289 case OCTNET_CMD_ID_ACTIVE:
290 netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
291
292 break;
293
294 case OCTNET_CMD_LRO_ENABLE:
295 dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
296 break;
297
298 case OCTNET_CMD_LRO_DISABLE:
299 dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
300 netdev->name);
301 break;
302
303 case OCTNET_CMD_VERBOSE_ENABLE:
304 dev_info(&oct->pci_dev->dev, "%s Firmware debug enabled\n",
305 netdev->name);
306 break;
307
308 case OCTNET_CMD_VERBOSE_DISABLE:
309 dev_info(&oct->pci_dev->dev, "%s Firmware debug disabled\n",
310 netdev->name);
311 break;
312
313 case OCTNET_CMD_VLAN_FILTER_CTL:
314 if (nctrl->ncmd.s.param1)
315 dev_info(&oct->pci_dev->dev,
316 "%s VLAN filter enabled\n", netdev->name);
317 else
318 dev_info(&oct->pci_dev->dev,
319 "%s VLAN filter disabled\n", netdev->name);
320 break;
321
322 case OCTNET_CMD_ADD_VLAN_FILTER:
323 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d added\n",
324 netdev->name, nctrl->ncmd.s.param1);
325 break;
326
327 case OCTNET_CMD_DEL_VLAN_FILTER:
328 dev_info(&oct->pci_dev->dev, "%s VLAN filter %d removed\n",
329 netdev->name, nctrl->ncmd.s.param1);
330 break;
331
332 case OCTNET_CMD_SET_SETTINGS:
333 dev_info(&oct->pci_dev->dev, "%s settings changed\n",
334 netdev->name);
335
336 break;
337
338
339
340
341 case OCTNET_CMD_TNL_RX_CSUM_CTL:
342 if (nctrl->ncmd.s.param1 == OCTNET_CMD_RXCSUM_ENABLE) {
343 netif_info(lio, probe, lio->netdev,
344 "RX Checksum Offload Enabled\n");
345 } else if (nctrl->ncmd.s.param1 ==
346 OCTNET_CMD_RXCSUM_DISABLE) {
347 netif_info(lio, probe, lio->netdev,
348 "RX Checksum Offload Disabled\n");
349 }
350 break;
351
352
353
354
355 case OCTNET_CMD_TNL_TX_CSUM_CTL:
356 if (nctrl->ncmd.s.param1 == OCTNET_CMD_TXCSUM_ENABLE) {
357 netif_info(lio, probe, lio->netdev,
358 "TX Checksum Offload Enabled\n");
359 } else if (nctrl->ncmd.s.param1 ==
360 OCTNET_CMD_TXCSUM_DISABLE) {
361 netif_info(lio, probe, lio->netdev,
362 "TX Checksum Offload Disabled\n");
363 }
364 break;
365
366
367
368
369 case OCTNET_CMD_VXLAN_PORT_CONFIG:
370 if (nctrl->ncmd.s.more == OCTNET_CMD_VXLAN_PORT_ADD) {
371 netif_info(lio, probe, lio->netdev,
372 "VxLAN Destination UDP PORT:%d ADDED\n",
373 nctrl->ncmd.s.param1);
374 } else if (nctrl->ncmd.s.more ==
375 OCTNET_CMD_VXLAN_PORT_DEL) {
376 netif_info(lio, probe, lio->netdev,
377 "VxLAN Destination UDP PORT:%d DELETED\n",
378 nctrl->ncmd.s.param1);
379 }
380 break;
381
382 case OCTNET_CMD_SET_FLOW_CTL:
383 netif_info(lio, probe, lio->netdev, "Set RX/TX flow control parameters\n");
384 break;
385
386 case OCTNET_CMD_QUEUE_COUNT_CTL:
387 netif_info(lio, probe, lio->netdev, "Queue count updated to %d\n",
388 nctrl->ncmd.s.param1);
389 break;
390
391 default:
392 dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
393 nctrl->ncmd.s.cmd);
394 }
395}
396
397void octeon_pf_changed_vf_macaddr(struct octeon_device *oct, u8 *mac)
398{
399 bool macaddr_changed = false;
400 struct net_device *netdev;
401 struct lio *lio;
402
403 rtnl_lock();
404
405 netdev = oct->props[0].netdev;
406 lio = GET_LIO(netdev);
407
408 lio->linfo.macaddr_is_admin_asgnd = true;
409
410 if (!ether_addr_equal(netdev->dev_addr, mac)) {
411 macaddr_changed = true;
412 ether_addr_copy(netdev->dev_addr, mac);
413 ether_addr_copy(((u8 *)&lio->linfo.hw_addr) + 2, mac);
414 call_netdevice_notifiers(NETDEV_CHANGEADDR, netdev);
415 }
416
417 rtnl_unlock();
418
419 if (macaddr_changed)
420 dev_info(&oct->pci_dev->dev,
421 "PF changed VF's MAC address to %pM\n", mac);
422
423
424
425
426}
427
428void octeon_schedule_rxq_oom_work(struct octeon_device *oct,
429 struct octeon_droq *droq)
430{
431 struct net_device *netdev = oct->props[0].netdev;
432 struct lio *lio = GET_LIO(netdev);
433 struct cavium_wq *wq = &lio->rxq_status_wq[droq->q_no];
434
435 queue_delayed_work(wq->wq, &wq->wk.work,
436 msecs_to_jiffies(LIO_OOM_POLL_INTERVAL_MS));
437}
438
439static void octnet_poll_check_rxq_oom_status(struct work_struct *work)
440{
441 struct cavium_wk *wk = (struct cavium_wk *)work;
442 struct lio *lio = (struct lio *)wk->ctxptr;
443 struct octeon_device *oct = lio->oct_dev;
444 int q_no = wk->ctxul;
445 struct octeon_droq *droq = oct->droq[q_no];
446
447 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING) || !droq)
448 return;
449
450 if (octeon_retry_droq_refill(droq))
451 octeon_schedule_rxq_oom_work(oct, droq);
452}
453
454int setup_rx_oom_poll_fn(struct net_device *netdev)
455{
456 struct lio *lio = GET_LIO(netdev);
457 struct octeon_device *oct = lio->oct_dev;
458 struct cavium_wq *wq;
459 int q, q_no;
460
461 for (q = 0; q < oct->num_oqs; q++) {
462 q_no = lio->linfo.rxpciq[q].s.q_no;
463 wq = &lio->rxq_status_wq[q_no];
464 wq->wq = alloc_workqueue("rxq-oom-status",
465 WQ_MEM_RECLAIM, 0);
466 if (!wq->wq) {
467 dev_err(&oct->pci_dev->dev, "unable to create cavium rxq oom status wq\n");
468 return -ENOMEM;
469 }
470
471 INIT_DELAYED_WORK(&wq->wk.work,
472 octnet_poll_check_rxq_oom_status);
473 wq->wk.ctxptr = lio;
474 wq->wk.ctxul = q_no;
475 }
476
477 return 0;
478}
479
480void cleanup_rx_oom_poll_fn(struct net_device *netdev)
481{
482 struct lio *lio = GET_LIO(netdev);
483 struct octeon_device *oct = lio->oct_dev;
484 struct cavium_wq *wq;
485 int q_no;
486
487 for (q_no = 0; q_no < oct->num_oqs; q_no++) {
488 wq = &lio->rxq_status_wq[q_no];
489 if (wq->wq) {
490 cancel_delayed_work_sync(&wq->wk.work);
491 flush_workqueue(wq->wq);
492 destroy_workqueue(wq->wq);
493 wq->wq = NULL;
494 }
495 }
496}
497
498
499static void lio_update_txq_status(struct octeon_device *oct, int iq_num)
500{
501 struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
502 struct net_device *netdev;
503 struct lio *lio;
504
505 netdev = oct->props[iq->ifidx].netdev;
506
507
508
509
510 if (!netdev)
511 return;
512
513 lio = GET_LIO(netdev);
514 if (__netif_subqueue_stopped(netdev, iq->q_index) &&
515 lio->linfo.link.s.link_up &&
516 (!octnet_iq_is_full(oct, iq_num))) {
517 netif_wake_subqueue(netdev, iq->q_index);
518 INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num,
519 tx_restart, 1);
520 }
521}
522
523
524
525
526
527
528
529
530
531static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
532 int desc_size, void *app_ctx)
533{
534 int ret_val;
535
536 dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
537
538 ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
539 if (ret_val < 0)
540 return ret_val;
541
542 if (ret_val == 1) {
543 dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
544 return 0;
545 }
546
547
548 octeon_set_droq_pkt_op(oct, q_no, 1);
549
550
551
552
553 writel(oct->droq[q_no]->max_count, oct->droq[q_no]->pkts_credit_reg);
554
555 return ret_val;
556}
557
558
559
560
561
562
563
564
565
566static void
567liquidio_push_packet(u32 octeon_id __attribute__((unused)),
568 void *skbuff,
569 u32 len,
570 union octeon_rh *rh,
571 void *param,
572 void *arg)
573{
574 struct net_device *netdev = (struct net_device *)arg;
575 struct octeon_droq *droq =
576 container_of(param, struct octeon_droq, napi);
577 struct sk_buff *skb = (struct sk_buff *)skbuff;
578 struct skb_shared_hwtstamps *shhwtstamps;
579 struct napi_struct *napi = param;
580 u16 vtag = 0;
581 u32 r_dh_off;
582 u64 ns;
583
584 if (netdev) {
585 struct lio *lio = GET_LIO(netdev);
586 struct octeon_device *oct = lio->oct_dev;
587
588
589 if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
590 recv_buffer_free(skb);
591 droq->stats.rx_dropped++;
592 return;
593 }
594
595 skb->dev = netdev;
596
597 skb_record_rx_queue(skb, droq->q_no);
598 if (likely(len > MIN_SKB_SIZE)) {
599 struct octeon_skb_page_info *pg_info;
600 unsigned char *va;
601
602 pg_info = ((struct octeon_skb_page_info *)(skb->cb));
603 if (pg_info->page) {
604
605 va = page_address(pg_info->page) +
606 pg_info->page_offset;
607 memcpy(skb->data, va, MIN_SKB_SIZE);
608 skb_put(skb, MIN_SKB_SIZE);
609 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
610 pg_info->page,
611 pg_info->page_offset +
612 MIN_SKB_SIZE,
613 len - MIN_SKB_SIZE,
614 LIO_RXBUFFER_SZ);
615 }
616 } else {
617 struct octeon_skb_page_info *pg_info =
618 ((struct octeon_skb_page_info *)(skb->cb));
619 skb_copy_to_linear_data(skb, page_address(pg_info->page)
620 + pg_info->page_offset, len);
621 skb_put(skb, len);
622 put_page(pg_info->page);
623 }
624
625 r_dh_off = (rh->r_dh.len - 1) * BYTES_PER_DHLEN_UNIT;
626
627 if (oct->ptp_enable) {
628 if (rh->r_dh.has_hwtstamp) {
629
630
631
632 if (ifstate_check
633 (lio,
634 LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
635
636
637
638 memcpy(&ns, (skb->data + r_dh_off),
639 sizeof(ns));
640 r_dh_off -= BYTES_PER_DHLEN_UNIT;
641 shhwtstamps = skb_hwtstamps(skb);
642 shhwtstamps->hwtstamp =
643 ns_to_ktime(ns +
644 lio->ptp_adjust);
645 }
646 }
647 }
648
649 if (rh->r_dh.has_hash) {
650 __be32 *hash_be = (__be32 *)(skb->data + r_dh_off);
651 u32 hash = be32_to_cpu(*hash_be);
652
653 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
654 r_dh_off -= BYTES_PER_DHLEN_UNIT;
655 }
656
657 skb_pull(skb, rh->r_dh.len * BYTES_PER_DHLEN_UNIT);
658 skb->protocol = eth_type_trans(skb, skb->dev);
659
660 if ((netdev->features & NETIF_F_RXCSUM) &&
661 (((rh->r_dh.encap_on) &&
662 (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) ||
663 (!(rh->r_dh.encap_on) &&
664 ((rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED) ==
665 CNNIC_CSUM_VERIFIED))))
666
667 skb->ip_summed = CHECKSUM_UNNECESSARY;
668 else
669 skb->ip_summed = CHECKSUM_NONE;
670
671
672
673
674 if (rh->r_dh.encap_on) {
675 skb->encapsulation = 1;
676 skb->csum_level = 1;
677 droq->stats.rx_vxlan++;
678 }
679
680
681 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
682 rh->r_dh.vlan) {
683 u16 priority = rh->r_dh.priority;
684 u16 vid = rh->r_dh.vlan;
685
686 vtag = (priority << VLAN_PRIO_SHIFT) | vid;
687 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
688 }
689
690 napi_gro_receive(napi, skb);
691
692 droq->stats.rx_bytes_received += len -
693 rh->r_dh.len * BYTES_PER_DHLEN_UNIT;
694 droq->stats.rx_pkts_received++;
695 } else {
696 recv_buffer_free(skb);
697 }
698}
699
700
701
702
703
704
705
706static void napi_schedule_wrapper(void *param)
707{
708 struct napi_struct *napi = param;
709
710 napi_schedule(napi);
711}
712
713
714
715
716
717static void liquidio_napi_drv_callback(void *arg)
718{
719 struct octeon_device *oct;
720 struct octeon_droq *droq = arg;
721 int this_cpu = smp_processor_id();
722
723 oct = droq->oct_dev;
724
725 if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct) ||
726 droq->cpu_id == this_cpu) {
727 napi_schedule_irqoff(&droq->napi);
728 } else {
729 call_single_data_t *csd = &droq->csd;
730
731 csd->func = napi_schedule_wrapper;
732 csd->info = &droq->napi;
733 csd->flags = 0;
734
735 smp_call_function_single_async(droq->cpu_id, csd);
736 }
737}
738
739
740
741
742
743
744static int liquidio_napi_poll(struct napi_struct *napi, int budget)
745{
746 struct octeon_instr_queue *iq;
747 struct octeon_device *oct;
748 struct octeon_droq *droq;
749 int tx_done = 0, iq_no;
750 int work_done;
751
752 droq = container_of(napi, struct octeon_droq, napi);
753 oct = droq->oct_dev;
754 iq_no = droq->q_no;
755
756
757 work_done = octeon_droq_process_poll_pkts(oct, droq, budget);
758
759
760 iq = oct->instr_queue[iq_no];
761 if (iq) {
762
763
764
765 if (atomic_read(&iq->instr_pending))
766
767 tx_done = octeon_flush_iq(oct, iq, budget);
768 else
769 tx_done = 1;
770
771
772
773
774 lio_update_txq_status(oct, iq_no);
775 } else {
776 dev_err(&oct->pci_dev->dev, "%s: iq (%d) num invalid\n",
777 __func__, iq_no);
778 }
779
780#define MAX_REG_CNT 2000000U
781
782 if ((work_done < budget && tx_done) ||
783 (iq && iq->pkt_in_done >= MAX_REG_CNT) ||
784 (droq->pkt_count >= MAX_REG_CNT)) {
785 napi_complete_done(napi, work_done);
786
787 octeon_enable_irq(droq->oct_dev, droq->q_no);
788 return 0;
789 }
790
791 return (!tx_done) ? (budget) : (work_done);
792}
793
794
795
796
797
798
799
800
801
802
803int liquidio_setup_io_queues(struct octeon_device *octeon_dev, int ifidx,
804 u32 num_iqs, u32 num_oqs)
805{
806 struct octeon_droq_ops droq_ops;
807 struct net_device *netdev;
808 struct octeon_droq *droq;
809 struct napi_struct *napi;
810 int cpu_id_modulus;
811 int num_tx_descs;
812 struct lio *lio;
813 int retval = 0;
814 int q, q_no;
815 int cpu_id;
816
817 netdev = octeon_dev->props[ifidx].netdev;
818
819 lio = GET_LIO(netdev);
820
821 memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
822
823 droq_ops.fptr = liquidio_push_packet;
824 droq_ops.farg = netdev;
825
826 droq_ops.poll_mode = 1;
827 droq_ops.napi_fn = liquidio_napi_drv_callback;
828 cpu_id = 0;
829 cpu_id_modulus = num_present_cpus();
830
831
832 for (q = 0; q < num_oqs; q++) {
833 q_no = lio->linfo.rxpciq[q].s.q_no;
834 dev_dbg(&octeon_dev->pci_dev->dev,
835 "%s index:%d linfo.rxpciq.s.q_no:%d\n",
836 __func__, q, q_no);
837 retval = octeon_setup_droq(
838 octeon_dev, q_no,
839 CFG_GET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(octeon_dev),
840 lio->ifidx),
841 CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(octeon_get_conf(octeon_dev),
842 lio->ifidx),
843 NULL);
844 if (retval) {
845 dev_err(&octeon_dev->pci_dev->dev,
846 "%s : Runtime DROQ(RxQ) creation failed.\n",
847 __func__);
848 return 1;
849 }
850
851 droq = octeon_dev->droq[q_no];
852 napi = &droq->napi;
853 dev_dbg(&octeon_dev->pci_dev->dev, "netif_napi_add netdev:%llx oct:%llx\n",
854 (u64)netdev, (u64)octeon_dev);
855 netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
856
857
858 droq->cpu_id = cpu_id;
859 cpu_id++;
860 if (cpu_id >= cpu_id_modulus)
861 cpu_id = 0;
862
863 octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
864 }
865
866 if (OCTEON_CN23XX_PF(octeon_dev) || OCTEON_CN23XX_VF(octeon_dev)) {
867
868
869
870
871
872 octeon_dev->droq[0]->ops.poll_mode = 0;
873 }
874
875
876 for (q = 0; q < num_iqs; q++) {
877 num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(
878 octeon_get_conf(octeon_dev), lio->ifidx);
879 retval = octeon_setup_iq(octeon_dev, ifidx, q,
880 lio->linfo.txpciq[q], num_tx_descs,
881 netdev_get_tx_queue(netdev, q));
882 if (retval) {
883 dev_err(&octeon_dev->pci_dev->dev,
884 " %s : Runtime IQ(TxQ) creation failed.\n",
885 __func__);
886 return 1;
887 }
888
889
890 if (!OCTEON_CN23XX_VF(octeon_dev) && octeon_dev->msix_on &&
891 octeon_dev->ioq_vector) {
892 struct octeon_ioq_vector *ioq_vector;
893
894 ioq_vector = &octeon_dev->ioq_vector[q];
895 netif_set_xps_queue(netdev,
896 &ioq_vector->affinity_mask,
897 ioq_vector->iq_index);
898 }
899 }
900
901 return 0;
902}
903
904static
905int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret)
906{
907 struct octeon_device *oct = droq->oct_dev;
908 struct octeon_device_priv *oct_priv =
909 (struct octeon_device_priv *)oct->priv;
910
911 if (droq->ops.poll_mode) {
912 droq->ops.napi_fn(droq);
913 } else {
914 if (ret & MSIX_PO_INT) {
915 if (OCTEON_CN23XX_VF(oct))
916 dev_err(&oct->pci_dev->dev,
917 "should not come here should not get rx when poll mode = 0 for vf\n");
918 tasklet_schedule(&oct_priv->droq_tasklet);
919 return 1;
920 }
921
922 if (ret & MSIX_PI_INT)
923 return 0;
924 }
925
926 return 0;
927}
928
929irqreturn_t
930liquidio_msix_intr_handler(int irq __attribute__((unused)), void *dev)
931{
932 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
933 struct octeon_device *oct = ioq_vector->oct_dev;
934 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
935 u64 ret;
936
937 ret = oct->fn_list.msix_interrupt_handler(ioq_vector);
938
939 if (ret & MSIX_PO_INT || ret & MSIX_PI_INT)
940 liquidio_schedule_msix_droq_pkt_handler(droq, ret);
941
942 return IRQ_HANDLED;
943}
944
945
946
947
948
949static void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
950{
951 struct octeon_device_priv *oct_priv =
952 (struct octeon_device_priv *)oct->priv;
953 struct octeon_droq *droq;
954 u64 oq_no;
955
956 if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
957 for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
958 oq_no++) {
959 if (!(oct->droq_intr & BIT_ULL(oq_no)))
960 continue;
961
962 droq = oct->droq[oq_no];
963
964 if (droq->ops.poll_mode) {
965 droq->ops.napi_fn(droq);
966 oct_priv->napi_mask |= BIT_ULL(oq_no);
967 } else {
968 tasklet_schedule(&oct_priv->droq_tasklet);
969 }
970 }
971 }
972}
973
974
975
976
977
978
979static
980irqreturn_t liquidio_legacy_intr_handler(int irq __attribute__((unused)),
981 void *dev)
982{
983 struct octeon_device *oct = (struct octeon_device *)dev;
984 irqreturn_t ret;
985
986
987 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
988
989 ret = oct->fn_list.process_interrupt_regs(oct);
990
991 if (ret == IRQ_HANDLED)
992 liquidio_schedule_droq_pkt_handlers(oct);
993
994
995 if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
996 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
997
998 return ret;
999}
1000
1001
1002
1003
1004
1005
1006
1007int octeon_setup_interrupt(struct octeon_device *oct, u32 num_ioqs)
1008{
1009 struct msix_entry *msix_entries;
1010 char *queue_irq_names = NULL;
1011 int i, num_interrupts = 0;
1012 int num_alloc_ioq_vectors;
1013 char *aux_irq_name = NULL;
1014 int num_ioq_vectors;
1015 int irqret, err;
1016
1017 if (oct->msix_on) {
1018 oct->num_msix_irqs = num_ioqs;
1019 if (OCTEON_CN23XX_PF(oct)) {
1020 num_interrupts = MAX_IOQ_INTERRUPTS_PER_PF + 1;
1021
1022
1023
1024
1025 oct->num_msix_irqs += 1;
1026 } else if (OCTEON_CN23XX_VF(oct)) {
1027 num_interrupts = MAX_IOQ_INTERRUPTS_PER_VF;
1028 }
1029
1030
1031 oct->irq_name_storage =
1032 kcalloc(num_interrupts, INTRNAMSIZ, GFP_KERNEL);
1033 if (!oct->irq_name_storage) {
1034 dev_err(&oct->pci_dev->dev, "Irq name storage alloc failed...\n");
1035 return -ENOMEM;
1036 }
1037
1038 queue_irq_names = oct->irq_name_storage;
1039
1040 if (OCTEON_CN23XX_PF(oct))
1041 aux_irq_name = &queue_irq_names
1042 [IRQ_NAME_OFF(MAX_IOQ_INTERRUPTS_PER_PF)];
1043
1044 oct->msix_entries = kcalloc(oct->num_msix_irqs,
1045 sizeof(struct msix_entry),
1046 GFP_KERNEL);
1047 if (!oct->msix_entries) {
1048 dev_err(&oct->pci_dev->dev, "Memory Alloc failed...\n");
1049 kfree(oct->irq_name_storage);
1050 oct->irq_name_storage = NULL;
1051 return -ENOMEM;
1052 }
1053
1054 msix_entries = (struct msix_entry *)oct->msix_entries;
1055
1056
1057
1058
1059 if (OCTEON_CN23XX_PF(oct)) {
1060 for (i = 0; i < oct->num_msix_irqs - 1; i++)
1061 msix_entries[i].entry =
1062 oct->sriov_info.pf_srn + i;
1063
1064 msix_entries[oct->num_msix_irqs - 1].entry =
1065 oct->sriov_info.trs;
1066 } else if (OCTEON_CN23XX_VF(oct)) {
1067 for (i = 0; i < oct->num_msix_irqs; i++)
1068 msix_entries[i].entry = i;
1069 }
1070 num_alloc_ioq_vectors = pci_enable_msix_range(
1071 oct->pci_dev, msix_entries,
1072 oct->num_msix_irqs,
1073 oct->num_msix_irqs);
1074 if (num_alloc_ioq_vectors < 0) {
1075 dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n");
1076 kfree(oct->msix_entries);
1077 oct->msix_entries = NULL;
1078 kfree(oct->irq_name_storage);
1079 oct->irq_name_storage = NULL;
1080 return num_alloc_ioq_vectors;
1081 }
1082
1083 dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n");
1084
1085 num_ioq_vectors = oct->num_msix_irqs;
1086
1087 if (OCTEON_CN23XX_PF(oct)) {
1088 num_ioq_vectors -= 1;
1089
1090 snprintf(aux_irq_name, INTRNAMSIZ,
1091 "LiquidIO%u-pf%u-aux", oct->octeon_id,
1092 oct->pf_num);
1093 irqret = request_irq(
1094 msix_entries[num_ioq_vectors].vector,
1095 liquidio_legacy_intr_handler, 0,
1096 aux_irq_name, oct);
1097 if (irqret) {
1098 dev_err(&oct->pci_dev->dev,
1099 "Request_irq failed for MSIX interrupt Error: %d\n",
1100 irqret);
1101 pci_disable_msix(oct->pci_dev);
1102 kfree(oct->msix_entries);
1103 kfree(oct->irq_name_storage);
1104 oct->irq_name_storage = NULL;
1105 oct->msix_entries = NULL;
1106 return irqret;
1107 }
1108 }
1109 for (i = 0 ; i < num_ioq_vectors ; i++) {
1110 if (OCTEON_CN23XX_PF(oct))
1111 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)],
1112 INTRNAMSIZ, "LiquidIO%u-pf%u-rxtx-%u",
1113 oct->octeon_id, oct->pf_num, i);
1114
1115 if (OCTEON_CN23XX_VF(oct))
1116 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)],
1117 INTRNAMSIZ, "LiquidIO%u-vf%u-rxtx-%u",
1118 oct->octeon_id, oct->vf_num, i);
1119
1120 irqret = request_irq(msix_entries[i].vector,
1121 liquidio_msix_intr_handler, 0,
1122 &queue_irq_names[IRQ_NAME_OFF(i)],
1123 &oct->ioq_vector[i]);
1124
1125 if (irqret) {
1126 dev_err(&oct->pci_dev->dev,
1127 "Request_irq failed for MSIX interrupt Error: %d\n",
1128 irqret);
1129
1130 free_irq(msix_entries[num_ioq_vectors].vector,
1131 oct);
1132
1133 while (i) {
1134 i--;
1135
1136 irq_set_affinity_hint(
1137 msix_entries[i].vector,
1138 NULL);
1139 free_irq(msix_entries[i].vector,
1140 &oct->ioq_vector[i]);
1141 }
1142 pci_disable_msix(oct->pci_dev);
1143 kfree(oct->msix_entries);
1144 kfree(oct->irq_name_storage);
1145 oct->irq_name_storage = NULL;
1146 oct->msix_entries = NULL;
1147 return irqret;
1148 }
1149 oct->ioq_vector[i].vector = msix_entries[i].vector;
1150
1151 irq_set_affinity_hint(msix_entries[i].vector,
1152 &oct->ioq_vector[i].affinity_mask
1153 );
1154 }
1155 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: MSI-X enabled\n",
1156 oct->octeon_id);
1157 } else {
1158 err = pci_enable_msi(oct->pci_dev);
1159 if (err)
1160 dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1161 err);
1162 else
1163 oct->flags |= LIO_FLAG_MSI_ENABLED;
1164
1165
1166 oct->irq_name_storage = kcalloc(1, INTRNAMSIZ, GFP_KERNEL);
1167 if (!oct->irq_name_storage)
1168 return -ENOMEM;
1169
1170 queue_irq_names = oct->irq_name_storage;
1171
1172 if (OCTEON_CN23XX_PF(oct))
1173 snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1174 "LiquidIO%u-pf%u-rxtx-%u",
1175 oct->octeon_id, oct->pf_num, 0);
1176
1177 if (OCTEON_CN23XX_VF(oct))
1178 snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1179 "LiquidIO%u-vf%u-rxtx-%u",
1180 oct->octeon_id, oct->vf_num, 0);
1181
1182 irqret = request_irq(oct->pci_dev->irq,
1183 liquidio_legacy_intr_handler,
1184 IRQF_SHARED,
1185 &queue_irq_names[IRQ_NAME_OFF(0)], oct);
1186 if (irqret) {
1187 if (oct->flags & LIO_FLAG_MSI_ENABLED)
1188 pci_disable_msi(oct->pci_dev);
1189 dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1190 irqret);
1191 kfree(oct->irq_name_storage);
1192 oct->irq_name_storage = NULL;
1193 return irqret;
1194 }
1195 }
1196 return 0;
1197}
1198
1199
1200
1201
1202
1203int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
1204{
1205 struct lio *lio = GET_LIO(netdev);
1206 struct octeon_device *oct = lio->oct_dev;
1207 struct octeon_soft_command *sc;
1208 union octnet_cmd *ncmd;
1209 int ret = 0;
1210
1211 sc = (struct octeon_soft_command *)
1212 octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE, 16, 0);
1213 if (!sc) {
1214 netif_info(lio, rx_err, lio->netdev,
1215 "Failed to allocate soft command\n");
1216 return -ENOMEM;
1217 }
1218
1219 ncmd = (union octnet_cmd *)sc->virtdptr;
1220
1221 init_completion(&sc->complete);
1222 sc->sc_status = OCTEON_REQUEST_PENDING;
1223
1224 ncmd->u64 = 0;
1225 ncmd->s.cmd = OCTNET_CMD_CHANGE_MTU;
1226 ncmd->s.param1 = new_mtu;
1227
1228 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1229
1230 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1231
1232 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1233 OPCODE_NIC_CMD, 0, 0, 0);
1234
1235 ret = octeon_send_soft_command(oct, sc);
1236 if (ret == IQ_SEND_FAILED) {
1237 netif_info(lio, rx_err, lio->netdev, "Failed to change MTU\n");
1238 octeon_free_soft_command(oct, sc);
1239 return -EINVAL;
1240 }
1241
1242
1243
1244 ret = wait_for_sc_completion_timeout(oct, sc, 0);
1245 if (ret)
1246 return ret;
1247
1248 if (sc->sc_status) {
1249 WRITE_ONCE(sc->caller_is_done, true);
1250 return -EINVAL;
1251 }
1252
1253 netdev->mtu = new_mtu;
1254 lio->mtu = new_mtu;
1255
1256 WRITE_ONCE(sc->caller_is_done, true);
1257 return 0;
1258}
1259
1260int lio_wait_for_clean_oq(struct octeon_device *oct)
1261{
1262 int retry = 100, pending_pkts = 0;
1263 int idx;
1264
1265 do {
1266 pending_pkts = 0;
1267
1268 for (idx = 0; idx < MAX_OCTEON_OUTPUT_QUEUES(oct); idx++) {
1269 if (!(oct->io_qmask.oq & BIT_ULL(idx)))
1270 continue;
1271 pending_pkts +=
1272 atomic_read(&oct->droq[idx]->pkts_pending);
1273 }
1274
1275 if (pending_pkts > 0)
1276 schedule_timeout_uninterruptible(1);
1277
1278 } while (retry-- && pending_pkts);
1279
1280 return pending_pkts;
1281}
1282
1283static void
1284octnet_nic_stats_callback(struct octeon_device *oct_dev,
1285 u32 status, void *ptr)
1286{
1287 struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1288 struct oct_nic_stats_resp *resp =
1289 (struct oct_nic_stats_resp *)sc->virtrptr;
1290 struct nic_rx_stats *rsp_rstats = &resp->stats.fromwire;
1291 struct nic_tx_stats *rsp_tstats = &resp->stats.fromhost;
1292 struct nic_rx_stats *rstats = &oct_dev->link_stats.fromwire;
1293 struct nic_tx_stats *tstats = &oct_dev->link_stats.fromhost;
1294
1295 if (status != OCTEON_REQUEST_TIMEOUT && !resp->status) {
1296 octeon_swap_8B_data((u64 *)&resp->stats,
1297 (sizeof(struct oct_link_stats)) >> 3);
1298
1299
1300 rstats->total_rcvd = rsp_rstats->total_rcvd;
1301 rstats->bytes_rcvd = rsp_rstats->bytes_rcvd;
1302 rstats->total_bcst = rsp_rstats->total_bcst;
1303 rstats->total_mcst = rsp_rstats->total_mcst;
1304 rstats->runts = rsp_rstats->runts;
1305 rstats->ctl_rcvd = rsp_rstats->ctl_rcvd;
1306
1307 rstats->fifo_err = rsp_rstats->fifo_err;
1308 rstats->dmac_drop = rsp_rstats->dmac_drop;
1309 rstats->fcs_err = rsp_rstats->fcs_err;
1310 rstats->jabber_err = rsp_rstats->jabber_err;
1311 rstats->l2_err = rsp_rstats->l2_err;
1312 rstats->frame_err = rsp_rstats->frame_err;
1313 rstats->red_drops = rsp_rstats->red_drops;
1314
1315
1316 rstats->fw_total_rcvd = rsp_rstats->fw_total_rcvd;
1317 rstats->fw_total_fwd = rsp_rstats->fw_total_fwd;
1318 rstats->fw_total_mcast = rsp_rstats->fw_total_mcast;
1319 rstats->fw_total_bcast = rsp_rstats->fw_total_bcast;
1320 rstats->fw_err_pko = rsp_rstats->fw_err_pko;
1321 rstats->fw_err_link = rsp_rstats->fw_err_link;
1322 rstats->fw_err_drop = rsp_rstats->fw_err_drop;
1323 rstats->fw_rx_vxlan = rsp_rstats->fw_rx_vxlan;
1324 rstats->fw_rx_vxlan_err = rsp_rstats->fw_rx_vxlan_err;
1325
1326
1327 rstats->fw_lro_pkts = rsp_rstats->fw_lro_pkts;
1328
1329 rstats->fw_lro_octs = rsp_rstats->fw_lro_octs;
1330
1331 rstats->fw_total_lro = rsp_rstats->fw_total_lro;
1332
1333 rstats->fw_lro_aborts = rsp_rstats->fw_lro_aborts;
1334 rstats->fw_lro_aborts_port = rsp_rstats->fw_lro_aborts_port;
1335 rstats->fw_lro_aborts_seq = rsp_rstats->fw_lro_aborts_seq;
1336 rstats->fw_lro_aborts_tsval = rsp_rstats->fw_lro_aborts_tsval;
1337 rstats->fw_lro_aborts_timer = rsp_rstats->fw_lro_aborts_timer;
1338
1339 rstats->fwd_rate = rsp_rstats->fwd_rate;
1340
1341
1342 tstats->total_pkts_sent = rsp_tstats->total_pkts_sent;
1343 tstats->total_bytes_sent = rsp_tstats->total_bytes_sent;
1344 tstats->mcast_pkts_sent = rsp_tstats->mcast_pkts_sent;
1345 tstats->bcast_pkts_sent = rsp_tstats->bcast_pkts_sent;
1346 tstats->ctl_sent = rsp_tstats->ctl_sent;
1347
1348 tstats->one_collision_sent = rsp_tstats->one_collision_sent;
1349
1350 tstats->multi_collision_sent = rsp_tstats->multi_collision_sent;
1351
1352 tstats->max_collision_fail = rsp_tstats->max_collision_fail;
1353
1354 tstats->max_deferral_fail = rsp_tstats->max_deferral_fail;
1355
1356 tstats->fifo_err = rsp_tstats->fifo_err;
1357 tstats->runts = rsp_tstats->runts;
1358
1359 tstats->total_collisions = rsp_tstats->total_collisions;
1360
1361
1362 tstats->fw_total_sent = rsp_tstats->fw_total_sent;
1363 tstats->fw_total_fwd = rsp_tstats->fw_total_fwd;
1364 tstats->fw_total_mcast_sent = rsp_tstats->fw_total_mcast_sent;
1365 tstats->fw_total_bcast_sent = rsp_tstats->fw_total_bcast_sent;
1366 tstats->fw_err_pko = rsp_tstats->fw_err_pko;
1367 tstats->fw_err_pki = rsp_tstats->fw_err_pki;
1368 tstats->fw_err_link = rsp_tstats->fw_err_link;
1369 tstats->fw_err_drop = rsp_tstats->fw_err_drop;
1370 tstats->fw_tso = rsp_tstats->fw_tso;
1371 tstats->fw_tso_fwd = rsp_tstats->fw_tso_fwd;
1372 tstats->fw_err_tso = rsp_tstats->fw_err_tso;
1373 tstats->fw_tx_vxlan = rsp_tstats->fw_tx_vxlan;
1374
1375 resp->status = 1;
1376 } else {
1377 dev_err(&oct_dev->pci_dev->dev, "sc OPCODE_NIC_PORT_STATS command failed\n");
1378 resp->status = -1;
1379 }
1380}
1381
1382static int lio_fetch_vf_stats(struct lio *lio)
1383{
1384 struct octeon_device *oct_dev = lio->oct_dev;
1385 struct octeon_soft_command *sc;
1386 struct oct_nic_vf_stats_resp *resp;
1387
1388 int retval;
1389
1390
1391 sc = (struct octeon_soft_command *)
1392 octeon_alloc_soft_command(oct_dev,
1393 0,
1394 sizeof(struct oct_nic_vf_stats_resp),
1395 0);
1396
1397 if (!sc) {
1398 dev_err(&oct_dev->pci_dev->dev, "Soft command allocation failed\n");
1399 retval = -ENOMEM;
1400 goto lio_fetch_vf_stats_exit;
1401 }
1402
1403 resp = (struct oct_nic_vf_stats_resp *)sc->virtrptr;
1404 memset(resp, 0, sizeof(struct oct_nic_vf_stats_resp));
1405
1406 init_completion(&sc->complete);
1407 sc->sc_status = OCTEON_REQUEST_PENDING;
1408
1409 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1410
1411 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1412 OPCODE_NIC_VF_PORT_STATS, 0, 0, 0);
1413
1414 retval = octeon_send_soft_command(oct_dev, sc);
1415 if (retval == IQ_SEND_FAILED) {
1416 octeon_free_soft_command(oct_dev, sc);
1417 goto lio_fetch_vf_stats_exit;
1418 }
1419
1420 retval =
1421 wait_for_sc_completion_timeout(oct_dev, sc,
1422 (2 * LIO_SC_MAX_TMO_MS));
1423 if (retval) {
1424 dev_err(&oct_dev->pci_dev->dev,
1425 "sc OPCODE_NIC_VF_PORT_STATS command failed\n");
1426 goto lio_fetch_vf_stats_exit;
1427 }
1428
1429 if (sc->sc_status != OCTEON_REQUEST_TIMEOUT && !resp->status) {
1430 octeon_swap_8B_data((u64 *)&resp->spoofmac_cnt,
1431 (sizeof(u64)) >> 3);
1432
1433 if (resp->spoofmac_cnt != 0) {
1434 dev_warn(&oct_dev->pci_dev->dev,
1435 "%llu Spoofed packets detected\n",
1436 resp->spoofmac_cnt);
1437 }
1438 }
1439 WRITE_ONCE(sc->caller_is_done, 1);
1440
1441lio_fetch_vf_stats_exit:
1442 return retval;
1443}
1444
1445void lio_fetch_stats(struct work_struct *work)
1446{
1447 struct cavium_wk *wk = (struct cavium_wk *)work;
1448 struct lio *lio = wk->ctxptr;
1449 struct octeon_device *oct_dev = lio->oct_dev;
1450 struct octeon_soft_command *sc;
1451 struct oct_nic_stats_resp *resp;
1452 unsigned long time_in_jiffies;
1453 int retval;
1454
1455 if (OCTEON_CN23XX_PF(oct_dev)) {
1456
1457 if (!(oct_dev->vfstats_poll % LIO_VFSTATS_POLL) &&
1458 (oct_dev->fw_info.app_cap_flags & LIQUIDIO_SPOOFCHK_CAP) &&
1459 oct_dev->sriov_info.num_vfs_alloced) {
1460 lio_fetch_vf_stats(lio);
1461 }
1462
1463 oct_dev->vfstats_poll++;
1464 }
1465
1466
1467 sc = (struct octeon_soft_command *)
1468 octeon_alloc_soft_command(oct_dev,
1469 0,
1470 sizeof(struct oct_nic_stats_resp),
1471 0);
1472
1473 if (!sc) {
1474 dev_err(&oct_dev->pci_dev->dev, "Soft command allocation failed\n");
1475 goto lio_fetch_stats_exit;
1476 }
1477
1478 resp = (struct oct_nic_stats_resp *)sc->virtrptr;
1479 memset(resp, 0, sizeof(struct oct_nic_stats_resp));
1480
1481 init_completion(&sc->complete);
1482 sc->sc_status = OCTEON_REQUEST_PENDING;
1483
1484 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1485
1486 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1487 OPCODE_NIC_PORT_STATS, 0, 0, 0);
1488
1489 retval = octeon_send_soft_command(oct_dev, sc);
1490 if (retval == IQ_SEND_FAILED) {
1491 octeon_free_soft_command(oct_dev, sc);
1492 goto lio_fetch_stats_exit;
1493 }
1494
1495 retval = wait_for_sc_completion_timeout(oct_dev, sc,
1496 (2 * LIO_SC_MAX_TMO_MS));
1497 if (retval) {
1498 dev_err(&oct_dev->pci_dev->dev, "sc OPCODE_NIC_PORT_STATS command failed\n");
1499 goto lio_fetch_stats_exit;
1500 }
1501
1502 octnet_nic_stats_callback(oct_dev, sc->sc_status, sc);
1503 WRITE_ONCE(sc->caller_is_done, true);
1504
1505lio_fetch_stats_exit:
1506 time_in_jiffies = msecs_to_jiffies(LIQUIDIO_NDEV_STATS_POLL_TIME_MS);
1507 if (ifstate_check(lio, LIO_IFSTATE_RUNNING))
1508 schedule_delayed_work(&lio->stats_wk.work, time_in_jiffies);
1509
1510 return;
1511}
1512
1513int liquidio_set_speed(struct lio *lio, int speed)
1514{
1515 struct octeon_device *oct = lio->oct_dev;
1516 struct oct_nic_seapi_resp *resp;
1517 struct octeon_soft_command *sc;
1518 union octnet_cmd *ncmd;
1519 int retval;
1520 u32 var;
1521
1522 if (oct->speed_setting == speed)
1523 return 0;
1524
1525 if (!OCTEON_CN23XX_PF(oct)) {
1526 dev_err(&oct->pci_dev->dev, "%s: SET SPEED only for PF\n",
1527 __func__);
1528 return -EOPNOTSUPP;
1529 }
1530
1531 sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1532 sizeof(struct oct_nic_seapi_resp),
1533 0);
1534 if (!sc)
1535 return -ENOMEM;
1536
1537 ncmd = sc->virtdptr;
1538 resp = sc->virtrptr;
1539 memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1540
1541 init_completion(&sc->complete);
1542 sc->sc_status = OCTEON_REQUEST_PENDING;
1543
1544 ncmd->u64 = 0;
1545 ncmd->s.cmd = SEAPI_CMD_SPEED_SET;
1546 ncmd->s.param1 = speed;
1547
1548 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1549
1550 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1551
1552 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1553 OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1554
1555 retval = octeon_send_soft_command(oct, sc);
1556 if (retval == IQ_SEND_FAILED) {
1557 dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1558 octeon_free_soft_command(oct, sc);
1559 retval = -EBUSY;
1560 } else {
1561
1562 retval = wait_for_sc_completion_timeout(oct, sc, 0);
1563 if (retval)
1564 return retval;
1565
1566 retval = resp->status;
1567
1568 if (retval) {
1569 dev_err(&oct->pci_dev->dev, "%s failed, retval=%d\n",
1570 __func__, retval);
1571 WRITE_ONCE(sc->caller_is_done, true);
1572
1573 return -EIO;
1574 }
1575
1576 var = be32_to_cpu((__force __be32)resp->speed);
1577 if (var != speed) {
1578 dev_err(&oct->pci_dev->dev,
1579 "%s: setting failed speed= %x, expect %x\n",
1580 __func__, var, speed);
1581 }
1582
1583 oct->speed_setting = var;
1584 WRITE_ONCE(sc->caller_is_done, true);
1585 }
1586
1587 return retval;
1588}
1589
1590int liquidio_get_speed(struct lio *lio)
1591{
1592 struct octeon_device *oct = lio->oct_dev;
1593 struct oct_nic_seapi_resp *resp;
1594 struct octeon_soft_command *sc;
1595 union octnet_cmd *ncmd;
1596 int retval;
1597
1598 sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1599 sizeof(struct oct_nic_seapi_resp),
1600 0);
1601 if (!sc)
1602 return -ENOMEM;
1603
1604 ncmd = sc->virtdptr;
1605 resp = sc->virtrptr;
1606 memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1607
1608 init_completion(&sc->complete);
1609 sc->sc_status = OCTEON_REQUEST_PENDING;
1610
1611 ncmd->u64 = 0;
1612 ncmd->s.cmd = SEAPI_CMD_SPEED_GET;
1613
1614 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1615
1616 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1617
1618 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1619 OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1620
1621 retval = octeon_send_soft_command(oct, sc);
1622 if (retval == IQ_SEND_FAILED) {
1623 dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1624 octeon_free_soft_command(oct, sc);
1625 retval = -EIO;
1626 } else {
1627 retval = wait_for_sc_completion_timeout(oct, sc, 0);
1628 if (retval)
1629 return retval;
1630
1631 retval = resp->status;
1632 if (retval) {
1633 dev_err(&oct->pci_dev->dev,
1634 "%s failed retval=%d\n", __func__, retval);
1635 retval = -EIO;
1636 } else {
1637 u32 var;
1638
1639 var = be32_to_cpu((__force __be32)resp->speed);
1640 oct->speed_setting = var;
1641 if (var == 0xffff) {
1642
1643
1644
1645 if (oct->subsystem_id ==
1646 OCTEON_CN2350_25GB_SUBSYS_ID ||
1647 oct->subsystem_id ==
1648 OCTEON_CN2360_25GB_SUBSYS_ID) {
1649 oct->no_speed_setting = 1;
1650 oct->speed_setting = 25;
1651 } else {
1652 oct->speed_setting = 10;
1653 }
1654 }
1655
1656 }
1657 WRITE_ONCE(sc->caller_is_done, true);
1658 }
1659
1660 return retval;
1661}
1662
1663int liquidio_set_fec(struct lio *lio, int on_off)
1664{
1665 struct oct_nic_seapi_resp *resp;
1666 struct octeon_soft_command *sc;
1667 struct octeon_device *oct;
1668 union octnet_cmd *ncmd;
1669 int retval;
1670 u32 var;
1671
1672 oct = lio->oct_dev;
1673
1674 if (oct->props[lio->ifidx].fec == on_off)
1675 return 0;
1676
1677 if (!OCTEON_CN23XX_PF(oct)) {
1678 dev_err(&oct->pci_dev->dev, "%s: SET FEC only for PF\n",
1679 __func__);
1680 return -1;
1681 }
1682
1683 if (oct->speed_boot != 25) {
1684 dev_err(&oct->pci_dev->dev,
1685 "Set FEC only when link speed is 25G during insmod\n");
1686 return -1;
1687 }
1688
1689 sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1690 sizeof(struct oct_nic_seapi_resp), 0);
1691 if (!sc) {
1692 dev_err(&oct->pci_dev->dev,
1693 "Failed to allocate soft command\n");
1694 return -ENOMEM;
1695 }
1696
1697 ncmd = sc->virtdptr;
1698 resp = sc->virtrptr;
1699 memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1700
1701 init_completion(&sc->complete);
1702 sc->sc_status = OCTEON_REQUEST_PENDING;
1703
1704 ncmd->u64 = 0;
1705 ncmd->s.cmd = SEAPI_CMD_FEC_SET;
1706 ncmd->s.param1 = on_off;
1707
1708
1709 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1710
1711 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1712
1713 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1714 OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1715
1716 retval = octeon_send_soft_command(oct, sc);
1717 if (retval == IQ_SEND_FAILED) {
1718 dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1719 octeon_free_soft_command(oct, sc);
1720 return -EIO;
1721 }
1722
1723 retval = wait_for_sc_completion_timeout(oct, sc, 0);
1724 if (retval)
1725 return (-EIO);
1726
1727 var = be32_to_cpu(resp->fec_setting);
1728 resp->fec_setting = var;
1729 if (var != on_off) {
1730 dev_err(&oct->pci_dev->dev,
1731 "Setting failed fec= %x, expect %x\n",
1732 var, on_off);
1733 oct->props[lio->ifidx].fec = var;
1734 if (resp->fec_setting == SEAPI_CMD_FEC_SET_RS)
1735 oct->props[lio->ifidx].fec = 1;
1736 else
1737 oct->props[lio->ifidx].fec = 0;
1738 }
1739
1740 WRITE_ONCE(sc->caller_is_done, true);
1741
1742 if (oct->props[lio->ifidx].fec !=
1743 oct->props[lio->ifidx].fec_boot) {
1744 dev_dbg(&oct->pci_dev->dev,
1745 "Reload driver to change fec to %s\n",
1746 oct->props[lio->ifidx].fec ? "on" : "off");
1747 }
1748
1749 return retval;
1750}
1751
1752int liquidio_get_fec(struct lio *lio)
1753{
1754 struct oct_nic_seapi_resp *resp;
1755 struct octeon_soft_command *sc;
1756 struct octeon_device *oct;
1757 union octnet_cmd *ncmd;
1758 int retval;
1759 u32 var;
1760
1761 oct = lio->oct_dev;
1762
1763 sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1764 sizeof(struct oct_nic_seapi_resp), 0);
1765 if (!sc)
1766 return -ENOMEM;
1767
1768 ncmd = sc->virtdptr;
1769 resp = sc->virtrptr;
1770 memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1771
1772 init_completion(&sc->complete);
1773 sc->sc_status = OCTEON_REQUEST_PENDING;
1774
1775 ncmd->u64 = 0;
1776 ncmd->s.cmd = SEAPI_CMD_FEC_GET;
1777
1778 octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1779
1780 sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1781
1782 octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1783 OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1784
1785 retval = octeon_send_soft_command(oct, sc);
1786 if (retval == IQ_SEND_FAILED) {
1787 dev_info(&oct->pci_dev->dev,
1788 "%s: Failed to send soft command\n", __func__);
1789 octeon_free_soft_command(oct, sc);
1790 return -EIO;
1791 }
1792
1793 retval = wait_for_sc_completion_timeout(oct, sc, 0);
1794 if (retval)
1795 return retval;
1796
1797 var = be32_to_cpu(resp->fec_setting);
1798 resp->fec_setting = var;
1799 if (resp->fec_setting == SEAPI_CMD_FEC_SET_RS)
1800 oct->props[lio->ifidx].fec = 1;
1801 else
1802 oct->props[lio->ifidx].fec = 0;
1803
1804 WRITE_ONCE(sc->caller_is_done, true);
1805
1806 if (oct->props[lio->ifidx].fec !=
1807 oct->props[lio->ifidx].fec_boot) {
1808 dev_dbg(&oct->pci_dev->dev,
1809 "Reload driver to change fec to %s\n",
1810 oct->props[lio->ifidx].fec ? "on" : "off");
1811 }
1812
1813 return retval;
1814}
1815
