1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61#define DEBUG
62
63#include <linux/kernel.h>
64#include <linux/string.h>
65#include <linux/errno.h>
66#include <linux/unistd.h>
67#include <linux/slab.h>
68#include <linux/interrupt.h>
69#include <linux/delay.h>
70#include <linux/netdevice.h>
71#include <linux/etherdevice.h>
72#include <linux/skbuff.h>
73#include <linux/if_vlan.h>
74#include <linux/spinlock.h>
75#include <linux/mm.h>
76#include <linux/of_address.h>
77#include <linux/of_irq.h>
78#include <linux/of_mdio.h>
79#include <linux/of_platform.h>
80#include <linux/ip.h>
81#include <linux/tcp.h>
82#include <linux/udp.h>
83#include <linux/in.h>
84#include <linux/net_tstamp.h>
85
86#include <asm/io.h>
87#ifdef CONFIG_PPC
88#include <asm/reg.h>
89#include <asm/mpc85xx.h>
90#endif
91#include <asm/irq.h>
92#include <linux/uaccess.h>
93#include <linux/module.h>
94#include <linux/dma-mapping.h>
95#include <linux/crc32.h>
96#include <linux/mii.h>
97#include <linux/phy.h>
98#include <linux/phy_fixed.h>
99#include <linux/of.h>
100#include <linux/of_net.h>
101
102#include "gianfar.h"
103
104#define TX_TIMEOUT (5*HZ)
105
106MODULE_AUTHOR("Freescale Semiconductor, Inc");
107MODULE_DESCRIPTION("Gianfar Ethernet Driver");
108MODULE_LICENSE("GPL");
109
110static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
111 dma_addr_t buf)
112{
113 u32 lstatus;
114
115 bdp->bufPtr = cpu_to_be32(buf);
116
117 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
118 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
119 lstatus |= BD_LFLAG(RXBD_WRAP);
120
121 gfar_wmb();
122
123 bdp->lstatus = cpu_to_be32(lstatus);
124}
125
126static void gfar_init_tx_rx_base(struct gfar_private *priv)
127{
128 struct gfar __iomem *regs = priv->gfargrp[0].regs;
129 u32 __iomem *baddr;
130 int i;
131
132 baddr = ®s->tbase0;
133 for (i = 0; i < priv->num_tx_queues; i++) {
134 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
135 baddr += 2;
136 }
137
138 baddr = ®s->rbase0;
139 for (i = 0; i < priv->num_rx_queues; i++) {
140 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
141 baddr += 2;
142 }
143}
144
145static void gfar_init_rqprm(struct gfar_private *priv)
146{
147 struct gfar __iomem *regs = priv->gfargrp[0].regs;
148 u32 __iomem *baddr;
149 int i;
150
151 baddr = ®s->rqprm0;
152 for (i = 0; i < priv->num_rx_queues; i++) {
153 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
154 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
155 baddr++;
156 }
157}
158
159static void gfar_rx_offload_en(struct gfar_private *priv)
160{
161
162 priv->uses_rxfcb = 0;
163
164 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
165 priv->uses_rxfcb = 1;
166
167 if (priv->hwts_rx_en || priv->rx_filer_enable)
168 priv->uses_rxfcb = 1;
169}
170
171static void gfar_mac_rx_config(struct gfar_private *priv)
172{
173 struct gfar __iomem *regs = priv->gfargrp[0].regs;
174 u32 rctrl = 0;
175
176 if (priv->rx_filer_enable) {
177 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
178
179 if (priv->poll_mode == GFAR_SQ_POLLING)
180 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
181 else
182 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
183 }
184
185
186 if (priv->ndev->flags & IFF_PROMISC)
187 rctrl |= RCTRL_PROM;
188
189 if (priv->ndev->features & NETIF_F_RXCSUM)
190 rctrl |= RCTRL_CHECKSUMMING;
191
192 if (priv->extended_hash)
193 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
194
195 if (priv->padding) {
196 rctrl &= ~RCTRL_PAL_MASK;
197 rctrl |= RCTRL_PADDING(priv->padding);
198 }
199
200
201 if (priv->hwts_rx_en)
202 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
203
204 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
205 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
206
207
208 gfar_write(®s->rctrl, rctrl);
209
210 gfar_init_rqprm(priv);
211 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
212 rctrl |= RCTRL_LFC;
213
214
215 gfar_write(®s->rctrl, rctrl);
216}
217
218static void gfar_mac_tx_config(struct gfar_private *priv)
219{
220 struct gfar __iomem *regs = priv->gfargrp[0].regs;
221 u32 tctrl = 0;
222
223 if (priv->ndev->features & NETIF_F_IP_CSUM)
224 tctrl |= TCTRL_INIT_CSUM;
225
226 if (priv->prio_sched_en)
227 tctrl |= TCTRL_TXSCHED_PRIO;
228 else {
229 tctrl |= TCTRL_TXSCHED_WRRS;
230 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
231 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
232 }
233
234 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
235 tctrl |= TCTRL_VLINS;
236
237 gfar_write(®s->tctrl, tctrl);
238}
239
240static void gfar_configure_coalescing(struct gfar_private *priv,
241 unsigned long tx_mask, unsigned long rx_mask)
242{
243 struct gfar __iomem *regs = priv->gfargrp[0].regs;
244 u32 __iomem *baddr;
245
246 if (priv->mode == MQ_MG_MODE) {
247 int i = 0;
248
249 baddr = ®s->txic0;
250 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
251 gfar_write(baddr + i, 0);
252 if (likely(priv->tx_queue[i]->txcoalescing))
253 gfar_write(baddr + i, priv->tx_queue[i]->txic);
254 }
255
256 baddr = ®s->rxic0;
257 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
258 gfar_write(baddr + i, 0);
259 if (likely(priv->rx_queue[i]->rxcoalescing))
260 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
261 }
262 } else {
263
264
265
266 gfar_write(®s->txic, 0);
267 if (likely(priv->tx_queue[0]->txcoalescing))
268 gfar_write(®s->txic, priv->tx_queue[0]->txic);
269
270 gfar_write(®s->rxic, 0);
271 if (unlikely(priv->rx_queue[0]->rxcoalescing))
272 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
273 }
274}
275
276static void gfar_configure_coalescing_all(struct gfar_private *priv)
277{
278 gfar_configure_coalescing(priv, 0xFF, 0xFF);
279}
280
281static struct net_device_stats *gfar_get_stats(struct net_device *dev)
282{
283 struct gfar_private *priv = netdev_priv(dev);
284 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
285 unsigned long tx_packets = 0, tx_bytes = 0;
286 int i;
287
288 for (i = 0; i < priv->num_rx_queues; i++) {
289 rx_packets += priv->rx_queue[i]->stats.rx_packets;
290 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
291 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
292 }
293
294 dev->stats.rx_packets = rx_packets;
295 dev->stats.rx_bytes = rx_bytes;
296 dev->stats.rx_dropped = rx_dropped;
297
298 for (i = 0; i < priv->num_tx_queues; i++) {
299 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
300 tx_packets += priv->tx_queue[i]->stats.tx_packets;
301 }
302
303 dev->stats.tx_bytes = tx_bytes;
304 dev->stats.tx_packets = tx_packets;
305
306 return &dev->stats;
307}
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
324{
325 u32 tempval;
326 struct gfar_private *priv = netdev_priv(dev);
327 u32 result = ether_crc(ETH_ALEN, addr);
328 int width = priv->hash_width;
329 u8 whichbit = (result >> (32 - width)) & 0x1f;
330 u8 whichreg = result >> (32 - width + 5);
331 u32 value = (1 << (31-whichbit));
332
333 tempval = gfar_read(priv->hash_regs[whichreg]);
334 tempval |= value;
335 gfar_write(priv->hash_regs[whichreg], tempval);
336}
337
338
339
340
341static void gfar_set_mac_for_addr(struct net_device *dev, int num,
342 const u8 *addr)
343{
344 struct gfar_private *priv = netdev_priv(dev);
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 u32 tempval;
347 u32 __iomem *macptr = ®s->macstnaddr1;
348
349 macptr += num*2;
350
351
352
353
354
355 tempval = (addr[5] << 24) | (addr[4] << 16) |
356 (addr[3] << 8) | addr[2];
357
358 gfar_write(macptr, tempval);
359
360 tempval = (addr[1] << 24) | (addr[0] << 16);
361
362 gfar_write(macptr+1, tempval);
363}
364
365static int gfar_set_mac_addr(struct net_device *dev, void *p)
366{
367 eth_mac_addr(dev, p);
368
369 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
370
371 return 0;
372}
373
374static void gfar_ints_disable(struct gfar_private *priv)
375{
376 int i;
377 for (i = 0; i < priv->num_grps; i++) {
378 struct gfar __iomem *regs = priv->gfargrp[i].regs;
379
380 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
381
382
383 gfar_write(®s->imask, IMASK_INIT_CLEAR);
384 }
385}
386
387static void gfar_ints_enable(struct gfar_private *priv)
388{
389 int i;
390 for (i = 0; i < priv->num_grps; i++) {
391 struct gfar __iomem *regs = priv->gfargrp[i].regs;
392
393 gfar_write(®s->imask, IMASK_DEFAULT);
394 }
395}
396
397static int gfar_alloc_tx_queues(struct gfar_private *priv)
398{
399 int i;
400
401 for (i = 0; i < priv->num_tx_queues; i++) {
402 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
403 GFP_KERNEL);
404 if (!priv->tx_queue[i])
405 return -ENOMEM;
406
407 priv->tx_queue[i]->tx_skbuff = NULL;
408 priv->tx_queue[i]->qindex = i;
409 priv->tx_queue[i]->dev = priv->ndev;
410 spin_lock_init(&(priv->tx_queue[i]->txlock));
411 }
412 return 0;
413}
414
415static int gfar_alloc_rx_queues(struct gfar_private *priv)
416{
417 int i;
418
419 for (i = 0; i < priv->num_rx_queues; i++) {
420 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
421 GFP_KERNEL);
422 if (!priv->rx_queue[i])
423 return -ENOMEM;
424
425 priv->rx_queue[i]->qindex = i;
426 priv->rx_queue[i]->ndev = priv->ndev;
427 }
428 return 0;
429}
430
431static void gfar_free_tx_queues(struct gfar_private *priv)
432{
433 int i;
434
435 for (i = 0; i < priv->num_tx_queues; i++)
436 kfree(priv->tx_queue[i]);
437}
438
439static void gfar_free_rx_queues(struct gfar_private *priv)
440{
441 int i;
442
443 for (i = 0; i < priv->num_rx_queues; i++)
444 kfree(priv->rx_queue[i]);
445}
446
447static void unmap_group_regs(struct gfar_private *priv)
448{
449 int i;
450
451 for (i = 0; i < MAXGROUPS; i++)
452 if (priv->gfargrp[i].regs)
453 iounmap(priv->gfargrp[i].regs);
454}
455
456static void free_gfar_dev(struct gfar_private *priv)
457{
458 int i, j;
459
460 for (i = 0; i < priv->num_grps; i++)
461 for (j = 0; j < GFAR_NUM_IRQS; j++) {
462 kfree(priv->gfargrp[i].irqinfo[j]);
463 priv->gfargrp[i].irqinfo[j] = NULL;
464 }
465
466 free_netdev(priv->ndev);
467}
468
469static void disable_napi(struct gfar_private *priv)
470{
471 int i;
472
473 for (i = 0; i < priv->num_grps; i++) {
474 napi_disable(&priv->gfargrp[i].napi_rx);
475 napi_disable(&priv->gfargrp[i].napi_tx);
476 }
477}
478
479static void enable_napi(struct gfar_private *priv)
480{
481 int i;
482
483 for (i = 0; i < priv->num_grps; i++) {
484 napi_enable(&priv->gfargrp[i].napi_rx);
485 napi_enable(&priv->gfargrp[i].napi_tx);
486 }
487}
488
489static int gfar_parse_group(struct device_node *np,
490 struct gfar_private *priv, const char *model)
491{
492 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
493 int i;
494
495 for (i = 0; i < GFAR_NUM_IRQS; i++) {
496 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
497 GFP_KERNEL);
498 if (!grp->irqinfo[i])
499 return -ENOMEM;
500 }
501
502 grp->regs = of_iomap(np, 0);
503 if (!grp->regs)
504 return -ENOMEM;
505
506 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
507
508
509 if (model && strcasecmp(model, "FEC")) {
510 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
511 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
512 if (!gfar_irq(grp, TX)->irq ||
513 !gfar_irq(grp, RX)->irq ||
514 !gfar_irq(grp, ER)->irq)
515 return -EINVAL;
516 }
517
518 grp->priv = priv;
519 spin_lock_init(&grp->grplock);
520 if (priv->mode == MQ_MG_MODE) {
521 u32 rxq_mask, txq_mask;
522 int ret;
523
524 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
525 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
526
527 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
528 if (!ret) {
529 grp->rx_bit_map = rxq_mask ?
530 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
531 }
532
533 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
534 if (!ret) {
535 grp->tx_bit_map = txq_mask ?
536 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
537 }
538
539 if (priv->poll_mode == GFAR_SQ_POLLING) {
540
541 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
542 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
543 }
544 } else {
545 grp->rx_bit_map = 0xFF;
546 grp->tx_bit_map = 0xFF;
547 }
548
549
550
551
552 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
553 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
554
555
556
557
558 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
559 if (!grp->rx_queue)
560 grp->rx_queue = priv->rx_queue[i];
561 grp->num_rx_queues++;
562 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
563 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
564 priv->rx_queue[i]->grp = grp;
565 }
566
567 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
568 if (!grp->tx_queue)
569 grp->tx_queue = priv->tx_queue[i];
570 grp->num_tx_queues++;
571 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
572 priv->tqueue |= (TQUEUE_EN0 >> i);
573 priv->tx_queue[i]->grp = grp;
574 }
575
576 priv->num_grps++;
577
578 return 0;
579}
580
581static int gfar_of_group_count(struct device_node *np)
582{
583 struct device_node *child;
584 int num = 0;
585
586 for_each_available_child_of_node(np, child)
587 if (of_node_name_eq(child, "queue-group"))
588 num++;
589
590 return num;
591}
592
593
594
595
596static phy_interface_t gfar_get_interface(struct net_device *dev)
597{
598 struct gfar_private *priv = netdev_priv(dev);
599 struct gfar __iomem *regs = priv->gfargrp[0].regs;
600 u32 ecntrl;
601
602 ecntrl = gfar_read(®s->ecntrl);
603
604 if (ecntrl & ECNTRL_SGMII_MODE)
605 return PHY_INTERFACE_MODE_SGMII;
606
607 if (ecntrl & ECNTRL_TBI_MODE) {
608 if (ecntrl & ECNTRL_REDUCED_MODE)
609 return PHY_INTERFACE_MODE_RTBI;
610 else
611 return PHY_INTERFACE_MODE_TBI;
612 }
613
614 if (ecntrl & ECNTRL_REDUCED_MODE) {
615 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
616 return PHY_INTERFACE_MODE_RMII;
617 }
618 else {
619 phy_interface_t interface = priv->interface;
620
621
622
623
624 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
625 return PHY_INTERFACE_MODE_RGMII_ID;
626
627 return PHY_INTERFACE_MODE_RGMII;
628 }
629 }
630
631 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
632 return PHY_INTERFACE_MODE_GMII;
633
634 return PHY_INTERFACE_MODE_MII;
635}
636
637static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
638{
639 const char *model;
640 const void *mac_addr;
641 int err = 0, i;
642 phy_interface_t interface;
643 struct net_device *dev = NULL;
644 struct gfar_private *priv = NULL;
645 struct device_node *np = ofdev->dev.of_node;
646 struct device_node *child = NULL;
647 u32 stash_len = 0;
648 u32 stash_idx = 0;
649 unsigned int num_tx_qs, num_rx_qs;
650 unsigned short mode, poll_mode;
651
652 if (!np)
653 return -ENODEV;
654
655 if (of_device_is_compatible(np, "fsl,etsec2")) {
656 mode = MQ_MG_MODE;
657 poll_mode = GFAR_SQ_POLLING;
658 } else {
659 mode = SQ_SG_MODE;
660 poll_mode = GFAR_SQ_POLLING;
661 }
662
663 if (mode == SQ_SG_MODE) {
664 num_tx_qs = 1;
665 num_rx_qs = 1;
666 } else {
667
668 unsigned int num_grps = gfar_of_group_count(np);
669
670 if (num_grps == 0 || num_grps > MAXGROUPS) {
671 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
672 num_grps);
673 pr_err("Cannot do alloc_etherdev, aborting\n");
674 return -EINVAL;
675 }
676
677 if (poll_mode == GFAR_SQ_POLLING) {
678 num_tx_qs = num_grps;
679 num_rx_qs = num_grps;
680 } else {
681 u32 tx_queues, rx_queues;
682 int ret;
683
684
685 ret = of_property_read_u32(np, "fsl,num_tx_queues",
686 &tx_queues);
687 num_tx_qs = ret ? 1 : tx_queues;
688
689 ret = of_property_read_u32(np, "fsl,num_rx_queues",
690 &rx_queues);
691 num_rx_qs = ret ? 1 : rx_queues;
692 }
693 }
694
695 if (num_tx_qs > MAX_TX_QS) {
696 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
697 num_tx_qs, MAX_TX_QS);
698 pr_err("Cannot do alloc_etherdev, aborting\n");
699 return -EINVAL;
700 }
701
702 if (num_rx_qs > MAX_RX_QS) {
703 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
704 num_rx_qs, MAX_RX_QS);
705 pr_err("Cannot do alloc_etherdev, aborting\n");
706 return -EINVAL;
707 }
708
709 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
710 dev = *pdev;
711 if (NULL == dev)
712 return -ENOMEM;
713
714 priv = netdev_priv(dev);
715 priv->ndev = dev;
716
717 priv->mode = mode;
718 priv->poll_mode = poll_mode;
719
720 priv->num_tx_queues = num_tx_qs;
721 netif_set_real_num_rx_queues(dev, num_rx_qs);
722 priv->num_rx_queues = num_rx_qs;
723
724 err = gfar_alloc_tx_queues(priv);
725 if (err)
726 goto tx_alloc_failed;
727
728 err = gfar_alloc_rx_queues(priv);
729 if (err)
730 goto rx_alloc_failed;
731
732 err = of_property_read_string(np, "model", &model);
733 if (err) {
734 pr_err("Device model property missing, aborting\n");
735 goto rx_alloc_failed;
736 }
737
738
739 INIT_LIST_HEAD(&priv->rx_list.list);
740 priv->rx_list.count = 0;
741 mutex_init(&priv->rx_queue_access);
742
743 for (i = 0; i < MAXGROUPS; i++)
744 priv->gfargrp[i].regs = NULL;
745
746
747 if (priv->mode == MQ_MG_MODE) {
748 for_each_available_child_of_node(np, child) {
749 if (!of_node_name_eq(child, "queue-group"))
750 continue;
751
752 err = gfar_parse_group(child, priv, model);
753 if (err) {
754 of_node_put(child);
755 goto err_grp_init;
756 }
757 }
758 } else {
759 err = gfar_parse_group(np, priv, model);
760 if (err)
761 goto err_grp_init;
762 }
763
764 if (of_property_read_bool(np, "bd-stash")) {
765 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
766 priv->bd_stash_en = 1;
767 }
768
769 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
770
771 if (err == 0)
772 priv->rx_stash_size = stash_len;
773
774 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
775
776 if (err == 0)
777 priv->rx_stash_index = stash_idx;
778
779 if (stash_len || stash_idx)
780 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
781
782 mac_addr = of_get_mac_address(np);
783
784 if (!IS_ERR(mac_addr)) {
785 ether_addr_copy(dev->dev_addr, mac_addr);
786 } else {
787 eth_hw_addr_random(dev);
788 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
789 }
790
791 if (model && !strcasecmp(model, "TSEC"))
792 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
793 FSL_GIANFAR_DEV_HAS_COALESCE |
794 FSL_GIANFAR_DEV_HAS_RMON |
795 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
796
797 if (model && !strcasecmp(model, "eTSEC"))
798 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
799 FSL_GIANFAR_DEV_HAS_COALESCE |
800 FSL_GIANFAR_DEV_HAS_RMON |
801 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
802 FSL_GIANFAR_DEV_HAS_CSUM |
803 FSL_GIANFAR_DEV_HAS_VLAN |
804 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
805 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
806 FSL_GIANFAR_DEV_HAS_TIMER |
807 FSL_GIANFAR_DEV_HAS_RX_FILER;
808
809
810
811
812
813 err = of_get_phy_mode(np, &interface);
814 if (!err)
815 priv->interface = interface;
816 else
817 priv->interface = gfar_get_interface(dev);
818
819 if (of_find_property(np, "fsl,magic-packet", NULL))
820 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
821
822 if (of_get_property(np, "fsl,wake-on-filer", NULL))
823 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
824
825 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
826
827
828
829
830 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
831 err = of_phy_register_fixed_link(np);
832 if (err)
833 goto err_grp_init;
834
835 priv->phy_node = of_node_get(np);
836 }
837
838
839 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
840
841 return 0;
842
843err_grp_init:
844 unmap_group_regs(priv);
845rx_alloc_failed:
846 gfar_free_rx_queues(priv);
847tx_alloc_failed:
848 gfar_free_tx_queues(priv);
849 free_gfar_dev(priv);
850 return err;
851}
852
853static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
854 u32 class)
855{
856 u32 rqfpr = FPR_FILER_MASK;
857 u32 rqfcr = 0x0;
858
859 rqfar--;
860 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
861 priv->ftp_rqfpr[rqfar] = rqfpr;
862 priv->ftp_rqfcr[rqfar] = rqfcr;
863 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
864
865 rqfar--;
866 rqfcr = RQFCR_CMP_NOMATCH;
867 priv->ftp_rqfpr[rqfar] = rqfpr;
868 priv->ftp_rqfcr[rqfar] = rqfcr;
869 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
870
871 rqfar--;
872 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
873 rqfpr = class;
874 priv->ftp_rqfcr[rqfar] = rqfcr;
875 priv->ftp_rqfpr[rqfar] = rqfpr;
876 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
877
878 rqfar--;
879 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
880 rqfpr = class;
881 priv->ftp_rqfcr[rqfar] = rqfcr;
882 priv->ftp_rqfpr[rqfar] = rqfpr;
883 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
884
885 return rqfar;
886}
887
888static void gfar_init_filer_table(struct gfar_private *priv)
889{
890 int i = 0x0;
891 u32 rqfar = MAX_FILER_IDX;
892 u32 rqfcr = 0x0;
893 u32 rqfpr = FPR_FILER_MASK;
894
895
896 rqfcr = RQFCR_CMP_MATCH;
897 priv->ftp_rqfcr[rqfar] = rqfcr;
898 priv->ftp_rqfpr[rqfar] = rqfpr;
899 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
900
901 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
902 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
903 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
904 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
905 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
906 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
907
908
909 priv->cur_filer_idx = rqfar;
910
911
912 rqfcr = RQFCR_CMP_NOMATCH;
913 for (i = 0; i < rqfar; i++) {
914 priv->ftp_rqfcr[i] = rqfcr;
915 priv->ftp_rqfpr[i] = rqfpr;
916 gfar_write_filer(priv, i, rqfcr, rqfpr);
917 }
918}
919
920#ifdef CONFIG_PPC
921static void __gfar_detect_errata_83xx(struct gfar_private *priv)
922{
923 unsigned int pvr = mfspr(SPRN_PVR);
924 unsigned int svr = mfspr(SPRN_SVR);
925 unsigned int mod = (svr >> 16) & 0xfff6;
926 unsigned int rev = svr & 0xffff;
927
928
929 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
930 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
931 priv->errata |= GFAR_ERRATA_74;
932
933
934 if ((pvr == 0x80850010 && mod == 0x80b0) ||
935 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
936 priv->errata |= GFAR_ERRATA_76;
937
938
939 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
940 priv->errata |= GFAR_ERRATA_12;
941}
942
943static void __gfar_detect_errata_85xx(struct gfar_private *priv)
944{
945 unsigned int svr = mfspr(SPRN_SVR);
946
947 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
948 priv->errata |= GFAR_ERRATA_12;
949
950 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
951 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
952 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
953 priv->errata |= GFAR_ERRATA_76;
954}
955#endif
956
957static void gfar_detect_errata(struct gfar_private *priv)
958{
959 struct device *dev = &priv->ofdev->dev;
960
961
962 priv->errata |= GFAR_ERRATA_A002;
963
964#ifdef CONFIG_PPC
965 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
966 __gfar_detect_errata_85xx(priv);
967 else
968 __gfar_detect_errata_83xx(priv);
969#endif
970
971 if (priv->errata)
972 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
973 priv->errata);
974}
975
976static void gfar_init_addr_hash_table(struct gfar_private *priv)
977{
978 struct gfar __iomem *regs = priv->gfargrp[0].regs;
979
980 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
981 priv->extended_hash = 1;
982 priv->hash_width = 9;
983
984 priv->hash_regs[0] = ®s->igaddr0;
985 priv->hash_regs[1] = ®s->igaddr1;
986 priv->hash_regs[2] = ®s->igaddr2;
987 priv->hash_regs[3] = ®s->igaddr3;
988 priv->hash_regs[4] = ®s->igaddr4;
989 priv->hash_regs[5] = ®s->igaddr5;
990 priv->hash_regs[6] = ®s->igaddr6;
991 priv->hash_regs[7] = ®s->igaddr7;
992 priv->hash_regs[8] = ®s->gaddr0;
993 priv->hash_regs[9] = ®s->gaddr1;
994 priv->hash_regs[10] = ®s->gaddr2;
995 priv->hash_regs[11] = ®s->gaddr3;
996 priv->hash_regs[12] = ®s->gaddr4;
997 priv->hash_regs[13] = ®s->gaddr5;
998 priv->hash_regs[14] = ®s->gaddr6;
999 priv->hash_regs[15] = ®s->gaddr7;
1000
1001 } else {
1002 priv->extended_hash = 0;
1003 priv->hash_width = 8;
1004
1005 priv->hash_regs[0] = ®s->gaddr0;
1006 priv->hash_regs[1] = ®s->gaddr1;
1007 priv->hash_regs[2] = ®s->gaddr2;
1008 priv->hash_regs[3] = ®s->gaddr3;
1009 priv->hash_regs[4] = ®s->gaddr4;
1010 priv->hash_regs[5] = ®s->gaddr5;
1011 priv->hash_regs[6] = ®s->gaddr6;
1012 priv->hash_regs[7] = ®s->gaddr7;
1013 }
1014}
1015
1016static int __gfar_is_rx_idle(struct gfar_private *priv)
1017{
1018 u32 res;
1019
1020
1021
1022
1023 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1024 return 0;
1025
1026
1027
1028
1029
1030 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1031 res &= 0x7f807f80;
1032 if ((res & 0xffff) == (res >> 16))
1033 return 1;
1034
1035 return 0;
1036}
1037
1038
1039static void gfar_halt_nodisable(struct gfar_private *priv)
1040{
1041 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1042 u32 tempval;
1043 unsigned int timeout;
1044 int stopped;
1045
1046 gfar_ints_disable(priv);
1047
1048 if (gfar_is_dma_stopped(priv))
1049 return;
1050
1051
1052 tempval = gfar_read(®s->dmactrl);
1053 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1054 gfar_write(®s->dmactrl, tempval);
1055
1056retry:
1057 timeout = 1000;
1058 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1059 cpu_relax();
1060 timeout--;
1061 }
1062
1063 if (!timeout)
1064 stopped = gfar_is_dma_stopped(priv);
1065
1066 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1067 !__gfar_is_rx_idle(priv))
1068 goto retry;
1069}
1070
1071
1072static void gfar_halt(struct gfar_private *priv)
1073{
1074 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1075 u32 tempval;
1076
1077
1078 gfar_write(®s->rqueue, 0);
1079 gfar_write(®s->tqueue, 0);
1080
1081 mdelay(10);
1082
1083 gfar_halt_nodisable(priv);
1084
1085
1086 tempval = gfar_read(®s->maccfg1);
1087 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1088 gfar_write(®s->maccfg1, tempval);
1089}
1090
1091static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1092{
1093 struct txbd8 *txbdp;
1094 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1095 int i, j;
1096
1097 txbdp = tx_queue->tx_bd_base;
1098
1099 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1100 if (!tx_queue->tx_skbuff[i])
1101 continue;
1102
1103 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1104 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1105 txbdp->lstatus = 0;
1106 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1107 j++) {
1108 txbdp++;
1109 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1110 be16_to_cpu(txbdp->length),
1111 DMA_TO_DEVICE);
1112 }
1113 txbdp++;
1114 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1115 tx_queue->tx_skbuff[i] = NULL;
1116 }
1117 kfree(tx_queue->tx_skbuff);
1118 tx_queue->tx_skbuff = NULL;
1119}
1120
1121static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1122{
1123 int i;
1124
1125 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1126
1127 dev_kfree_skb(rx_queue->skb);
1128
1129 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1130 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1131
1132 rxbdp->lstatus = 0;
1133 rxbdp->bufPtr = 0;
1134 rxbdp++;
1135
1136 if (!rxb->page)
1137 continue;
1138
1139 dma_unmap_page(rx_queue->dev, rxb->dma,
1140 PAGE_SIZE, DMA_FROM_DEVICE);
1141 __free_page(rxb->page);
1142
1143 rxb->page = NULL;
1144 }
1145
1146 kfree(rx_queue->rx_buff);
1147 rx_queue->rx_buff = NULL;
1148}
1149
1150
1151
1152
1153static void free_skb_resources(struct gfar_private *priv)
1154{
1155 struct gfar_priv_tx_q *tx_queue = NULL;
1156 struct gfar_priv_rx_q *rx_queue = NULL;
1157 int i;
1158
1159
1160 for (i = 0; i < priv->num_tx_queues; i++) {
1161 struct netdev_queue *txq;
1162
1163 tx_queue = priv->tx_queue[i];
1164 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1165 if (tx_queue->tx_skbuff)
1166 free_skb_tx_queue(tx_queue);
1167 netdev_tx_reset_queue(txq);
1168 }
1169
1170 for (i = 0; i < priv->num_rx_queues; i++) {
1171 rx_queue = priv->rx_queue[i];
1172 if (rx_queue->rx_buff)
1173 free_skb_rx_queue(rx_queue);
1174 }
1175
1176 dma_free_coherent(priv->dev,
1177 sizeof(struct txbd8) * priv->total_tx_ring_size +
1178 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1179 priv->tx_queue[0]->tx_bd_base,
1180 priv->tx_queue[0]->tx_bd_dma_base);
1181}
1182
1183void stop_gfar(struct net_device *dev)
1184{
1185 struct gfar_private *priv = netdev_priv(dev);
1186
1187 netif_tx_stop_all_queues(dev);
1188
1189 smp_mb__before_atomic();
1190 set_bit(GFAR_DOWN, &priv->state);
1191 smp_mb__after_atomic();
1192
1193 disable_napi(priv);
1194
1195
1196 gfar_halt(priv);
1197
1198 phy_stop(dev->phydev);
1199
1200 free_skb_resources(priv);
1201}
1202
1203static void gfar_start(struct gfar_private *priv)
1204{
1205 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1206 u32 tempval;
1207 int i = 0;
1208
1209
1210 gfar_write(®s->rqueue, priv->rqueue);
1211 gfar_write(®s->tqueue, priv->tqueue);
1212
1213
1214 tempval = gfar_read(®s->dmactrl);
1215 tempval |= DMACTRL_INIT_SETTINGS;
1216 gfar_write(®s->dmactrl, tempval);
1217
1218
1219 tempval = gfar_read(®s->dmactrl);
1220 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1221 gfar_write(®s->dmactrl, tempval);
1222
1223 for (i = 0; i < priv->num_grps; i++) {
1224 regs = priv->gfargrp[i].regs;
1225
1226 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1227 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1228 }
1229
1230
1231 tempval = gfar_read(®s->maccfg1);
1232 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1233 gfar_write(®s->maccfg1, tempval);
1234
1235 gfar_ints_enable(priv);
1236
1237 netif_trans_update(priv->ndev);
1238}
1239
1240static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1241{
1242 struct page *page;
1243 dma_addr_t addr;
1244
1245 page = dev_alloc_page();
1246 if (unlikely(!page))
1247 return false;
1248
1249 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1250 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1251 __free_page(page);
1252
1253 return false;
1254 }
1255
1256 rxb->dma = addr;
1257 rxb->page = page;
1258 rxb->page_offset = 0;
1259
1260 return true;
1261}
1262
1263static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1264{
1265 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1266 struct gfar_extra_stats *estats = &priv->extra_stats;
1267
1268 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1269 atomic64_inc(&estats->rx_alloc_err);
1270}
1271
1272static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1273 int alloc_cnt)
1274{
1275 struct rxbd8 *bdp;
1276 struct gfar_rx_buff *rxb;
1277 int i;
1278
1279 i = rx_queue->next_to_use;
1280 bdp = &rx_queue->rx_bd_base[i];
1281 rxb = &rx_queue->rx_buff[i];
1282
1283 while (alloc_cnt--) {
1284
1285 if (unlikely(!rxb->page)) {
1286 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1287 gfar_rx_alloc_err(rx_queue);
1288 break;
1289 }
1290 }
1291
1292
1293 gfar_init_rxbdp(rx_queue, bdp,
1294 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1295
1296
1297 bdp++;
1298 rxb++;
1299
1300 if (unlikely(++i == rx_queue->rx_ring_size)) {
1301 i = 0;
1302 bdp = rx_queue->rx_bd_base;
1303 rxb = rx_queue->rx_buff;
1304 }
1305 }
1306
1307 rx_queue->next_to_use = i;
1308 rx_queue->next_to_alloc = i;
1309}
1310
1311static void gfar_init_bds(struct net_device *ndev)
1312{
1313 struct gfar_private *priv = netdev_priv(ndev);
1314 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1315 struct gfar_priv_tx_q *tx_queue = NULL;
1316 struct gfar_priv_rx_q *rx_queue = NULL;
1317 struct txbd8 *txbdp;
1318 u32 __iomem *rfbptr;
1319 int i, j;
1320
1321 for (i = 0; i < priv->num_tx_queues; i++) {
1322 tx_queue = priv->tx_queue[i];
1323
1324 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1325 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1326 tx_queue->cur_tx = tx_queue->tx_bd_base;
1327 tx_queue->skb_curtx = 0;
1328 tx_queue->skb_dirtytx = 0;
1329
1330
1331 txbdp = tx_queue->tx_bd_base;
1332 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1333 txbdp->lstatus = 0;
1334 txbdp->bufPtr = 0;
1335 txbdp++;
1336 }
1337
1338
1339 txbdp--;
1340 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1341 TXBD_WRAP);
1342 }
1343
1344 rfbptr = ®s->rfbptr0;
1345 for (i = 0; i < priv->num_rx_queues; i++) {
1346 rx_queue = priv->rx_queue[i];
1347
1348 rx_queue->next_to_clean = 0;
1349 rx_queue->next_to_use = 0;
1350 rx_queue->next_to_alloc = 0;
1351
1352
1353
1354
1355 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1356
1357 rx_queue->rfbptr = rfbptr;
1358 rfbptr += 2;
1359 }
1360}
1361
1362static int gfar_alloc_skb_resources(struct net_device *ndev)
1363{
1364 void *vaddr;
1365 dma_addr_t addr;
1366 int i, j;
1367 struct gfar_private *priv = netdev_priv(ndev);
1368 struct device *dev = priv->dev;
1369 struct gfar_priv_tx_q *tx_queue = NULL;
1370 struct gfar_priv_rx_q *rx_queue = NULL;
1371
1372 priv->total_tx_ring_size = 0;
1373 for (i = 0; i < priv->num_tx_queues; i++)
1374 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1375
1376 priv->total_rx_ring_size = 0;
1377 for (i = 0; i < priv->num_rx_queues; i++)
1378 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1379
1380
1381 vaddr = dma_alloc_coherent(dev,
1382 (priv->total_tx_ring_size *
1383 sizeof(struct txbd8)) +
1384 (priv->total_rx_ring_size *
1385 sizeof(struct rxbd8)),
1386 &addr, GFP_KERNEL);
1387 if (!vaddr)
1388 return -ENOMEM;
1389
1390 for (i = 0; i < priv->num_tx_queues; i++) {
1391 tx_queue = priv->tx_queue[i];
1392 tx_queue->tx_bd_base = vaddr;
1393 tx_queue->tx_bd_dma_base = addr;
1394 tx_queue->dev = ndev;
1395
1396 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1397 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1398 }
1399
1400
1401 for (i = 0; i < priv->num_rx_queues; i++) {
1402 rx_queue = priv->rx_queue[i];
1403 rx_queue->rx_bd_base = vaddr;
1404 rx_queue->rx_bd_dma_base = addr;
1405 rx_queue->ndev = ndev;
1406 rx_queue->dev = dev;
1407 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1408 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1409 }
1410
1411
1412 for (i = 0; i < priv->num_tx_queues; i++) {
1413 tx_queue = priv->tx_queue[i];
1414 tx_queue->tx_skbuff =
1415 kmalloc_array(tx_queue->tx_ring_size,
1416 sizeof(*tx_queue->tx_skbuff),
1417 GFP_KERNEL);
1418 if (!tx_queue->tx_skbuff)
1419 goto cleanup;
1420
1421 for (j = 0; j < tx_queue->tx_ring_size; j++)
1422 tx_queue->tx_skbuff[j] = NULL;
1423 }
1424
1425 for (i = 0; i < priv->num_rx_queues; i++) {
1426 rx_queue = priv->rx_queue[i];
1427 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1428 sizeof(*rx_queue->rx_buff),
1429 GFP_KERNEL);
1430 if (!rx_queue->rx_buff)
1431 goto cleanup;
1432 }
1433
1434 gfar_init_bds(ndev);
1435
1436 return 0;
1437
1438cleanup:
1439 free_skb_resources(priv);
1440 return -ENOMEM;
1441}
1442
1443
1444int startup_gfar(struct net_device *ndev)
1445{
1446 struct gfar_private *priv = netdev_priv(ndev);
1447 int err;
1448
1449 gfar_mac_reset(priv);
1450
1451 err = gfar_alloc_skb_resources(ndev);
1452 if (err)
1453 return err;
1454
1455 gfar_init_tx_rx_base(priv);
1456
1457 smp_mb__before_atomic();
1458 clear_bit(GFAR_DOWN, &priv->state);
1459 smp_mb__after_atomic();
1460
1461
1462 gfar_start(priv);
1463
1464
1465 priv->oldlink = 0;
1466 priv->oldspeed = 0;
1467 priv->oldduplex = -1;
1468
1469 phy_start(ndev->phydev);
1470
1471 enable_napi(priv);
1472
1473 netif_tx_wake_all_queues(ndev);
1474
1475 return 0;
1476}
1477
1478static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1479{
1480 struct net_device *ndev = priv->ndev;
1481 struct phy_device *phydev = ndev->phydev;
1482 u32 val = 0;
1483
1484 if (!phydev->duplex)
1485 return val;
1486
1487 if (!priv->pause_aneg_en) {
1488 if (priv->tx_pause_en)
1489 val |= MACCFG1_TX_FLOW;
1490 if (priv->rx_pause_en)
1491 val |= MACCFG1_RX_FLOW;
1492 } else {
1493 u16 lcl_adv, rmt_adv;
1494 u8 flowctrl;
1495
1496 rmt_adv = 0;
1497 if (phydev->pause)
1498 rmt_adv = LPA_PAUSE_CAP;
1499 if (phydev->asym_pause)
1500 rmt_adv |= LPA_PAUSE_ASYM;
1501
1502 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1503 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1504 if (flowctrl & FLOW_CTRL_TX)
1505 val |= MACCFG1_TX_FLOW;
1506 if (flowctrl & FLOW_CTRL_RX)
1507 val |= MACCFG1_RX_FLOW;
1508 }
1509
1510 return val;
1511}
1512
1513static noinline void gfar_update_link_state(struct gfar_private *priv)
1514{
1515 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1516 struct net_device *ndev = priv->ndev;
1517 struct phy_device *phydev = ndev->phydev;
1518 struct gfar_priv_rx_q *rx_queue = NULL;
1519 int i;
1520
1521 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1522 return;
1523
1524 if (phydev->link) {
1525 u32 tempval1 = gfar_read(®s->maccfg1);
1526 u32 tempval = gfar_read(®s->maccfg2);
1527 u32 ecntrl = gfar_read(®s->ecntrl);
1528 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1529
1530 if (phydev->duplex != priv->oldduplex) {
1531 if (!(phydev->duplex))
1532 tempval &= ~(MACCFG2_FULL_DUPLEX);
1533 else
1534 tempval |= MACCFG2_FULL_DUPLEX;
1535
1536 priv->oldduplex = phydev->duplex;
1537 }
1538
1539 if (phydev->speed != priv->oldspeed) {
1540 switch (phydev->speed) {
1541 case 1000:
1542 tempval =
1543 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1544
1545 ecntrl &= ~(ECNTRL_R100);
1546 break;
1547 case 100:
1548 case 10:
1549 tempval =
1550 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1551
1552
1553
1554
1555 if (phydev->speed == SPEED_100)
1556 ecntrl |= ECNTRL_R100;
1557 else
1558 ecntrl &= ~(ECNTRL_R100);
1559 break;
1560 default:
1561 netif_warn(priv, link, priv->ndev,
1562 "Ack! Speed (%d) is not 10/100/1000!\n",
1563 phydev->speed);
1564 break;
1565 }
1566
1567 priv->oldspeed = phydev->speed;
1568 }
1569
1570 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1571 tempval1 |= gfar_get_flowctrl_cfg(priv);
1572
1573
1574 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1575 for (i = 0; i < priv->num_rx_queues; i++) {
1576 u32 bdp_dma;
1577
1578 rx_queue = priv->rx_queue[i];
1579 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1580 gfar_write(rx_queue->rfbptr, bdp_dma);
1581 }
1582
1583 priv->tx_actual_en = 1;
1584 }
1585
1586 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1587 priv->tx_actual_en = 0;
1588
1589 gfar_write(®s->maccfg1, tempval1);
1590 gfar_write(®s->maccfg2, tempval);
1591 gfar_write(®s->ecntrl, ecntrl);
1592
1593 if (!priv->oldlink)
1594 priv->oldlink = 1;
1595
1596 } else if (priv->oldlink) {
1597 priv->oldlink = 0;
1598 priv->oldspeed = 0;
1599 priv->oldduplex = -1;
1600 }
1601
1602 if (netif_msg_link(priv))
1603 phy_print_status(phydev);
1604}
1605
1606
1607
1608
1609
1610
1611
1612static void adjust_link(struct net_device *dev)
1613{
1614 struct gfar_private *priv = netdev_priv(dev);
1615 struct phy_device *phydev = dev->phydev;
1616
1617 if (unlikely(phydev->link != priv->oldlink ||
1618 (phydev->link && (phydev->duplex != priv->oldduplex ||
1619 phydev->speed != priv->oldspeed))))
1620 gfar_update_link_state(priv);
1621}
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631static void gfar_configure_serdes(struct net_device *dev)
1632{
1633 struct gfar_private *priv = netdev_priv(dev);
1634 struct phy_device *tbiphy;
1635
1636 if (!priv->tbi_node) {
1637 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1638 "device tree specify a tbi-handle\n");
1639 return;
1640 }
1641
1642 tbiphy = of_phy_find_device(priv->tbi_node);
1643 if (!tbiphy) {
1644 dev_err(&dev->dev, "error: Could not get TBI device\n");
1645 return;
1646 }
1647
1648
1649
1650
1651
1652
1653 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1654 put_device(&tbiphy->mdio.dev);
1655 return;
1656 }
1657
1658
1659 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1660
1661 phy_write(tbiphy, MII_ADVERTISE,
1662 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1663 ADVERTISE_1000XPSE_ASYM);
1664
1665 phy_write(tbiphy, MII_BMCR,
1666 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1667 BMCR_SPEED1000);
1668
1669 put_device(&tbiphy->mdio.dev);
1670}
1671
1672
1673
1674
1675static int init_phy(struct net_device *dev)
1676{
1677 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1678 struct gfar_private *priv = netdev_priv(dev);
1679 phy_interface_t interface = priv->interface;
1680 struct phy_device *phydev;
1681 struct ethtool_eee edata;
1682
1683 linkmode_set_bit_array(phy_10_100_features_array,
1684 ARRAY_SIZE(phy_10_100_features_array),
1685 mask);
1686 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1687 linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1688 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1689 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1690
1691 priv->oldlink = 0;
1692 priv->oldspeed = 0;
1693 priv->oldduplex = -1;
1694
1695 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1696 interface);
1697 if (!phydev) {
1698 dev_err(&dev->dev, "could not attach to PHY\n");
1699 return -ENODEV;
1700 }
1701
1702 if (interface == PHY_INTERFACE_MODE_SGMII)
1703 gfar_configure_serdes(dev);
1704
1705
1706 linkmode_and(phydev->supported, phydev->supported, mask);
1707 linkmode_copy(phydev->advertising, phydev->supported);
1708
1709
1710 phy_support_asym_pause(phydev);
1711
1712
1713 memset(&edata, 0, sizeof(struct ethtool_eee));
1714 phy_ethtool_set_eee(phydev, &edata);
1715
1716 return 0;
1717}
1718
1719static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1720{
1721 struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1722
1723 memset(fcb, 0, GMAC_FCB_LEN);
1724
1725 return fcb;
1726}
1727
1728static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1729 int fcb_length)
1730{
1731
1732
1733
1734
1735 u8 flags = TXFCB_DEFAULT;
1736
1737
1738
1739
1740 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1741 flags |= TXFCB_UDP;
1742 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1743 } else
1744 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1745
1746
1747
1748
1749
1750
1751 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1752 fcb->l4os = skb_network_header_len(skb);
1753
1754 fcb->flags = flags;
1755}
1756
1757static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1758{
1759 fcb->flags |= TXFCB_VLN;
1760 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1761}
1762
1763static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1764 struct txbd8 *base, int ring_size)
1765{
1766 struct txbd8 *new_bd = bdp + stride;
1767
1768 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1769}
1770
1771static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1772 int ring_size)
1773{
1774 return skip_txbd(bdp, 1, base, ring_size);
1775}
1776
1777
1778static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1779 unsigned long fcb_addr)
1780{
1781 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1782 (fcb_addr % 0x20) > 0x18);
1783}
1784
1785
1786
1787
1788static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1789 unsigned int len)
1790{
1791 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1792 (len > 2500));
1793}
1794
1795
1796
1797
1798static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1799{
1800 struct gfar_private *priv = netdev_priv(dev);
1801 struct gfar_priv_tx_q *tx_queue = NULL;
1802 struct netdev_queue *txq;
1803 struct gfar __iomem *regs = NULL;
1804 struct txfcb *fcb = NULL;
1805 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1806 u32 lstatus;
1807 skb_frag_t *frag;
1808 int i, rq = 0;
1809 int do_tstamp, do_csum, do_vlan;
1810 u32 bufaddr;
1811 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1812
1813 rq = skb->queue_mapping;
1814 tx_queue = priv->tx_queue[rq];
1815 txq = netdev_get_tx_queue(dev, rq);
1816 base = tx_queue->tx_bd_base;
1817 regs = tx_queue->grp->regs;
1818
1819 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1820 do_vlan = skb_vlan_tag_present(skb);
1821 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1822 priv->hwts_tx_en;
1823
1824 if (do_csum || do_vlan)
1825 fcb_len = GMAC_FCB_LEN;
1826
1827
1828 if (unlikely(do_tstamp))
1829 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1830
1831
1832 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
1833 struct sk_buff *skb_new;
1834
1835 skb_new = skb_realloc_headroom(skb, fcb_len);
1836 if (!skb_new) {
1837 dev->stats.tx_errors++;
1838 dev_kfree_skb_any(skb);
1839 return NETDEV_TX_OK;
1840 }
1841
1842 if (skb->sk)
1843 skb_set_owner_w(skb_new, skb->sk);
1844 dev_consume_skb_any(skb);
1845 skb = skb_new;
1846 }
1847
1848
1849 nr_frags = skb_shinfo(skb)->nr_frags;
1850
1851
1852 if (unlikely(do_tstamp))
1853 nr_txbds = nr_frags + 2;
1854 else
1855 nr_txbds = nr_frags + 1;
1856
1857
1858 if (nr_txbds > tx_queue->num_txbdfree) {
1859
1860 netif_tx_stop_queue(txq);
1861 dev->stats.tx_fifo_errors++;
1862 return NETDEV_TX_BUSY;
1863 }
1864
1865
1866 bytes_sent = skb->len;
1867 tx_queue->stats.tx_bytes += bytes_sent;
1868
1869 GFAR_CB(skb)->bytes_sent = bytes_sent;
1870 tx_queue->stats.tx_packets++;
1871
1872 txbdp = txbdp_start = tx_queue->cur_tx;
1873 lstatus = be32_to_cpu(txbdp->lstatus);
1874
1875
1876 if (unlikely(do_tstamp)) {
1877 skb_push(skb, GMAC_TXPAL_LEN);
1878 memset(skb->data, 0, GMAC_TXPAL_LEN);
1879 }
1880
1881
1882 if (fcb_len) {
1883 fcb = gfar_add_fcb(skb);
1884 lstatus |= BD_LFLAG(TXBD_TOE);
1885 }
1886
1887
1888 if (do_csum) {
1889 gfar_tx_checksum(skb, fcb, fcb_len);
1890
1891 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1892 unlikely(gfar_csum_errata_76(priv, skb->len))) {
1893 __skb_pull(skb, GMAC_FCB_LEN);
1894 skb_checksum_help(skb);
1895 if (do_vlan || do_tstamp) {
1896
1897 fcb = gfar_add_fcb(skb);
1898 } else {
1899
1900 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1901 fcb = NULL;
1902 }
1903 }
1904 }
1905
1906 if (do_vlan)
1907 gfar_tx_vlan(skb, fcb);
1908
1909 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1910 DMA_TO_DEVICE);
1911 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1912 goto dma_map_err;
1913
1914 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1915
1916
1917 if (unlikely(do_tstamp))
1918 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1919 tx_queue->tx_ring_size);
1920
1921 if (likely(!nr_frags)) {
1922 if (likely(!do_tstamp))
1923 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1924 } else {
1925 u32 lstatus_start = lstatus;
1926
1927
1928 frag = &skb_shinfo(skb)->frags[0];
1929 for (i = 0; i < nr_frags; i++, frag++) {
1930 unsigned int size;
1931
1932
1933 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1934
1935 size = skb_frag_size(frag);
1936
1937 lstatus = be32_to_cpu(txbdp->lstatus) | size |
1938 BD_LFLAG(TXBD_READY);
1939
1940
1941 if (i == nr_frags - 1)
1942 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1943
1944 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1945 size, DMA_TO_DEVICE);
1946 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1947 goto dma_map_err;
1948
1949
1950 txbdp->bufPtr = cpu_to_be32(bufaddr);
1951 txbdp->lstatus = cpu_to_be32(lstatus);
1952 }
1953
1954 lstatus = lstatus_start;
1955 }
1956
1957
1958
1959
1960
1961
1962 if (unlikely(do_tstamp)) {
1963 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1964
1965 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1966 bufaddr += fcb_len;
1967
1968 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1969 (skb_headlen(skb) - fcb_len);
1970 if (!nr_frags)
1971 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1972
1973 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1974 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1975 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1976
1977
1978 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1979 fcb->ptp = 1;
1980 } else {
1981 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1982 }
1983
1984 netdev_tx_sent_queue(txq, bytes_sent);
1985
1986 gfar_wmb();
1987
1988 txbdp_start->lstatus = cpu_to_be32(lstatus);
1989
1990 gfar_wmb();
1991
1992 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1993
1994
1995
1996
1997 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1998 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1999
2000 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2001
2002
2003
2004
2005
2006
2007 spin_lock_bh(&tx_queue->txlock);
2008
2009 tx_queue->num_txbdfree -= (nr_txbds);
2010 spin_unlock_bh(&tx_queue->txlock);
2011
2012
2013
2014
2015 if (!tx_queue->num_txbdfree) {
2016 netif_tx_stop_queue(txq);
2017
2018 dev->stats.tx_fifo_errors++;
2019 }
2020
2021
2022 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2023
2024 return NETDEV_TX_OK;
2025
2026dma_map_err:
2027 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2028 if (do_tstamp)
2029 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2030 for (i = 0; i < nr_frags; i++) {
2031 lstatus = be32_to_cpu(txbdp->lstatus);
2032 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2033 break;
2034
2035 lstatus &= ~BD_LFLAG(TXBD_READY);
2036 txbdp->lstatus = cpu_to_be32(lstatus);
2037 bufaddr = be32_to_cpu(txbdp->bufPtr);
2038 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2039 DMA_TO_DEVICE);
2040 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2041 }
2042 gfar_wmb();
2043 dev_kfree_skb_any(skb);
2044 return NETDEV_TX_OK;
2045}
2046
2047
2048static int gfar_set_mac_address(struct net_device *dev)
2049{
2050 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2051
2052 return 0;
2053}
2054
2055static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2056{
2057 struct gfar_private *priv = netdev_priv(dev);
2058
2059 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2060 cpu_relax();
2061
2062 if (dev->flags & IFF_UP)
2063 stop_gfar(dev);
2064
2065 dev->mtu = new_mtu;
2066
2067 if (dev->flags & IFF_UP)
2068 startup_gfar(dev);
2069
2070 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2071
2072 return 0;
2073}
2074
2075static void reset_gfar(struct net_device *ndev)
2076{
2077 struct gfar_private *priv = netdev_priv(ndev);
2078
2079 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2080 cpu_relax();
2081
2082 stop_gfar(ndev);
2083 startup_gfar(ndev);
2084
2085 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2086}
2087
2088
2089
2090
2091
2092
2093static void gfar_reset_task(struct work_struct *work)
2094{
2095 struct gfar_private *priv = container_of(work, struct gfar_private,
2096 reset_task);
2097 reset_gfar(priv->ndev);
2098}
2099
2100static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2101{
2102 struct gfar_private *priv = netdev_priv(dev);
2103
2104 dev->stats.tx_errors++;
2105 schedule_work(&priv->reset_task);
2106}
2107
2108static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2109{
2110 struct hwtstamp_config config;
2111 struct gfar_private *priv = netdev_priv(netdev);
2112
2113 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2114 return -EFAULT;
2115
2116
2117 if (config.flags)
2118 return -EINVAL;
2119
2120 switch (config.tx_type) {
2121 case HWTSTAMP_TX_OFF:
2122 priv->hwts_tx_en = 0;
2123 break;
2124 case HWTSTAMP_TX_ON:
2125 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2126 return -ERANGE;
2127 priv->hwts_tx_en = 1;
2128 break;
2129 default:
2130 return -ERANGE;
2131 }
2132
2133 switch (config.rx_filter) {
2134 case HWTSTAMP_FILTER_NONE:
2135 if (priv->hwts_rx_en) {
2136 priv->hwts_rx_en = 0;
2137 reset_gfar(netdev);
2138 }
2139 break;
2140 default:
2141 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2142 return -ERANGE;
2143 if (!priv->hwts_rx_en) {
2144 priv->hwts_rx_en = 1;
2145 reset_gfar(netdev);
2146 }
2147 config.rx_filter = HWTSTAMP_FILTER_ALL;
2148 break;
2149 }
2150
2151 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2152 -EFAULT : 0;
2153}
2154
2155static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2156{
2157 struct hwtstamp_config config;
2158 struct gfar_private *priv = netdev_priv(netdev);
2159
2160 config.flags = 0;
2161 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2162 config.rx_filter = (priv->hwts_rx_en ?
2163 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2164
2165 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2166 -EFAULT : 0;
2167}
2168
2169static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2170{
2171 struct phy_device *phydev = dev->phydev;
2172
2173 if (!netif_running(dev))
2174 return -EINVAL;
2175
2176 if (cmd == SIOCSHWTSTAMP)
2177 return gfar_hwtstamp_set(dev, rq);
2178 if (cmd == SIOCGHWTSTAMP)
2179 return gfar_hwtstamp_get(dev, rq);
2180
2181 if (!phydev)
2182 return -ENODEV;
2183
2184 return phy_mii_ioctl(phydev, rq, cmd);
2185}
2186
2187
2188static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2189{
2190 struct net_device *dev = tx_queue->dev;
2191 struct netdev_queue *txq;
2192 struct gfar_private *priv = netdev_priv(dev);
2193 struct txbd8 *bdp, *next = NULL;
2194 struct txbd8 *lbdp = NULL;
2195 struct txbd8 *base = tx_queue->tx_bd_base;
2196 struct sk_buff *skb;
2197 int skb_dirtytx;
2198 int tx_ring_size = tx_queue->tx_ring_size;
2199 int frags = 0, nr_txbds = 0;
2200 int i;
2201 int howmany = 0;
2202 int tqi = tx_queue->qindex;
2203 unsigned int bytes_sent = 0;
2204 u32 lstatus;
2205 size_t buflen;
2206
2207 txq = netdev_get_tx_queue(dev, tqi);
2208 bdp = tx_queue->dirty_tx;
2209 skb_dirtytx = tx_queue->skb_dirtytx;
2210
2211 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2212 bool do_tstamp;
2213
2214 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2215 priv->hwts_tx_en;
2216
2217 frags = skb_shinfo(skb)->nr_frags;
2218
2219
2220
2221
2222 if (unlikely(do_tstamp))
2223 nr_txbds = frags + 2;
2224 else
2225 nr_txbds = frags + 1;
2226
2227 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2228
2229 lstatus = be32_to_cpu(lbdp->lstatus);
2230
2231
2232 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2233 (lstatus & BD_LENGTH_MASK))
2234 break;
2235
2236 if (unlikely(do_tstamp)) {
2237 next = next_txbd(bdp, base, tx_ring_size);
2238 buflen = be16_to_cpu(next->length) +
2239 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2240 } else
2241 buflen = be16_to_cpu(bdp->length);
2242
2243 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2244 buflen, DMA_TO_DEVICE);
2245
2246 if (unlikely(do_tstamp)) {
2247 struct skb_shared_hwtstamps shhwtstamps;
2248 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2249 ~0x7UL);
2250
2251 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2252 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2253 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2254 skb_tstamp_tx(skb, &shhwtstamps);
2255 gfar_clear_txbd_status(bdp);
2256 bdp = next;
2257 }
2258
2259 gfar_clear_txbd_status(bdp);
2260 bdp = next_txbd(bdp, base, tx_ring_size);
2261
2262 for (i = 0; i < frags; i++) {
2263 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2264 be16_to_cpu(bdp->length),
2265 DMA_TO_DEVICE);
2266 gfar_clear_txbd_status(bdp);
2267 bdp = next_txbd(bdp, base, tx_ring_size);
2268 }
2269
2270 bytes_sent += GFAR_CB(skb)->bytes_sent;
2271
2272 dev_kfree_skb_any(skb);
2273
2274 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2275
2276 skb_dirtytx = (skb_dirtytx + 1) &
2277 TX_RING_MOD_MASK(tx_ring_size);
2278
2279 howmany++;
2280 spin_lock(&tx_queue->txlock);
2281 tx_queue->num_txbdfree += nr_txbds;
2282 spin_unlock(&tx_queue->txlock);
2283 }
2284
2285
2286 if (tx_queue->num_txbdfree &&
2287 netif_tx_queue_stopped(txq) &&
2288 !(test_bit(GFAR_DOWN, &priv->state)))
2289 netif_wake_subqueue(priv->ndev, tqi);
2290
2291
2292 tx_queue->skb_dirtytx = skb_dirtytx;
2293 tx_queue->dirty_tx = bdp;
2294
2295 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2296}
2297
2298static void count_errors(u32 lstatus, struct net_device *ndev)
2299{
2300 struct gfar_private *priv = netdev_priv(ndev);
2301 struct net_device_stats *stats = &ndev->stats;
2302 struct gfar_extra_stats *estats = &priv->extra_stats;
2303
2304
2305 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2306 stats->rx_length_errors++;
2307
2308 atomic64_inc(&estats->rx_trunc);
2309
2310 return;
2311 }
2312
2313 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2314 stats->rx_length_errors++;
2315
2316 if (lstatus & BD_LFLAG(RXBD_LARGE))
2317 atomic64_inc(&estats->rx_large);
2318 else
2319 atomic64_inc(&estats->rx_short);
2320 }
2321 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2322 stats->rx_frame_errors++;
2323 atomic64_inc(&estats->rx_nonoctet);
2324 }
2325 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2326 atomic64_inc(&estats->rx_crcerr);
2327 stats->rx_crc_errors++;
2328 }
2329 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2330 atomic64_inc(&estats->rx_overrun);
2331 stats->rx_over_errors++;
2332 }
2333}
2334
2335static irqreturn_t gfar_receive(int irq, void *grp_id)
2336{
2337 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2338 unsigned long flags;
2339 u32 imask, ievent;
2340
2341 ievent = gfar_read(&grp->regs->ievent);
2342
2343 if (unlikely(ievent & IEVENT_FGPI)) {
2344 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2345 return IRQ_HANDLED;
2346 }
2347
2348 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2349 spin_lock_irqsave(&grp->grplock, flags);
2350 imask = gfar_read(&grp->regs->imask);
2351 imask &= IMASK_RX_DISABLED;
2352 gfar_write(&grp->regs->imask, imask);
2353 spin_unlock_irqrestore(&grp->grplock, flags);
2354 __napi_schedule(&grp->napi_rx);
2355 } else {
2356
2357
2358
2359 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2360 }
2361
2362 return IRQ_HANDLED;
2363}
2364
2365
2366static irqreturn_t gfar_transmit(int irq, void *grp_id)
2367{
2368 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2369 unsigned long flags;
2370 u32 imask;
2371
2372 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2373 spin_lock_irqsave(&grp->grplock, flags);
2374 imask = gfar_read(&grp->regs->imask);
2375 imask &= IMASK_TX_DISABLED;
2376 gfar_write(&grp->regs->imask, imask);
2377 spin_unlock_irqrestore(&grp->grplock, flags);
2378 __napi_schedule(&grp->napi_tx);
2379 } else {
2380
2381
2382
2383 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2384 }
2385
2386 return IRQ_HANDLED;
2387}
2388
2389static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2390 struct sk_buff *skb, bool first)
2391{
2392 int size = lstatus & BD_LENGTH_MASK;
2393 struct page *page = rxb->page;
2394
2395 if (likely(first)) {
2396 skb_put(skb, size);
2397 } else {
2398
2399 if (lstatus & BD_LFLAG(RXBD_LAST))
2400 size -= skb->len;
2401
2402 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2403 rxb->page_offset + RXBUF_ALIGNMENT,
2404 size, GFAR_RXB_TRUESIZE);
2405 }
2406
2407
2408 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2409 return false;
2410
2411
2412 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2413
2414 page_ref_inc(page);
2415
2416 return true;
2417}
2418
2419static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2420 struct gfar_rx_buff *old_rxb)
2421{
2422 struct gfar_rx_buff *new_rxb;
2423 u16 nta = rxq->next_to_alloc;
2424
2425 new_rxb = &rxq->rx_buff[nta];
2426
2427
2428 nta++;
2429 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2430
2431
2432 *new_rxb = *old_rxb;
2433
2434
2435 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2436 old_rxb->page_offset,
2437 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2438}
2439
2440static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2441 u32 lstatus, struct sk_buff *skb)
2442{
2443 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2444 struct page *page = rxb->page;
2445 bool first = false;
2446
2447 if (likely(!skb)) {
2448 void *buff_addr = page_address(page) + rxb->page_offset;
2449
2450 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2451 if (unlikely(!skb)) {
2452 gfar_rx_alloc_err(rx_queue);
2453 return NULL;
2454 }
2455 skb_reserve(skb, RXBUF_ALIGNMENT);
2456 first = true;
2457 }
2458
2459 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2460 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2461
2462 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2463
2464 gfar_reuse_rx_page(rx_queue, rxb);
2465 } else {
2466
2467 dma_unmap_page(rx_queue->dev, rxb->dma,
2468 PAGE_SIZE, DMA_FROM_DEVICE);
2469 }
2470
2471
2472 rxb->page = NULL;
2473
2474 return skb;
2475}
2476
2477static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2478{
2479
2480
2481
2482
2483 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2484 (RXFCB_CIP | RXFCB_CTU))
2485 skb->ip_summed = CHECKSUM_UNNECESSARY;
2486 else
2487 skb_checksum_none_assert(skb);
2488}
2489
2490
2491static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2492{
2493 struct gfar_private *priv = netdev_priv(ndev);
2494 struct rxfcb *fcb = NULL;
2495
2496
2497 fcb = (struct rxfcb *)skb->data;
2498
2499
2500
2501
2502 if (priv->uses_rxfcb)
2503 skb_pull(skb, GMAC_FCB_LEN);
2504
2505
2506 if (priv->hwts_rx_en) {
2507 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2508 u64 *ns = (u64 *) skb->data;
2509
2510 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2511 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2512 }
2513
2514 if (priv->padding)
2515 skb_pull(skb, priv->padding);
2516
2517
2518 pskb_trim(skb, skb->len - ETH_FCS_LEN);
2519
2520 if (ndev->features & NETIF_F_RXCSUM)
2521 gfar_rx_checksum(skb, fcb);
2522
2523
2524
2525
2526
2527 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2528 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2529 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2530 be16_to_cpu(fcb->vlctl));
2531}
2532
2533
2534
2535
2536
2537static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2538 int rx_work_limit)
2539{
2540 struct net_device *ndev = rx_queue->ndev;
2541 struct gfar_private *priv = netdev_priv(ndev);
2542 struct rxbd8 *bdp;
2543 int i, howmany = 0;
2544 struct sk_buff *skb = rx_queue->skb;
2545 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2546 unsigned int total_bytes = 0, total_pkts = 0;
2547
2548
2549 i = rx_queue->next_to_clean;
2550
2551 while (rx_work_limit--) {
2552 u32 lstatus;
2553
2554 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2555 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2556 cleaned_cnt = 0;
2557 }
2558
2559 bdp = &rx_queue->rx_bd_base[i];
2560 lstatus = be32_to_cpu(bdp->lstatus);
2561 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2562 break;
2563
2564
2565 rmb();
2566
2567
2568 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2569 if (unlikely(!skb))
2570 break;
2571
2572 cleaned_cnt++;
2573 howmany++;
2574
2575 if (unlikely(++i == rx_queue->rx_ring_size))
2576 i = 0;
2577
2578 rx_queue->next_to_clean = i;
2579
2580
2581 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2582 continue;
2583
2584 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2585 count_errors(lstatus, ndev);
2586
2587
2588 dev_kfree_skb(skb);
2589 skb = NULL;
2590 rx_queue->stats.rx_dropped++;
2591 continue;
2592 }
2593
2594 gfar_process_frame(ndev, skb);
2595
2596
2597 total_pkts++;
2598 total_bytes += skb->len;
2599
2600 skb_record_rx_queue(skb, rx_queue->qindex);
2601
2602 skb->protocol = eth_type_trans(skb, ndev);
2603
2604
2605 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2606
2607 skb = NULL;
2608 }
2609
2610
2611 rx_queue->skb = skb;
2612
2613 rx_queue->stats.rx_packets += total_pkts;
2614 rx_queue->stats.rx_bytes += total_bytes;
2615
2616 if (cleaned_cnt)
2617 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2618
2619
2620 if (unlikely(priv->tx_actual_en)) {
2621 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2622
2623 gfar_write(rx_queue->rfbptr, bdp_dma);
2624 }
2625
2626 return howmany;
2627}
2628
2629static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2630{
2631 struct gfar_priv_grp *gfargrp =
2632 container_of(napi, struct gfar_priv_grp, napi_rx);
2633 struct gfar __iomem *regs = gfargrp->regs;
2634 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2635 int work_done = 0;
2636
2637
2638
2639
2640 gfar_write(®s->ievent, IEVENT_RX_MASK);
2641
2642 work_done = gfar_clean_rx_ring(rx_queue, budget);
2643
2644 if (work_done < budget) {
2645 u32 imask;
2646 napi_complete_done(napi, work_done);
2647
2648 gfar_write(®s->rstat, gfargrp->rstat);
2649
2650 spin_lock_irq(&gfargrp->grplock);
2651 imask = gfar_read(®s->imask);
2652 imask |= IMASK_RX_DEFAULT;
2653 gfar_write(®s->imask, imask);
2654 spin_unlock_irq(&gfargrp->grplock);
2655 }
2656
2657 return work_done;
2658}
2659
2660static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2661{
2662 struct gfar_priv_grp *gfargrp =
2663 container_of(napi, struct gfar_priv_grp, napi_tx);
2664 struct gfar __iomem *regs = gfargrp->regs;
2665 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2666 u32 imask;
2667
2668
2669
2670
2671 gfar_write(®s->ievent, IEVENT_TX_MASK);
2672
2673
2674 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2675 gfar_clean_tx_ring(tx_queue);
2676
2677 napi_complete(napi);
2678
2679 spin_lock_irq(&gfargrp->grplock);
2680 imask = gfar_read(®s->imask);
2681 imask |= IMASK_TX_DEFAULT;
2682 gfar_write(®s->imask, imask);
2683 spin_unlock_irq(&gfargrp->grplock);
2684
2685 return 0;
2686}
2687
2688static int gfar_poll_rx(struct napi_struct *napi, int budget)
2689{
2690 struct gfar_priv_grp *gfargrp =
2691 container_of(napi, struct gfar_priv_grp, napi_rx);
2692 struct gfar_private *priv = gfargrp->priv;
2693 struct gfar __iomem *regs = gfargrp->regs;
2694 struct gfar_priv_rx_q *rx_queue = NULL;
2695 int work_done = 0, work_done_per_q = 0;
2696 int i, budget_per_q = 0;
2697 unsigned long rstat_rxf;
2698 int num_act_queues;
2699
2700
2701
2702
2703 gfar_write(®s->ievent, IEVENT_RX_MASK);
2704
2705 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
2706
2707 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2708 if (num_act_queues)
2709 budget_per_q = budget/num_act_queues;
2710
2711 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2712
2713 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2714 continue;
2715
2716 rx_queue = priv->rx_queue[i];
2717 work_done_per_q =
2718 gfar_clean_rx_ring(rx_queue, budget_per_q);
2719 work_done += work_done_per_q;
2720
2721
2722 if (work_done_per_q < budget_per_q) {
2723
2724 gfar_write(®s->rstat,
2725 RSTAT_CLEAR_RXF0 >> i);
2726 num_act_queues--;
2727
2728 if (!num_act_queues)
2729 break;
2730 }
2731 }
2732
2733 if (!num_act_queues) {
2734 u32 imask;
2735 napi_complete_done(napi, work_done);
2736
2737
2738 gfar_write(®s->rstat, gfargrp->rstat);
2739
2740 spin_lock_irq(&gfargrp->grplock);
2741 imask = gfar_read(®s->imask);
2742 imask |= IMASK_RX_DEFAULT;
2743 gfar_write(®s->imask, imask);
2744 spin_unlock_irq(&gfargrp->grplock);
2745 }
2746
2747 return work_done;
2748}
2749
2750static int gfar_poll_tx(struct napi_struct *napi, int budget)
2751{
2752 struct gfar_priv_grp *gfargrp =
2753 container_of(napi, struct gfar_priv_grp, napi_tx);
2754 struct gfar_private *priv = gfargrp->priv;
2755 struct gfar __iomem *regs = gfargrp->regs;
2756 struct gfar_priv_tx_q *tx_queue = NULL;
2757 int has_tx_work = 0;
2758 int i;
2759
2760
2761
2762
2763 gfar_write(®s->ievent, IEVENT_TX_MASK);
2764
2765 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2766 tx_queue = priv->tx_queue[i];
2767
2768 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2769 gfar_clean_tx_ring(tx_queue);
2770 has_tx_work = 1;
2771 }
2772 }
2773
2774 if (!has_tx_work) {
2775 u32 imask;
2776 napi_complete(napi);
2777
2778 spin_lock_irq(&gfargrp->grplock);
2779 imask = gfar_read(®s->imask);
2780 imask |= IMASK_TX_DEFAULT;
2781 gfar_write(®s->imask, imask);
2782 spin_unlock_irq(&gfargrp->grplock);
2783 }
2784
2785 return 0;
2786}
2787
2788
2789static irqreturn_t gfar_error(int irq, void *grp_id)
2790{
2791 struct gfar_priv_grp *gfargrp = grp_id;
2792 struct gfar __iomem *regs = gfargrp->regs;
2793 struct gfar_private *priv= gfargrp->priv;
2794 struct net_device *dev = priv->ndev;
2795
2796
2797 u32 events = gfar_read(®s->ievent);
2798
2799
2800 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
2801
2802
2803 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2804 (events & IEVENT_MAG))
2805 events &= ~IEVENT_MAG;
2806
2807
2808 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2809 netdev_dbg(dev,
2810 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2811 events, gfar_read(®s->imask));
2812
2813
2814 if (events & IEVENT_TXE) {
2815 dev->stats.tx_errors++;
2816
2817 if (events & IEVENT_LC)
2818 dev->stats.tx_window_errors++;
2819 if (events & IEVENT_CRL)
2820 dev->stats.tx_aborted_errors++;
2821 if (events & IEVENT_XFUN) {
2822 netif_dbg(priv, tx_err, dev,
2823 "TX FIFO underrun, packet dropped\n");
2824 dev->stats.tx_dropped++;
2825 atomic64_inc(&priv->extra_stats.tx_underrun);
2826
2827 schedule_work(&priv->reset_task);
2828 }
2829 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2830 }
2831 if (events & IEVENT_BSY) {
2832 dev->stats.rx_over_errors++;
2833 atomic64_inc(&priv->extra_stats.rx_bsy);
2834
2835 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2836 gfar_read(®s->rstat));
2837 }
2838 if (events & IEVENT_BABR) {
2839 dev->stats.rx_errors++;
2840 atomic64_inc(&priv->extra_stats.rx_babr);
2841
2842 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2843 }
2844 if (events & IEVENT_EBERR) {
2845 atomic64_inc(&priv->extra_stats.eberr);
2846 netif_dbg(priv, rx_err, dev, "bus error\n");
2847 }
2848 if (events & IEVENT_RXC)
2849 netif_dbg(priv, rx_status, dev, "control frame\n");
2850
2851 if (events & IEVENT_BABT) {
2852 atomic64_inc(&priv->extra_stats.tx_babt);
2853 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2854 }
2855 return IRQ_HANDLED;
2856}
2857
2858
2859static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2860{
2861 struct gfar_priv_grp *gfargrp = grp_id;
2862
2863
2864 u32 events = gfar_read(&gfargrp->regs->ievent);
2865
2866
2867 if (events & IEVENT_RX_MASK)
2868 gfar_receive(irq, grp_id);
2869
2870
2871 if (events & IEVENT_TX_MASK)
2872 gfar_transmit(irq, grp_id);
2873
2874
2875 if (events & IEVENT_ERR_MASK)
2876 gfar_error(irq, grp_id);
2877
2878 return IRQ_HANDLED;
2879}
2880
2881#ifdef CONFIG_NET_POLL_CONTROLLER
2882
2883
2884
2885
2886static void gfar_netpoll(struct net_device *dev)
2887{
2888 struct gfar_private *priv = netdev_priv(dev);
2889 int i;
2890
2891
2892 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2893 for (i = 0; i < priv->num_grps; i++) {
2894 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2895
2896 disable_irq(gfar_irq(grp, TX)->irq);
2897 disable_irq(gfar_irq(grp, RX)->irq);
2898 disable_irq(gfar_irq(grp, ER)->irq);
2899 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2900 enable_irq(gfar_irq(grp, ER)->irq);
2901 enable_irq(gfar_irq(grp, RX)->irq);
2902 enable_irq(gfar_irq(grp, TX)->irq);
2903 }
2904 } else {
2905 for (i = 0; i < priv->num_grps; i++) {
2906 struct gfar_priv_grp *grp = &priv->gfargrp[i];
2907
2908 disable_irq(gfar_irq(grp, TX)->irq);
2909 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2910 enable_irq(gfar_irq(grp, TX)->irq);
2911 }
2912 }
2913}
2914#endif
2915
2916static void free_grp_irqs(struct gfar_priv_grp *grp)
2917{
2918 free_irq(gfar_irq(grp, TX)->irq, grp);
2919 free_irq(gfar_irq(grp, RX)->irq, grp);
2920 free_irq(gfar_irq(grp, ER)->irq, grp);
2921}
2922
2923static int register_grp_irqs(struct gfar_priv_grp *grp)
2924{
2925 struct gfar_private *priv = grp->priv;
2926 struct net_device *dev = priv->ndev;
2927 int err;
2928
2929
2930
2931
2932 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2933
2934
2935
2936 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2937 gfar_irq(grp, ER)->name, grp);
2938 if (err < 0) {
2939 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2940 gfar_irq(grp, ER)->irq);
2941
2942 goto err_irq_fail;
2943 }
2944 enable_irq_wake(gfar_irq(grp, ER)->irq);
2945
2946 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2947 gfar_irq(grp, TX)->name, grp);
2948 if (err < 0) {
2949 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2950 gfar_irq(grp, TX)->irq);
2951 goto tx_irq_fail;
2952 }
2953 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2954 gfar_irq(grp, RX)->name, grp);
2955 if (err < 0) {
2956 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2957 gfar_irq(grp, RX)->irq);
2958 goto rx_irq_fail;
2959 }
2960 enable_irq_wake(gfar_irq(grp, RX)->irq);
2961
2962 } else {
2963 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2964 gfar_irq(grp, TX)->name, grp);
2965 if (err < 0) {
2966 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2967 gfar_irq(grp, TX)->irq);
2968 goto err_irq_fail;
2969 }
2970 enable_irq_wake(gfar_irq(grp, TX)->irq);
2971 }
2972
2973 return 0;
2974
2975rx_irq_fail:
2976 free_irq(gfar_irq(grp, TX)->irq, grp);
2977tx_irq_fail:
2978 free_irq(gfar_irq(grp, ER)->irq, grp);
2979err_irq_fail:
2980 return err;
2981
2982}
2983
2984static void gfar_free_irq(struct gfar_private *priv)
2985{
2986 int i;
2987
2988
2989 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2990 for (i = 0; i < priv->num_grps; i++)
2991 free_grp_irqs(&priv->gfargrp[i]);
2992 } else {
2993 for (i = 0; i < priv->num_grps; i++)
2994 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2995 &priv->gfargrp[i]);
2996 }
2997}
2998
2999static int gfar_request_irq(struct gfar_private *priv)
3000{
3001 int err, i, j;
3002
3003 for (i = 0; i < priv->num_grps; i++) {
3004 err = register_grp_irqs(&priv->gfargrp[i]);
3005 if (err) {
3006 for (j = 0; j < i; j++)
3007 free_grp_irqs(&priv->gfargrp[j]);
3008 return err;
3009 }
3010 }
3011
3012 return 0;
3013}
3014
3015
3016
3017
3018static int gfar_enet_open(struct net_device *dev)
3019{
3020 struct gfar_private *priv = netdev_priv(dev);
3021 int err;
3022
3023 err = init_phy(dev);
3024 if (err)
3025 return err;
3026
3027 err = gfar_request_irq(priv);
3028 if (err)
3029 return err;
3030
3031 err = startup_gfar(dev);
3032 if (err)
3033 return err;
3034
3035 return err;
3036}
3037
3038
3039static int gfar_close(struct net_device *dev)
3040{
3041 struct gfar_private *priv = netdev_priv(dev);
3042
3043 cancel_work_sync(&priv->reset_task);
3044 stop_gfar(dev);
3045
3046
3047 phy_disconnect(dev->phydev);
3048
3049 gfar_free_irq(priv);
3050
3051 return 0;
3052}
3053
3054
3055
3056
3057static void gfar_clear_exact_match(struct net_device *dev)
3058{
3059 int idx;
3060 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3061
3062 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3063 gfar_set_mac_for_addr(dev, idx, zero_arr);
3064}
3065
3066
3067
3068
3069
3070
3071static void gfar_set_multi(struct net_device *dev)
3072{
3073 struct netdev_hw_addr *ha;
3074 struct gfar_private *priv = netdev_priv(dev);
3075 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3076 u32 tempval;
3077
3078 if (dev->flags & IFF_PROMISC) {
3079
3080 tempval = gfar_read(®s->rctrl);
3081 tempval |= RCTRL_PROM;
3082 gfar_write(®s->rctrl, tempval);
3083 } else {
3084
3085 tempval = gfar_read(®s->rctrl);
3086 tempval &= ~(RCTRL_PROM);
3087 gfar_write(®s->rctrl, tempval);
3088 }
3089
3090 if (dev->flags & IFF_ALLMULTI) {
3091
3092 gfar_write(®s->igaddr0, 0xffffffff);
3093 gfar_write(®s->igaddr1, 0xffffffff);
3094 gfar_write(®s->igaddr2, 0xffffffff);
3095 gfar_write(®s->igaddr3, 0xffffffff);
3096 gfar_write(®s->igaddr4, 0xffffffff);
3097 gfar_write(®s->igaddr5, 0xffffffff);
3098 gfar_write(®s->igaddr6, 0xffffffff);
3099 gfar_write(®s->igaddr7, 0xffffffff);
3100 gfar_write(®s->gaddr0, 0xffffffff);
3101 gfar_write(®s->gaddr1, 0xffffffff);
3102 gfar_write(®s->gaddr2, 0xffffffff);
3103 gfar_write(®s->gaddr3, 0xffffffff);
3104 gfar_write(®s->gaddr4, 0xffffffff);
3105 gfar_write(®s->gaddr5, 0xffffffff);
3106 gfar_write(®s->gaddr6, 0xffffffff);
3107 gfar_write(®s->gaddr7, 0xffffffff);
3108 } else {
3109 int em_num;
3110 int idx;
3111
3112
3113 gfar_write(®s->igaddr0, 0x0);
3114 gfar_write(®s->igaddr1, 0x0);
3115 gfar_write(®s->igaddr2, 0x0);
3116 gfar_write(®s->igaddr3, 0x0);
3117 gfar_write(®s->igaddr4, 0x0);
3118 gfar_write(®s->igaddr5, 0x0);
3119 gfar_write(®s->igaddr6, 0x0);
3120 gfar_write(®s->igaddr7, 0x0);
3121 gfar_write(®s->gaddr0, 0x0);
3122 gfar_write(®s->gaddr1, 0x0);
3123 gfar_write(®s->gaddr2, 0x0);
3124 gfar_write(®s->gaddr3, 0x0);
3125 gfar_write(®s->gaddr4, 0x0);
3126 gfar_write(®s->gaddr5, 0x0);
3127 gfar_write(®s->gaddr6, 0x0);
3128 gfar_write(®s->gaddr7, 0x0);
3129
3130
3131
3132
3133
3134 if (priv->extended_hash) {
3135 em_num = GFAR_EM_NUM + 1;
3136 gfar_clear_exact_match(dev);
3137 idx = 1;
3138 } else {
3139 idx = 0;
3140 em_num = 0;
3141 }
3142
3143 if (netdev_mc_empty(dev))
3144 return;
3145
3146
3147 netdev_for_each_mc_addr(ha, dev) {
3148 if (idx < em_num) {
3149 gfar_set_mac_for_addr(dev, idx, ha->addr);
3150 idx++;
3151 } else
3152 gfar_set_hash_for_addr(dev, ha->addr);
3153 }
3154 }
3155}
3156
3157void gfar_mac_reset(struct gfar_private *priv)
3158{
3159 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3160 u32 tempval;
3161
3162
3163 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
3164
3165
3166 udelay(3);
3167
3168
3169
3170
3171 gfar_write(®s->maccfg1, 0);
3172
3173 udelay(3);
3174
3175 gfar_rx_offload_en(priv);
3176
3177
3178 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3179 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
3180
3181
3182 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
3183
3184
3185 tempval = MACCFG2_INIT_SETTINGS;
3186
3187
3188
3189
3190
3191 if (gfar_has_errata(priv, GFAR_ERRATA_74))
3192 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3193
3194 gfar_write(®s->maccfg2, tempval);
3195
3196
3197 gfar_write(®s->igaddr0, 0);
3198 gfar_write(®s->igaddr1, 0);
3199 gfar_write(®s->igaddr2, 0);
3200 gfar_write(®s->igaddr3, 0);
3201 gfar_write(®s->igaddr4, 0);
3202 gfar_write(®s->igaddr5, 0);
3203 gfar_write(®s->igaddr6, 0);
3204 gfar_write(®s->igaddr7, 0);
3205
3206 gfar_write(®s->gaddr0, 0);
3207 gfar_write(®s->gaddr1, 0);
3208 gfar_write(®s->gaddr2, 0);
3209 gfar_write(®s->gaddr3, 0);
3210 gfar_write(®s->gaddr4, 0);
3211 gfar_write(®s->gaddr5, 0);
3212 gfar_write(®s->gaddr6, 0);
3213 gfar_write(®s->gaddr7, 0);
3214
3215 if (priv->extended_hash)
3216 gfar_clear_exact_match(priv->ndev);
3217
3218 gfar_mac_rx_config(priv);
3219
3220 gfar_mac_tx_config(priv);
3221
3222 gfar_set_mac_address(priv->ndev);
3223
3224 gfar_set_multi(priv->ndev);
3225
3226
3227 gfar_ints_disable(priv);
3228
3229
3230 gfar_configure_coalescing_all(priv);
3231}
3232
3233static void gfar_hw_init(struct gfar_private *priv)
3234{
3235 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3236 u32 attrs;
3237
3238
3239
3240
3241 gfar_halt(priv);
3242
3243 gfar_mac_reset(priv);
3244
3245
3246 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3247 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3248
3249
3250 gfar_write(®s->rmon.cam1, 0xffffffff);
3251 gfar_write(®s->rmon.cam2, 0xffffffff);
3252 }
3253
3254
3255 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
3256
3257
3258 attrs = ATTRELI_EL(priv->rx_stash_size) |
3259 ATTRELI_EI(priv->rx_stash_index);
3260
3261 gfar_write(®s->attreli, attrs);
3262
3263
3264
3265
3266 attrs = ATTR_INIT_SETTINGS;
3267
3268 if (priv->bd_stash_en)
3269 attrs |= ATTR_BDSTASH;
3270
3271 if (priv->rx_stash_size != 0)
3272 attrs |= ATTR_BUFSTASH;
3273
3274 gfar_write(®s->attr, attrs);
3275
3276
3277 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3278 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3279 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3280
3281
3282 if (priv->num_grps > 1)
3283 gfar_write_isrg(priv);
3284}
3285
3286static const struct net_device_ops gfar_netdev_ops = {
3287 .ndo_open = gfar_enet_open,
3288 .ndo_start_xmit = gfar_start_xmit,
3289 .ndo_stop = gfar_close,
3290 .ndo_change_mtu = gfar_change_mtu,
3291 .ndo_set_features = gfar_set_features,
3292 .ndo_set_rx_mode = gfar_set_multi,
3293 .ndo_tx_timeout = gfar_timeout,
3294 .ndo_do_ioctl = gfar_ioctl,
3295 .ndo_get_stats = gfar_get_stats,
3296 .ndo_change_carrier = fixed_phy_change_carrier,
3297 .ndo_set_mac_address = gfar_set_mac_addr,
3298 .ndo_validate_addr = eth_validate_addr,
3299#ifdef CONFIG_NET_POLL_CONTROLLER
3300 .ndo_poll_controller = gfar_netpoll,
3301#endif
3302};
3303
3304
3305
3306
3307static int gfar_probe(struct platform_device *ofdev)
3308{
3309 struct device_node *np = ofdev->dev.of_node;
3310 struct net_device *dev = NULL;
3311 struct gfar_private *priv = NULL;
3312 int err = 0, i;
3313
3314 err = gfar_of_init(ofdev, &dev);
3315
3316 if (err)
3317 return err;
3318
3319 priv = netdev_priv(dev);
3320 priv->ndev = dev;
3321 priv->ofdev = ofdev;
3322 priv->dev = &ofdev->dev;
3323 SET_NETDEV_DEV(dev, &ofdev->dev);
3324
3325 INIT_WORK(&priv->reset_task, gfar_reset_task);
3326
3327 platform_set_drvdata(ofdev, priv);
3328
3329 gfar_detect_errata(priv);
3330
3331
3332 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3333
3334
3335 dev->watchdog_timeo = TX_TIMEOUT;
3336
3337 dev->mtu = 1500;
3338 dev->min_mtu = 50;
3339 dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3340 dev->netdev_ops = &gfar_netdev_ops;
3341 dev->ethtool_ops = &gfar_ethtool_ops;
3342
3343
3344 for (i = 0; i < priv->num_grps; i++) {
3345 if (priv->poll_mode == GFAR_SQ_POLLING) {
3346 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3347 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3348 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3349 gfar_poll_tx_sq, 2);
3350 } else {
3351 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3352 gfar_poll_rx, GFAR_DEV_WEIGHT);
3353 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3354 gfar_poll_tx, 2);
3355 }
3356 }
3357
3358 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3359 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3360 NETIF_F_RXCSUM;
3361 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3362 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3363 }
3364
3365 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3366 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3367 NETIF_F_HW_VLAN_CTAG_RX;
3368 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3369 }
3370
3371 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3372
3373 gfar_init_addr_hash_table(priv);
3374
3375
3376
3377
3378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3379 priv->padding = 8 + DEFAULT_PADDING;
3380
3381 if (dev->features & NETIF_F_IP_CSUM ||
3382 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3383 dev->needed_headroom = GMAC_FCB_LEN;
3384
3385
3386 for (i = 0; i < priv->num_tx_queues; i++) {
3387 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3388 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3389 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3390 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3391 }
3392
3393 for (i = 0; i < priv->num_rx_queues; i++) {
3394 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3395 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3396 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3397 }
3398
3399
3400 priv->rx_filer_enable =
3401 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3402
3403 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3404
3405 if (priv->num_tx_queues == 1)
3406 priv->prio_sched_en = 1;
3407
3408 set_bit(GFAR_DOWN, &priv->state);
3409
3410 gfar_hw_init(priv);
3411
3412
3413 netif_carrier_off(dev);
3414
3415 err = register_netdev(dev);
3416
3417 if (err) {
3418 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3419 goto register_fail;
3420 }
3421
3422 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3423 priv->wol_supported |= GFAR_WOL_MAGIC;
3424
3425 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3426 priv->rx_filer_enable)
3427 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3428
3429 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3430
3431
3432 for (i = 0; i < priv->num_grps; i++) {
3433 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3434 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3435 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3436 dev->name, "_g", '0' + i, "_tx");
3437 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3438 dev->name, "_g", '0' + i, "_rx");
3439 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3440 dev->name, "_g", '0' + i, "_er");
3441 } else
3442 strcpy(gfar_irq(grp, TX)->name, dev->name);
3443 }
3444
3445
3446 gfar_init_filer_table(priv);
3447
3448
3449 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3450
3451
3452
3453
3454 netdev_info(dev, "Running with NAPI enabled\n");
3455 for (i = 0; i < priv->num_rx_queues; i++)
3456 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3457 i, priv->rx_queue[i]->rx_ring_size);
3458 for (i = 0; i < priv->num_tx_queues; i++)
3459 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3460 i, priv->tx_queue[i]->tx_ring_size);
3461
3462 return 0;
3463
3464register_fail:
3465 if (of_phy_is_fixed_link(np))
3466 of_phy_deregister_fixed_link(np);
3467 unmap_group_regs(priv);
3468 gfar_free_rx_queues(priv);
3469 gfar_free_tx_queues(priv);
3470 of_node_put(priv->phy_node);
3471 of_node_put(priv->tbi_node);
3472 free_gfar_dev(priv);
3473 return err;
3474}
3475
3476static int gfar_remove(struct platform_device *ofdev)
3477{
3478 struct gfar_private *priv = platform_get_drvdata(ofdev);
3479 struct device_node *np = ofdev->dev.of_node;
3480
3481 of_node_put(priv->phy_node);
3482 of_node_put(priv->tbi_node);
3483
3484 unregister_netdev(priv->ndev);
3485
3486 if (of_phy_is_fixed_link(np))
3487 of_phy_deregister_fixed_link(np);
3488
3489 unmap_group_regs(priv);
3490 gfar_free_rx_queues(priv);
3491 gfar_free_tx_queues(priv);
3492 free_gfar_dev(priv);
3493
3494 return 0;
3495}
3496
3497#ifdef CONFIG_PM
3498
3499static void __gfar_filer_disable(struct gfar_private *priv)
3500{
3501 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3502 u32 temp;
3503
3504 temp = gfar_read(®s->rctrl);
3505 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3506 gfar_write(®s->rctrl, temp);
3507}
3508
3509static void __gfar_filer_enable(struct gfar_private *priv)
3510{
3511 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3512 u32 temp;
3513
3514 temp = gfar_read(®s->rctrl);
3515 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3516 gfar_write(®s->rctrl, temp);
3517}
3518
3519
3520static void gfar_filer_config_wol(struct gfar_private *priv)
3521{
3522 unsigned int i;
3523 u32 rqfcr;
3524
3525 __gfar_filer_disable(priv);
3526
3527
3528 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3529 for (i = 0; i <= MAX_FILER_IDX; i++)
3530 gfar_write_filer(priv, i, rqfcr, 0);
3531
3532 i = 0;
3533 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3534
3535 struct net_device *ndev = priv->ndev;
3536
3537 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3538 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3539 (ndev->dev_addr[1] << 8) |
3540 ndev->dev_addr[2];
3541
3542 rqfcr = (qindex << 10) | RQFCR_AND |
3543 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3544
3545 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3546
3547 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3548 (ndev->dev_addr[4] << 8) |
3549 ndev->dev_addr[5];
3550 rqfcr = (qindex << 10) | RQFCR_GPI |
3551 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3552 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3553 }
3554
3555 __gfar_filer_enable(priv);
3556}
3557
3558static void gfar_filer_restore_table(struct gfar_private *priv)
3559{
3560 u32 rqfcr, rqfpr;
3561 unsigned int i;
3562
3563 __gfar_filer_disable(priv);
3564
3565 for (i = 0; i <= MAX_FILER_IDX; i++) {
3566 rqfcr = priv->ftp_rqfcr[i];
3567 rqfpr = priv->ftp_rqfpr[i];
3568 gfar_write_filer(priv, i, rqfcr, rqfpr);
3569 }
3570
3571 __gfar_filer_enable(priv);
3572}
3573
3574
3575static void gfar_start_wol_filer(struct gfar_private *priv)
3576{
3577 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3578 u32 tempval;
3579 int i = 0;
3580
3581
3582 gfar_write(®s->rqueue, priv->rqueue);
3583
3584
3585 tempval = gfar_read(®s->dmactrl);
3586 tempval |= DMACTRL_INIT_SETTINGS;
3587 gfar_write(®s->dmactrl, tempval);
3588
3589
3590 tempval = gfar_read(®s->dmactrl);
3591 tempval &= ~DMACTRL_GRS;
3592 gfar_write(®s->dmactrl, tempval);
3593
3594 for (i = 0; i < priv->num_grps; i++) {
3595 regs = priv->gfargrp[i].regs;
3596
3597 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
3598
3599 gfar_write(®s->imask, IMASK_FGPI);
3600 }
3601
3602
3603 tempval = gfar_read(®s->maccfg1);
3604 tempval |= MACCFG1_RX_EN;
3605 gfar_write(®s->maccfg1, tempval);
3606}
3607
3608static int gfar_suspend(struct device *dev)
3609{
3610 struct gfar_private *priv = dev_get_drvdata(dev);
3611 struct net_device *ndev = priv->ndev;
3612 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3613 u32 tempval;
3614 u16 wol = priv->wol_opts;
3615
3616 if (!netif_running(ndev))
3617 return 0;
3618
3619 disable_napi(priv);
3620 netif_tx_lock(ndev);
3621 netif_device_detach(ndev);
3622 netif_tx_unlock(ndev);
3623
3624 gfar_halt(priv);
3625
3626 if (wol & GFAR_WOL_MAGIC) {
3627
3628 gfar_write(®s->imask, IMASK_MAG);
3629
3630
3631 tempval = gfar_read(®s->maccfg2);
3632 tempval |= MACCFG2_MPEN;
3633 gfar_write(®s->maccfg2, tempval);
3634
3635
3636 tempval = gfar_read(®s->maccfg1);
3637 tempval |= MACCFG1_RX_EN;
3638 gfar_write(®s->maccfg1, tempval);
3639
3640 } else if (wol & GFAR_WOL_FILER_UCAST) {
3641 gfar_filer_config_wol(priv);
3642 gfar_start_wol_filer(priv);
3643
3644 } else {
3645 phy_stop(ndev->phydev);
3646 }
3647
3648 return 0;
3649}
3650
3651static int gfar_resume(struct device *dev)
3652{
3653 struct gfar_private *priv = dev_get_drvdata(dev);
3654 struct net_device *ndev = priv->ndev;
3655 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3656 u32 tempval;
3657 u16 wol = priv->wol_opts;
3658
3659 if (!netif_running(ndev))
3660 return 0;
3661
3662 if (wol & GFAR_WOL_MAGIC) {
3663
3664 tempval = gfar_read(®s->maccfg2);
3665 tempval &= ~MACCFG2_MPEN;
3666 gfar_write(®s->maccfg2, tempval);
3667
3668 } else if (wol & GFAR_WOL_FILER_UCAST) {
3669
3670 gfar_halt(priv);
3671 gfar_filer_restore_table(priv);
3672
3673 } else {
3674 phy_start(ndev->phydev);
3675 }
3676
3677 gfar_start(priv);
3678
3679 netif_device_attach(ndev);
3680 enable_napi(priv);
3681
3682 return 0;
3683}
3684
3685static int gfar_restore(struct device *dev)
3686{
3687 struct gfar_private *priv = dev_get_drvdata(dev);
3688 struct net_device *ndev = priv->ndev;
3689
3690 if (!netif_running(ndev)) {
3691 netif_device_attach(ndev);
3692
3693 return 0;
3694 }
3695
3696 gfar_init_bds(ndev);
3697
3698 gfar_mac_reset(priv);
3699
3700 gfar_init_tx_rx_base(priv);
3701
3702 gfar_start(priv);
3703
3704 priv->oldlink = 0;
3705 priv->oldspeed = 0;
3706 priv->oldduplex = -1;
3707
3708 if (ndev->phydev)
3709 phy_start(ndev->phydev);
3710
3711 netif_device_attach(ndev);
3712 enable_napi(priv);
3713
3714 return 0;
3715}
3716
3717static const struct dev_pm_ops gfar_pm_ops = {
3718 .suspend = gfar_suspend,
3719 .resume = gfar_resume,
3720 .freeze = gfar_suspend,
3721 .thaw = gfar_resume,
3722 .restore = gfar_restore,
3723};
3724
3725#define GFAR_PM_OPS (&gfar_pm_ops)
3726
3727#else
3728
3729#define GFAR_PM_OPS NULL
3730
3731#endif
3732
3733static const struct of_device_id gfar_match[] =
3734{
3735 {
3736 .type = "network",
3737 .compatible = "gianfar",
3738 },
3739 {
3740 .compatible = "fsl,etsec2",
3741 },
3742 {},
3743};
3744MODULE_DEVICE_TABLE(of, gfar_match);
3745
3746
3747static struct platform_driver gfar_driver = {
3748 .driver = {
3749 .name = "fsl-gianfar",
3750 .pm = GFAR_PM_OPS,
3751 .of_match_table = gfar_match,
3752 },
3753 .probe = gfar_probe,
3754 .remove = gfar_remove,
3755};
3756
3757module_platform_driver(gfar_driver);
3758