1
2
3
4#include <linux/etherdevice.h>
5#include <linux/iopoll.h>
6#include <net/rtnetlink.h>
7#include "hclgevf_cmd.h"
8#include "hclgevf_main.h"
9#include "hclge_mbx.h"
10#include "hnae3.h"
11
12#define HCLGEVF_NAME "hclgevf"
13
14#define HCLGEVF_RESET_MAX_FAIL_CNT 5
15
16static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
17static struct hnae3_ae_algo ae_algovf;
18
19static struct workqueue_struct *hclgevf_wq;
20
21static const struct pci_device_id ae_algovf_pci_tbl[] = {
22 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
23 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
24
25 {0, }
26};
27
28static const u8 hclgevf_hash_key[] = {
29 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
30 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
31 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
32 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
33 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
34};
35
36MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
37
38static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
39 HCLGEVF_CMDQ_TX_ADDR_H_REG,
40 HCLGEVF_CMDQ_TX_DEPTH_REG,
41 HCLGEVF_CMDQ_TX_TAIL_REG,
42 HCLGEVF_CMDQ_TX_HEAD_REG,
43 HCLGEVF_CMDQ_RX_ADDR_L_REG,
44 HCLGEVF_CMDQ_RX_ADDR_H_REG,
45 HCLGEVF_CMDQ_RX_DEPTH_REG,
46 HCLGEVF_CMDQ_RX_TAIL_REG,
47 HCLGEVF_CMDQ_RX_HEAD_REG,
48 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
49 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
50 HCLGEVF_CMDQ_INTR_EN_REG,
51 HCLGEVF_CMDQ_INTR_GEN_REG};
52
53static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
54 HCLGEVF_RST_ING,
55 HCLGEVF_GRO_EN_REG};
56
57static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
58 HCLGEVF_RING_RX_ADDR_H_REG,
59 HCLGEVF_RING_RX_BD_NUM_REG,
60 HCLGEVF_RING_RX_BD_LENGTH_REG,
61 HCLGEVF_RING_RX_MERGE_EN_REG,
62 HCLGEVF_RING_RX_TAIL_REG,
63 HCLGEVF_RING_RX_HEAD_REG,
64 HCLGEVF_RING_RX_FBD_NUM_REG,
65 HCLGEVF_RING_RX_OFFSET_REG,
66 HCLGEVF_RING_RX_FBD_OFFSET_REG,
67 HCLGEVF_RING_RX_STASH_REG,
68 HCLGEVF_RING_RX_BD_ERR_REG,
69 HCLGEVF_RING_TX_ADDR_L_REG,
70 HCLGEVF_RING_TX_ADDR_H_REG,
71 HCLGEVF_RING_TX_BD_NUM_REG,
72 HCLGEVF_RING_TX_PRIORITY_REG,
73 HCLGEVF_RING_TX_TC_REG,
74 HCLGEVF_RING_TX_MERGE_EN_REG,
75 HCLGEVF_RING_TX_TAIL_REG,
76 HCLGEVF_RING_TX_HEAD_REG,
77 HCLGEVF_RING_TX_FBD_NUM_REG,
78 HCLGEVF_RING_TX_OFFSET_REG,
79 HCLGEVF_RING_TX_EBD_NUM_REG,
80 HCLGEVF_RING_TX_EBD_OFFSET_REG,
81 HCLGEVF_RING_TX_BD_ERR_REG,
82 HCLGEVF_RING_EN_REG};
83
84static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
85 HCLGEVF_TQP_INTR_GL0_REG,
86 HCLGEVF_TQP_INTR_GL1_REG,
87 HCLGEVF_TQP_INTR_GL2_REG,
88 HCLGEVF_TQP_INTR_RL_REG};
89
90static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
91{
92 if (!handle->client)
93 return container_of(handle, struct hclgevf_dev, nic);
94 else if (handle->client->type == HNAE3_CLIENT_ROCE)
95 return container_of(handle, struct hclgevf_dev, roce);
96 else
97 return container_of(handle, struct hclgevf_dev, nic);
98}
99
100static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
101{
102 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
103 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
104 struct hclgevf_desc desc;
105 struct hclgevf_tqp *tqp;
106 int status;
107 int i;
108
109 for (i = 0; i < kinfo->num_tqps; i++) {
110 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
111 hclgevf_cmd_setup_basic_desc(&desc,
112 HCLGEVF_OPC_QUERY_RX_STATUS,
113 true);
114
115 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
116 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
117 if (status) {
118 dev_err(&hdev->pdev->dev,
119 "Query tqp stat fail, status = %d,queue = %d\n",
120 status, i);
121 return status;
122 }
123 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
124 le32_to_cpu(desc.data[1]);
125
126 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
127 true);
128
129 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
130 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
131 if (status) {
132 dev_err(&hdev->pdev->dev,
133 "Query tqp stat fail, status = %d,queue = %d\n",
134 status, i);
135 return status;
136 }
137 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
138 le32_to_cpu(desc.data[1]);
139 }
140
141 return 0;
142}
143
144static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
145{
146 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
147 struct hclgevf_tqp *tqp;
148 u64 *buff = data;
149 int i;
150
151 for (i = 0; i < kinfo->num_tqps; i++) {
152 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
153 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
154 }
155 for (i = 0; i < kinfo->num_tqps; i++) {
156 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
157 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
158 }
159
160 return buff;
161}
162
163static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
164{
165 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
166
167 return kinfo->num_tqps * 2;
168}
169
170static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
171{
172 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
173 u8 *buff = data;
174 int i = 0;
175
176 for (i = 0; i < kinfo->num_tqps; i++) {
177 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
178 struct hclgevf_tqp, q);
179 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
180 tqp->index);
181 buff += ETH_GSTRING_LEN;
182 }
183
184 for (i = 0; i < kinfo->num_tqps; i++) {
185 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
186 struct hclgevf_tqp, q);
187 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
188 tqp->index);
189 buff += ETH_GSTRING_LEN;
190 }
191
192 return buff;
193}
194
195static void hclgevf_update_stats(struct hnae3_handle *handle,
196 struct net_device_stats *net_stats)
197{
198 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
199 int status;
200
201 status = hclgevf_tqps_update_stats(handle);
202 if (status)
203 dev_err(&hdev->pdev->dev,
204 "VF update of TQPS stats fail, status = %d.\n",
205 status);
206}
207
208static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
209{
210 if (strset == ETH_SS_TEST)
211 return -EOPNOTSUPP;
212 else if (strset == ETH_SS_STATS)
213 return hclgevf_tqps_get_sset_count(handle, strset);
214
215 return 0;
216}
217
218static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
219 u8 *data)
220{
221 u8 *p = (char *)data;
222
223 if (strset == ETH_SS_STATS)
224 p = hclgevf_tqps_get_strings(handle, p);
225}
226
227static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
228{
229 hclgevf_tqps_get_stats(handle, data);
230}
231
232static void hclgevf_build_send_msg(struct hclge_vf_to_pf_msg *msg, u8 code,
233 u8 subcode)
234{
235 if (msg) {
236 memset(msg, 0, sizeof(struct hclge_vf_to_pf_msg));
237 msg->code = code;
238 msg->subcode = subcode;
239 }
240}
241
242static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
243{
244 struct hclge_vf_to_pf_msg send_msg;
245 u8 resp_msg;
246 int status;
247
248 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_TCINFO, 0);
249 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
250 sizeof(resp_msg));
251 if (status) {
252 dev_err(&hdev->pdev->dev,
253 "VF request to get TC info from PF failed %d",
254 status);
255 return status;
256 }
257
258 hdev->hw_tc_map = resp_msg;
259
260 return 0;
261}
262
263static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
264{
265 struct hnae3_handle *nic = &hdev->nic;
266 struct hclge_vf_to_pf_msg send_msg;
267 u8 resp_msg;
268 int ret;
269
270 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
271 HCLGE_MBX_GET_PORT_BASE_VLAN_STATE);
272 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
273 sizeof(u8));
274 if (ret) {
275 dev_err(&hdev->pdev->dev,
276 "VF request to get port based vlan state failed %d",
277 ret);
278 return ret;
279 }
280
281 nic->port_base_vlan_state = resp_msg;
282
283 return 0;
284}
285
286static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
287{
288#define HCLGEVF_TQPS_RSS_INFO_LEN 6
289#define HCLGEVF_TQPS_ALLOC_OFFSET 0
290#define HCLGEVF_TQPS_RSS_SIZE_OFFSET 2
291#define HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET 4
292
293 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
294 struct hclge_vf_to_pf_msg send_msg;
295 int status;
296
297 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QINFO, 0);
298 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
299 HCLGEVF_TQPS_RSS_INFO_LEN);
300 if (status) {
301 dev_err(&hdev->pdev->dev,
302 "VF request to get tqp info from PF failed %d",
303 status);
304 return status;
305 }
306
307 memcpy(&hdev->num_tqps, &resp_msg[HCLGEVF_TQPS_ALLOC_OFFSET],
308 sizeof(u16));
309 memcpy(&hdev->rss_size_max, &resp_msg[HCLGEVF_TQPS_RSS_SIZE_OFFSET],
310 sizeof(u16));
311 memcpy(&hdev->rx_buf_len, &resp_msg[HCLGEVF_TQPS_RX_BUFFER_LEN_OFFSET],
312 sizeof(u16));
313
314 return 0;
315}
316
317static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
318{
319#define HCLGEVF_TQPS_DEPTH_INFO_LEN 4
320#define HCLGEVF_TQPS_NUM_TX_DESC_OFFSET 0
321#define HCLGEVF_TQPS_NUM_RX_DESC_OFFSET 2
322
323 u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
324 struct hclge_vf_to_pf_msg send_msg;
325 int ret;
326
327 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QDEPTH, 0);
328 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
329 HCLGEVF_TQPS_DEPTH_INFO_LEN);
330 if (ret) {
331 dev_err(&hdev->pdev->dev,
332 "VF request to get tqp depth info from PF failed %d",
333 ret);
334 return ret;
335 }
336
337 memcpy(&hdev->num_tx_desc, &resp_msg[HCLGEVF_TQPS_NUM_TX_DESC_OFFSET],
338 sizeof(u16));
339 memcpy(&hdev->num_rx_desc, &resp_msg[HCLGEVF_TQPS_NUM_RX_DESC_OFFSET],
340 sizeof(u16));
341
342 return 0;
343}
344
345static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
346{
347 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
348 struct hclge_vf_to_pf_msg send_msg;
349 u16 qid_in_pf = 0;
350 u8 resp_data[2];
351 int ret;
352
353 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_QID_IN_PF, 0);
354 memcpy(send_msg.data, &queue_id, sizeof(queue_id));
355 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_data,
356 sizeof(resp_data));
357 if (!ret)
358 qid_in_pf = *(u16 *)resp_data;
359
360 return qid_in_pf;
361}
362
363static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
364{
365 struct hclge_vf_to_pf_msg send_msg;
366 u8 resp_msg[2];
367 int ret;
368
369 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MEDIA_TYPE, 0);
370 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
371 sizeof(resp_msg));
372 if (ret) {
373 dev_err(&hdev->pdev->dev,
374 "VF request to get the pf port media type failed %d",
375 ret);
376 return ret;
377 }
378
379 hdev->hw.mac.media_type = resp_msg[0];
380 hdev->hw.mac.module_type = resp_msg[1];
381
382 return 0;
383}
384
385static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
386{
387 struct hclgevf_tqp *tqp;
388 int i;
389
390 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
391 sizeof(struct hclgevf_tqp), GFP_KERNEL);
392 if (!hdev->htqp)
393 return -ENOMEM;
394
395 tqp = hdev->htqp;
396
397 for (i = 0; i < hdev->num_tqps; i++) {
398 tqp->dev = &hdev->pdev->dev;
399 tqp->index = i;
400
401 tqp->q.ae_algo = &ae_algovf;
402 tqp->q.buf_size = hdev->rx_buf_len;
403 tqp->q.tx_desc_num = hdev->num_tx_desc;
404 tqp->q.rx_desc_num = hdev->num_rx_desc;
405 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
406 i * HCLGEVF_TQP_REG_SIZE;
407
408 tqp++;
409 }
410
411 return 0;
412}
413
414static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
415{
416 struct hnae3_handle *nic = &hdev->nic;
417 struct hnae3_knic_private_info *kinfo;
418 u16 new_tqps = hdev->num_tqps;
419 unsigned int i;
420
421 kinfo = &nic->kinfo;
422 kinfo->num_tc = 0;
423 kinfo->num_tx_desc = hdev->num_tx_desc;
424 kinfo->num_rx_desc = hdev->num_rx_desc;
425 kinfo->rx_buf_len = hdev->rx_buf_len;
426 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
427 if (hdev->hw_tc_map & BIT(i))
428 kinfo->num_tc++;
429
430 kinfo->rss_size
431 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
432 new_tqps = kinfo->rss_size * kinfo->num_tc;
433 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
434
435 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
436 sizeof(struct hnae3_queue *), GFP_KERNEL);
437 if (!kinfo->tqp)
438 return -ENOMEM;
439
440 for (i = 0; i < kinfo->num_tqps; i++) {
441 hdev->htqp[i].q.handle = &hdev->nic;
442 hdev->htqp[i].q.tqp_index = i;
443 kinfo->tqp[i] = &hdev->htqp[i].q;
444 }
445
446
447
448
449 kinfo->num_tqps = min_t(u16, hdev->num_nic_msix - 1, kinfo->num_tqps);
450 kinfo->rss_size = min_t(u16, kinfo->num_tqps / kinfo->num_tc,
451 kinfo->rss_size);
452
453 return 0;
454}
455
456static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
457{
458 struct hclge_vf_to_pf_msg send_msg;
459 int status;
460
461 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_STATUS, 0);
462 status = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
463 if (status)
464 dev_err(&hdev->pdev->dev,
465 "VF failed to fetch link status(%d) from PF", status);
466}
467
468void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
469{
470 struct hnae3_handle *rhandle = &hdev->roce;
471 struct hnae3_handle *handle = &hdev->nic;
472 struct hnae3_client *rclient;
473 struct hnae3_client *client;
474
475 if (test_and_set_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state))
476 return;
477
478 client = handle->client;
479 rclient = hdev->roce_client;
480
481 link_state =
482 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
483
484 if (link_state != hdev->hw.mac.link) {
485 client->ops->link_status_change(handle, !!link_state);
486 if (rclient && rclient->ops->link_status_change)
487 rclient->ops->link_status_change(rhandle, !!link_state);
488 hdev->hw.mac.link = link_state;
489 }
490
491 clear_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state);
492}
493
494static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
495{
496#define HCLGEVF_ADVERTISING 0
497#define HCLGEVF_SUPPORTED 1
498
499 struct hclge_vf_to_pf_msg send_msg;
500
501 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_LINK_MODE, 0);
502 send_msg.data[0] = HCLGEVF_ADVERTISING;
503 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
504 send_msg.data[0] = HCLGEVF_SUPPORTED;
505 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
506}
507
508static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
509{
510 struct hnae3_handle *nic = &hdev->nic;
511 int ret;
512
513 nic->ae_algo = &ae_algovf;
514 nic->pdev = hdev->pdev;
515 nic->numa_node_mask = hdev->numa_node_mask;
516 nic->flags |= HNAE3_SUPPORT_VF;
517
518 ret = hclgevf_knic_setup(hdev);
519 if (ret)
520 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
521 ret);
522 return ret;
523}
524
525static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
526{
527 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
528 dev_warn(&hdev->pdev->dev,
529 "vector(vector_id %d) has been freed.\n", vector_id);
530 return;
531 }
532
533 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
534 hdev->num_msi_left += 1;
535 hdev->num_msi_used -= 1;
536}
537
538static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
539 struct hnae3_vector_info *vector_info)
540{
541 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
542 struct hnae3_vector_info *vector = vector_info;
543 int alloc = 0;
544 int i, j;
545
546 vector_num = min_t(u16, hdev->num_nic_msix - 1, vector_num);
547 vector_num = min(hdev->num_msi_left, vector_num);
548
549 for (j = 0; j < vector_num; j++) {
550 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
551 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
552 vector->vector = pci_irq_vector(hdev->pdev, i);
553 vector->io_addr = hdev->hw.io_base +
554 HCLGEVF_VECTOR_REG_BASE +
555 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
556 hdev->vector_status[i] = 0;
557 hdev->vector_irq[i] = vector->vector;
558
559 vector++;
560 alloc++;
561
562 break;
563 }
564 }
565 }
566 hdev->num_msi_left -= alloc;
567 hdev->num_msi_used += alloc;
568
569 return alloc;
570}
571
572static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
573{
574 int i;
575
576 for (i = 0; i < hdev->num_msi; i++)
577 if (vector == hdev->vector_irq[i])
578 return i;
579
580 return -EINVAL;
581}
582
583static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
584 const u8 hfunc, const u8 *key)
585{
586 struct hclgevf_rss_config_cmd *req;
587 unsigned int key_offset = 0;
588 struct hclgevf_desc desc;
589 int key_counts;
590 int key_size;
591 int ret;
592
593 key_counts = HCLGEVF_RSS_KEY_SIZE;
594 req = (struct hclgevf_rss_config_cmd *)desc.data;
595
596 while (key_counts) {
597 hclgevf_cmd_setup_basic_desc(&desc,
598 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
599 false);
600
601 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
602 req->hash_config |=
603 (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
604
605 key_size = min(HCLGEVF_RSS_HASH_KEY_NUM, key_counts);
606 memcpy(req->hash_key,
607 key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
608
609 key_counts -= key_size;
610 key_offset++;
611 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
612 if (ret) {
613 dev_err(&hdev->pdev->dev,
614 "Configure RSS config fail, status = %d\n",
615 ret);
616 return ret;
617 }
618 }
619
620 return 0;
621}
622
623static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
624{
625 return HCLGEVF_RSS_KEY_SIZE;
626}
627
628static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
629{
630 return HCLGEVF_RSS_IND_TBL_SIZE;
631}
632
633static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
634{
635 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
636 struct hclgevf_rss_indirection_table_cmd *req;
637 struct hclgevf_desc desc;
638 int status;
639 int i, j;
640
641 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
642
643 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
644 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
645 false);
646 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
647 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
648 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
649 req->rss_result[j] =
650 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
651
652 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
653 if (status) {
654 dev_err(&hdev->pdev->dev,
655 "VF failed(=%d) to set RSS indirection table\n",
656 status);
657 return status;
658 }
659 }
660
661 return 0;
662}
663
664static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
665{
666 struct hclgevf_rss_tc_mode_cmd *req;
667 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
668 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
669 u16 tc_size[HCLGEVF_MAX_TC_NUM];
670 struct hclgevf_desc desc;
671 u16 roundup_size;
672 unsigned int i;
673 int status;
674
675 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
676
677 roundup_size = roundup_pow_of_two(rss_size);
678 roundup_size = ilog2(roundup_size);
679
680 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
681 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
682 tc_size[i] = roundup_size;
683 tc_offset[i] = rss_size * i;
684 }
685
686 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
687 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
688 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
689 (tc_valid[i] & 0x1));
690 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
691 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
692 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
693 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
694 }
695 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
696 if (status)
697 dev_err(&hdev->pdev->dev,
698 "VF failed(=%d) to set rss tc mode\n", status);
699
700 return status;
701}
702
703
704static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
705{
706#define HCLGEVF_RSS_MBX_RESP_LEN 8
707 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
708 u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
709 struct hclge_vf_to_pf_msg send_msg;
710 u16 msg_num, hash_key_index;
711 u8 index;
712 int ret;
713
714 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_RSS_KEY, 0);
715 msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
716 HCLGEVF_RSS_MBX_RESP_LEN;
717 for (index = 0; index < msg_num; index++) {
718 send_msg.data[0] = index;
719 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, resp_msg,
720 HCLGEVF_RSS_MBX_RESP_LEN);
721 if (ret) {
722 dev_err(&hdev->pdev->dev,
723 "VF get rss hash key from PF failed, ret=%d",
724 ret);
725 return ret;
726 }
727
728 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
729 if (index == msg_num - 1)
730 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
731 &resp_msg[0],
732 HCLGEVF_RSS_KEY_SIZE - hash_key_index);
733 else
734 memcpy(&rss_cfg->rss_hash_key[hash_key_index],
735 &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
736 }
737
738 return 0;
739}
740
741static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
742 u8 *hfunc)
743{
744 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
745 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
746 int i, ret;
747
748 if (handle->pdev->revision >= 0x21) {
749
750 if (hfunc) {
751 switch (rss_cfg->hash_algo) {
752 case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
753 *hfunc = ETH_RSS_HASH_TOP;
754 break;
755 case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
756 *hfunc = ETH_RSS_HASH_XOR;
757 break;
758 default:
759 *hfunc = ETH_RSS_HASH_UNKNOWN;
760 break;
761 }
762 }
763
764
765 if (key)
766 memcpy(key, rss_cfg->rss_hash_key,
767 HCLGEVF_RSS_KEY_SIZE);
768 } else {
769 if (hfunc)
770 *hfunc = ETH_RSS_HASH_TOP;
771 if (key) {
772 ret = hclgevf_get_rss_hash_key(hdev);
773 if (ret)
774 return ret;
775 memcpy(key, rss_cfg->rss_hash_key,
776 HCLGEVF_RSS_KEY_SIZE);
777 }
778 }
779
780 if (indir)
781 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
782 indir[i] = rss_cfg->rss_indirection_tbl[i];
783
784 return 0;
785}
786
787static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
788 const u8 *key, const u8 hfunc)
789{
790 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
791 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
792 int ret, i;
793
794 if (handle->pdev->revision >= 0x21) {
795
796 if (key) {
797 switch (hfunc) {
798 case ETH_RSS_HASH_TOP:
799 rss_cfg->hash_algo =
800 HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
801 break;
802 case ETH_RSS_HASH_XOR:
803 rss_cfg->hash_algo =
804 HCLGEVF_RSS_HASH_ALGO_SIMPLE;
805 break;
806 case ETH_RSS_HASH_NO_CHANGE:
807 break;
808 default:
809 return -EINVAL;
810 }
811
812 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
813 key);
814 if (ret)
815 return ret;
816
817
818 memcpy(rss_cfg->rss_hash_key, key,
819 HCLGEVF_RSS_KEY_SIZE);
820 }
821 }
822
823
824 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
825 rss_cfg->rss_indirection_tbl[i] = indir[i];
826
827
828 return hclgevf_set_rss_indir_table(hdev);
829}
830
831static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
832{
833 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
834
835 if (nfc->data & RXH_L4_B_2_3)
836 hash_sets |= HCLGEVF_D_PORT_BIT;
837 else
838 hash_sets &= ~HCLGEVF_D_PORT_BIT;
839
840 if (nfc->data & RXH_IP_SRC)
841 hash_sets |= HCLGEVF_S_IP_BIT;
842 else
843 hash_sets &= ~HCLGEVF_S_IP_BIT;
844
845 if (nfc->data & RXH_IP_DST)
846 hash_sets |= HCLGEVF_D_IP_BIT;
847 else
848 hash_sets &= ~HCLGEVF_D_IP_BIT;
849
850 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
851 hash_sets |= HCLGEVF_V_TAG_BIT;
852
853 return hash_sets;
854}
855
856static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
857 struct ethtool_rxnfc *nfc)
858{
859 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
860 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
861 struct hclgevf_rss_input_tuple_cmd *req;
862 struct hclgevf_desc desc;
863 u8 tuple_sets;
864 int ret;
865
866 if (handle->pdev->revision == 0x20)
867 return -EOPNOTSUPP;
868
869 if (nfc->data &
870 ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
871 return -EINVAL;
872
873 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
874 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
875
876 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
877 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
878 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
879 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
880 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
881 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
882 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
883 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
884
885 tuple_sets = hclgevf_get_rss_hash_bits(nfc);
886 switch (nfc->flow_type) {
887 case TCP_V4_FLOW:
888 req->ipv4_tcp_en = tuple_sets;
889 break;
890 case TCP_V6_FLOW:
891 req->ipv6_tcp_en = tuple_sets;
892 break;
893 case UDP_V4_FLOW:
894 req->ipv4_udp_en = tuple_sets;
895 break;
896 case UDP_V6_FLOW:
897 req->ipv6_udp_en = tuple_sets;
898 break;
899 case SCTP_V4_FLOW:
900 req->ipv4_sctp_en = tuple_sets;
901 break;
902 case SCTP_V6_FLOW:
903 if ((nfc->data & RXH_L4_B_0_1) ||
904 (nfc->data & RXH_L4_B_2_3))
905 return -EINVAL;
906
907 req->ipv6_sctp_en = tuple_sets;
908 break;
909 case IPV4_FLOW:
910 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
911 break;
912 case IPV6_FLOW:
913 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
914 break;
915 default:
916 return -EINVAL;
917 }
918
919 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
920 if (ret) {
921 dev_err(&hdev->pdev->dev,
922 "Set rss tuple fail, status = %d\n", ret);
923 return ret;
924 }
925
926 rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
927 rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
928 rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
929 rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
930 rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
931 rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
932 rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
933 rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
934 return 0;
935}
936
937static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
938 struct ethtool_rxnfc *nfc)
939{
940 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
941 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
942 u8 tuple_sets;
943
944 if (handle->pdev->revision == 0x20)
945 return -EOPNOTSUPP;
946
947 nfc->data = 0;
948
949 switch (nfc->flow_type) {
950 case TCP_V4_FLOW:
951 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
952 break;
953 case UDP_V4_FLOW:
954 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
955 break;
956 case TCP_V6_FLOW:
957 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
958 break;
959 case UDP_V6_FLOW:
960 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
961 break;
962 case SCTP_V4_FLOW:
963 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
964 break;
965 case SCTP_V6_FLOW:
966 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
967 break;
968 case IPV4_FLOW:
969 case IPV6_FLOW:
970 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
971 break;
972 default:
973 return -EINVAL;
974 }
975
976 if (!tuple_sets)
977 return 0;
978
979 if (tuple_sets & HCLGEVF_D_PORT_BIT)
980 nfc->data |= RXH_L4_B_2_3;
981 if (tuple_sets & HCLGEVF_S_PORT_BIT)
982 nfc->data |= RXH_L4_B_0_1;
983 if (tuple_sets & HCLGEVF_D_IP_BIT)
984 nfc->data |= RXH_IP_DST;
985 if (tuple_sets & HCLGEVF_S_IP_BIT)
986 nfc->data |= RXH_IP_SRC;
987
988 return 0;
989}
990
991static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
992 struct hclgevf_rss_cfg *rss_cfg)
993{
994 struct hclgevf_rss_input_tuple_cmd *req;
995 struct hclgevf_desc desc;
996 int ret;
997
998 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
999
1000 req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
1001
1002 req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
1003 req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
1004 req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
1005 req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
1006 req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
1007 req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
1008 req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
1009 req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
1010
1011 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1012 if (ret)
1013 dev_err(&hdev->pdev->dev,
1014 "Configure rss input fail, status = %d\n", ret);
1015 return ret;
1016}
1017
1018static int hclgevf_get_tc_size(struct hnae3_handle *handle)
1019{
1020 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1021 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1022
1023 return rss_cfg->rss_size;
1024}
1025
1026static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
1027 int vector_id,
1028 struct hnae3_ring_chain_node *ring_chain)
1029{
1030 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1031 struct hclge_vf_to_pf_msg send_msg;
1032 struct hnae3_ring_chain_node *node;
1033 int status;
1034 int i = 0;
1035
1036 memset(&send_msg, 0, sizeof(send_msg));
1037 send_msg.code = en ? HCLGE_MBX_MAP_RING_TO_VECTOR :
1038 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1039 send_msg.vector_id = vector_id;
1040
1041 for (node = ring_chain; node; node = node->next) {
1042 send_msg.param[i].ring_type =
1043 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1044
1045 send_msg.param[i].tqp_index = node->tqp_index;
1046 send_msg.param[i].int_gl_index =
1047 hnae3_get_field(node->int_gl_idx,
1048 HNAE3_RING_GL_IDX_M,
1049 HNAE3_RING_GL_IDX_S);
1050
1051 i++;
1052 if (i == HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM || !node->next) {
1053 send_msg.ring_num = i;
1054
1055 status = hclgevf_send_mbx_msg(hdev, &send_msg, false,
1056 NULL, 0);
1057 if (status) {
1058 dev_err(&hdev->pdev->dev,
1059 "Map TQP fail, status is %d.\n",
1060 status);
1061 return status;
1062 }
1063 i = 0;
1064 }
1065 }
1066
1067 return 0;
1068}
1069
1070static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1071 struct hnae3_ring_chain_node *ring_chain)
1072{
1073 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1074 int vector_id;
1075
1076 vector_id = hclgevf_get_vector_index(hdev, vector);
1077 if (vector_id < 0) {
1078 dev_err(&handle->pdev->dev,
1079 "Get vector index fail. ret =%d\n", vector_id);
1080 return vector_id;
1081 }
1082
1083 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1084}
1085
1086static int hclgevf_unmap_ring_from_vector(
1087 struct hnae3_handle *handle,
1088 int vector,
1089 struct hnae3_ring_chain_node *ring_chain)
1090{
1091 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1092 int ret, vector_id;
1093
1094 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1095 return 0;
1096
1097 vector_id = hclgevf_get_vector_index(hdev, vector);
1098 if (vector_id < 0) {
1099 dev_err(&handle->pdev->dev,
1100 "Get vector index fail. ret =%d\n", vector_id);
1101 return vector_id;
1102 }
1103
1104 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1105 if (ret)
1106 dev_err(&handle->pdev->dev,
1107 "Unmap ring from vector fail. vector=%d, ret =%d\n",
1108 vector_id,
1109 ret);
1110
1111 return ret;
1112}
1113
1114static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1115{
1116 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1117 int vector_id;
1118
1119 vector_id = hclgevf_get_vector_index(hdev, vector);
1120 if (vector_id < 0) {
1121 dev_err(&handle->pdev->dev,
1122 "hclgevf_put_vector get vector index fail. ret =%d\n",
1123 vector_id);
1124 return vector_id;
1125 }
1126
1127 hclgevf_free_vector(hdev, vector_id);
1128
1129 return 0;
1130}
1131
1132static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1133 bool en_uc_pmc, bool en_mc_pmc,
1134 bool en_bc_pmc)
1135{
1136 struct hclge_vf_to_pf_msg send_msg;
1137 int ret;
1138
1139 memset(&send_msg, 0, sizeof(send_msg));
1140 send_msg.code = HCLGE_MBX_SET_PROMISC_MODE;
1141 send_msg.en_bc = en_bc_pmc ? 1 : 0;
1142 send_msg.en_uc = en_uc_pmc ? 1 : 0;
1143 send_msg.en_mc = en_mc_pmc ? 1 : 0;
1144
1145 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1146 if (ret)
1147 dev_err(&hdev->pdev->dev,
1148 "Set promisc mode fail, status is %d.\n", ret);
1149
1150 return ret;
1151}
1152
1153static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
1154 bool en_mc_pmc)
1155{
1156 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1157 struct pci_dev *pdev = hdev->pdev;
1158 bool en_bc_pmc;
1159
1160 en_bc_pmc = pdev->revision != 0x20;
1161
1162 return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
1163 en_bc_pmc);
1164}
1165
1166static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
1167{
1168 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1169
1170 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1171}
1172
1173static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
1174{
1175 struct hnae3_handle *handle = &hdev->nic;
1176 bool en_uc_pmc = handle->netdev_flags & HNAE3_UPE;
1177 bool en_mc_pmc = handle->netdev_flags & HNAE3_MPE;
1178 int ret;
1179
1180 if (test_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state)) {
1181 ret = hclgevf_set_promisc_mode(handle, en_uc_pmc, en_mc_pmc);
1182 if (!ret)
1183 clear_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
1184 }
1185}
1186
1187static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, unsigned int tqp_id,
1188 int stream_id, bool enable)
1189{
1190 struct hclgevf_cfg_com_tqp_queue_cmd *req;
1191 struct hclgevf_desc desc;
1192 int status;
1193
1194 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1195
1196 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1197 false);
1198 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1199 req->stream_id = cpu_to_le16(stream_id);
1200 if (enable)
1201 req->enable |= 1U << HCLGEVF_TQP_ENABLE_B;
1202
1203 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1204 if (status)
1205 dev_err(&hdev->pdev->dev,
1206 "TQP enable fail, status =%d.\n", status);
1207
1208 return status;
1209}
1210
1211static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1212{
1213 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1214 struct hclgevf_tqp *tqp;
1215 int i;
1216
1217 for (i = 0; i < kinfo->num_tqps; i++) {
1218 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1219 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1220 }
1221}
1222
1223static int hclgevf_get_host_mac_addr(struct hclgevf_dev *hdev, u8 *p)
1224{
1225 struct hclge_vf_to_pf_msg send_msg;
1226 u8 host_mac[ETH_ALEN];
1227 int status;
1228
1229 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_GET_MAC_ADDR, 0);
1230 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, host_mac,
1231 ETH_ALEN);
1232 if (status) {
1233 dev_err(&hdev->pdev->dev,
1234 "fail to get VF MAC from host %d", status);
1235 return status;
1236 }
1237
1238 ether_addr_copy(p, host_mac);
1239
1240 return 0;
1241}
1242
1243static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1244{
1245 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1246 u8 host_mac_addr[ETH_ALEN];
1247
1248 if (hclgevf_get_host_mac_addr(hdev, host_mac_addr))
1249 return;
1250
1251 hdev->has_pf_mac = !is_zero_ether_addr(host_mac_addr);
1252 if (hdev->has_pf_mac)
1253 ether_addr_copy(p, host_mac_addr);
1254 else
1255 ether_addr_copy(p, hdev->hw.mac.mac_addr);
1256}
1257
1258static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1259 bool is_first)
1260{
1261 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1262 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1263 struct hclge_vf_to_pf_msg send_msg;
1264 u8 *new_mac_addr = (u8 *)p;
1265 int status;
1266
1267 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_UNICAST, 0);
1268 send_msg.subcode = HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1269 ether_addr_copy(send_msg.data, new_mac_addr);
1270 if (is_first && !hdev->has_pf_mac)
1271 eth_zero_addr(&send_msg.data[ETH_ALEN]);
1272 else
1273 ether_addr_copy(&send_msg.data[ETH_ALEN], old_mac_addr);
1274 status = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1275 if (!status)
1276 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1277
1278 return status;
1279}
1280
1281static struct hclgevf_mac_addr_node *
1282hclgevf_find_mac_node(struct list_head *list, const u8 *mac_addr)
1283{
1284 struct hclgevf_mac_addr_node *mac_node, *tmp;
1285
1286 list_for_each_entry_safe(mac_node, tmp, list, node)
1287 if (ether_addr_equal(mac_addr, mac_node->mac_addr))
1288 return mac_node;
1289
1290 return NULL;
1291}
1292
1293static void hclgevf_update_mac_node(struct hclgevf_mac_addr_node *mac_node,
1294 enum HCLGEVF_MAC_NODE_STATE state)
1295{
1296 switch (state) {
1297
1298 case HCLGEVF_MAC_TO_ADD:
1299 if (mac_node->state == HCLGEVF_MAC_TO_DEL)
1300 mac_node->state = HCLGEVF_MAC_ACTIVE;
1301 break;
1302
1303 case HCLGEVF_MAC_TO_DEL:
1304 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1305 list_del(&mac_node->node);
1306 kfree(mac_node);
1307 } else {
1308 mac_node->state = HCLGEVF_MAC_TO_DEL;
1309 }
1310 break;
1311
1312
1313
1314 case HCLGEVF_MAC_ACTIVE:
1315 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1316 mac_node->state = HCLGEVF_MAC_ACTIVE;
1317 break;
1318 }
1319}
1320
1321static int hclgevf_update_mac_list(struct hnae3_handle *handle,
1322 enum HCLGEVF_MAC_NODE_STATE state,
1323 enum HCLGEVF_MAC_ADDR_TYPE mac_type,
1324 const unsigned char *addr)
1325{
1326 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1327 struct hclgevf_mac_addr_node *mac_node;
1328 struct list_head *list;
1329
1330 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1331 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1332
1333 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1334
1335
1336
1337
1338
1339 mac_node = hclgevf_find_mac_node(list, addr);
1340 if (mac_node) {
1341 hclgevf_update_mac_node(mac_node, state);
1342 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1343 return 0;
1344 }
1345
1346 if (state == HCLGEVF_MAC_TO_DEL) {
1347 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1348 return -ENOENT;
1349 }
1350
1351 mac_node = kzalloc(sizeof(*mac_node), GFP_ATOMIC);
1352 if (!mac_node) {
1353 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1354 return -ENOMEM;
1355 }
1356
1357 mac_node->state = state;
1358 ether_addr_copy(mac_node->mac_addr, addr);
1359 list_add_tail(&mac_node->node, list);
1360
1361 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1362 return 0;
1363}
1364
1365static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1366 const unsigned char *addr)
1367{
1368 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1369 HCLGEVF_MAC_ADDR_UC, addr);
1370}
1371
1372static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1373 const unsigned char *addr)
1374{
1375 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1376 HCLGEVF_MAC_ADDR_UC, addr);
1377}
1378
1379static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1380 const unsigned char *addr)
1381{
1382 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_ADD,
1383 HCLGEVF_MAC_ADDR_MC, addr);
1384}
1385
1386static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1387 const unsigned char *addr)
1388{
1389 return hclgevf_update_mac_list(handle, HCLGEVF_MAC_TO_DEL,
1390 HCLGEVF_MAC_ADDR_MC, addr);
1391}
1392
1393static int hclgevf_add_del_mac_addr(struct hclgevf_dev *hdev,
1394 struct hclgevf_mac_addr_node *mac_node,
1395 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1396{
1397 struct hclge_vf_to_pf_msg send_msg;
1398 u8 code, subcode;
1399
1400 if (mac_type == HCLGEVF_MAC_ADDR_UC) {
1401 code = HCLGE_MBX_SET_UNICAST;
1402 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1403 subcode = HCLGE_MBX_MAC_VLAN_UC_ADD;
1404 else
1405 subcode = HCLGE_MBX_MAC_VLAN_UC_REMOVE;
1406 } else {
1407 code = HCLGE_MBX_SET_MULTICAST;
1408 if (mac_node->state == HCLGEVF_MAC_TO_ADD)
1409 subcode = HCLGE_MBX_MAC_VLAN_MC_ADD;
1410 else
1411 subcode = HCLGE_MBX_MAC_VLAN_MC_REMOVE;
1412 }
1413
1414 hclgevf_build_send_msg(&send_msg, code, subcode);
1415 ether_addr_copy(send_msg.data, mac_node->mac_addr);
1416 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1417}
1418
1419static void hclgevf_config_mac_list(struct hclgevf_dev *hdev,
1420 struct list_head *list,
1421 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1422{
1423 struct hclgevf_mac_addr_node *mac_node, *tmp;
1424 int ret;
1425
1426 list_for_each_entry_safe(mac_node, tmp, list, node) {
1427 ret = hclgevf_add_del_mac_addr(hdev, mac_node, mac_type);
1428 if (ret) {
1429 dev_err(&hdev->pdev->dev,
1430 "failed to configure mac %pM, state = %d, ret = %d\n",
1431 mac_node->mac_addr, mac_node->state, ret);
1432 return;
1433 }
1434 if (mac_node->state == HCLGEVF_MAC_TO_ADD) {
1435 mac_node->state = HCLGEVF_MAC_ACTIVE;
1436 } else {
1437 list_del(&mac_node->node);
1438 kfree(mac_node);
1439 }
1440 }
1441}
1442
1443static void hclgevf_sync_from_add_list(struct list_head *add_list,
1444 struct list_head *mac_list)
1445{
1446 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1447
1448 list_for_each_entry_safe(mac_node, tmp, add_list, node) {
1449
1450
1451
1452
1453
1454
1455
1456 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1457 if (new_node) {
1458 hclgevf_update_mac_node(new_node, mac_node->state);
1459 list_del(&mac_node->node);
1460 kfree(mac_node);
1461 } else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
1462 mac_node->state = HCLGEVF_MAC_TO_DEL;
1463 list_del(&mac_node->node);
1464 list_add_tail(&mac_node->node, mac_list);
1465 } else {
1466 list_del(&mac_node->node);
1467 kfree(mac_node);
1468 }
1469 }
1470}
1471
1472static void hclgevf_sync_from_del_list(struct list_head *del_list,
1473 struct list_head *mac_list)
1474{
1475 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1476
1477 list_for_each_entry_safe(mac_node, tmp, del_list, node) {
1478 new_node = hclgevf_find_mac_node(mac_list, mac_node->mac_addr);
1479 if (new_node) {
1480
1481
1482
1483
1484
1485 new_node->state = HCLGEVF_MAC_ACTIVE;
1486 list_del(&mac_node->node);
1487 kfree(mac_node);
1488 } else {
1489 list_del(&mac_node->node);
1490 list_add_tail(&mac_node->node, mac_list);
1491 }
1492 }
1493}
1494
1495static void hclgevf_clear_list(struct list_head *list)
1496{
1497 struct hclgevf_mac_addr_node *mac_node, *tmp;
1498
1499 list_for_each_entry_safe(mac_node, tmp, list, node) {
1500 list_del(&mac_node->node);
1501 kfree(mac_node);
1502 }
1503}
1504
1505static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
1506 enum HCLGEVF_MAC_ADDR_TYPE mac_type)
1507{
1508 struct hclgevf_mac_addr_node *mac_node, *tmp, *new_node;
1509 struct list_head tmp_add_list, tmp_del_list;
1510 struct list_head *list;
1511
1512 INIT_LIST_HEAD(&tmp_add_list);
1513 INIT_LIST_HEAD(&tmp_del_list);
1514
1515
1516
1517
1518 list = (mac_type == HCLGEVF_MAC_ADDR_UC) ?
1519 &hdev->mac_table.uc_mac_list : &hdev->mac_table.mc_mac_list;
1520
1521 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1522
1523 list_for_each_entry_safe(mac_node, tmp, list, node) {
1524 switch (mac_node->state) {
1525 case HCLGEVF_MAC_TO_DEL:
1526 list_del(&mac_node->node);
1527 list_add_tail(&mac_node->node, &tmp_del_list);
1528 break;
1529 case HCLGEVF_MAC_TO_ADD:
1530 new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
1531 if (!new_node)
1532 goto stop_traverse;
1533
1534 ether_addr_copy(new_node->mac_addr, mac_node->mac_addr);
1535 new_node->state = mac_node->state;
1536 list_add_tail(&new_node->node, &tmp_add_list);
1537 break;
1538 default:
1539 break;
1540 }
1541 }
1542
1543stop_traverse:
1544 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1545
1546
1547 hclgevf_config_mac_list(hdev, &tmp_del_list, mac_type);
1548 hclgevf_config_mac_list(hdev, &tmp_add_list, mac_type);
1549
1550
1551
1552
1553 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1554
1555 hclgevf_sync_from_del_list(&tmp_del_list, list);
1556 hclgevf_sync_from_add_list(&tmp_add_list, list);
1557
1558 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1559}
1560
1561static void hclgevf_sync_mac_table(struct hclgevf_dev *hdev)
1562{
1563 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_UC);
1564 hclgevf_sync_mac_list(hdev, HCLGEVF_MAC_ADDR_MC);
1565}
1566
1567static void hclgevf_uninit_mac_list(struct hclgevf_dev *hdev)
1568{
1569 spin_lock_bh(&hdev->mac_table.mac_list_lock);
1570
1571 hclgevf_clear_list(&hdev->mac_table.uc_mac_list);
1572 hclgevf_clear_list(&hdev->mac_table.mc_mac_list);
1573
1574 spin_unlock_bh(&hdev->mac_table.mac_list_lock);
1575}
1576
1577static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1578 __be16 proto, u16 vlan_id,
1579 bool is_kill)
1580{
1581#define HCLGEVF_VLAN_MBX_IS_KILL_OFFSET 0
1582#define HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET 1
1583#define HCLGEVF_VLAN_MBX_PROTO_OFFSET 3
1584
1585 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1586 struct hclge_vf_to_pf_msg send_msg;
1587 int ret;
1588
1589 if (vlan_id > HCLGEVF_MAX_VLAN_ID)
1590 return -EINVAL;
1591
1592 if (proto != htons(ETH_P_8021Q))
1593 return -EPROTONOSUPPORT;
1594
1595
1596
1597
1598
1599 if ((test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
1600 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) && is_kill) {
1601 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1602 return -EBUSY;
1603 }
1604
1605 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1606 HCLGE_MBX_VLAN_FILTER);
1607 send_msg.data[HCLGEVF_VLAN_MBX_IS_KILL_OFFSET] = is_kill;
1608 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_VLAN_ID_OFFSET], &vlan_id,
1609 sizeof(vlan_id));
1610 memcpy(&send_msg.data[HCLGEVF_VLAN_MBX_PROTO_OFFSET], &proto,
1611 sizeof(proto));
1612
1613
1614
1615
1616 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1617 if (is_kill && ret)
1618 set_bit(vlan_id, hdev->vlan_del_fail_bmap);
1619
1620 return ret;
1621}
1622
1623static void hclgevf_sync_vlan_filter(struct hclgevf_dev *hdev)
1624{
1625#define HCLGEVF_MAX_SYNC_COUNT 60
1626 struct hnae3_handle *handle = &hdev->nic;
1627 int ret, sync_cnt = 0;
1628 u16 vlan_id;
1629
1630 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1631 while (vlan_id != VLAN_N_VID) {
1632 ret = hclgevf_set_vlan_filter(handle, htons(ETH_P_8021Q),
1633 vlan_id, true);
1634 if (ret)
1635 return;
1636
1637 clear_bit(vlan_id, hdev->vlan_del_fail_bmap);
1638 sync_cnt++;
1639 if (sync_cnt >= HCLGEVF_MAX_SYNC_COUNT)
1640 return;
1641
1642 vlan_id = find_first_bit(hdev->vlan_del_fail_bmap, VLAN_N_VID);
1643 }
1644}
1645
1646static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1647{
1648 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1649 struct hclge_vf_to_pf_msg send_msg;
1650
1651 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
1652 HCLGE_MBX_VLAN_RX_OFF_CFG);
1653 send_msg.data[0] = enable ? 1 : 0;
1654 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
1655}
1656
1657static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1658{
1659 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1660 struct hclge_vf_to_pf_msg send_msg;
1661 int ret;
1662
1663
1664 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1665 if (ret)
1666 return ret;
1667
1668 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_QUEUE_RESET, 0);
1669 memcpy(send_msg.data, &queue_id, sizeof(queue_id));
1670 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1671}
1672
1673static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1674{
1675 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1676 struct hclge_vf_to_pf_msg send_msg;
1677
1678 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_MTU, 0);
1679 memcpy(send_msg.data, &new_mtu, sizeof(new_mtu));
1680 return hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1681}
1682
1683static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1684 enum hnae3_reset_notify_type type)
1685{
1686 struct hnae3_client *client = hdev->nic_client;
1687 struct hnae3_handle *handle = &hdev->nic;
1688 int ret;
1689
1690 if (!test_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state) ||
1691 !client)
1692 return 0;
1693
1694 if (!client->ops->reset_notify)
1695 return -EOPNOTSUPP;
1696
1697 ret = client->ops->reset_notify(handle, type);
1698 if (ret)
1699 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1700 type, ret);
1701
1702 return ret;
1703}
1704
1705static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1706{
1707#define HCLGEVF_RESET_WAIT_US 20000
1708#define HCLGEVF_RESET_WAIT_CNT 2000
1709#define HCLGEVF_RESET_WAIT_TIMEOUT_US \
1710 (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1711
1712 u32 val;
1713 int ret;
1714
1715 if (hdev->reset_type == HNAE3_VF_RESET)
1716 ret = readl_poll_timeout(hdev->hw.io_base +
1717 HCLGEVF_VF_RST_ING, val,
1718 !(val & HCLGEVF_VF_RST_ING_BIT),
1719 HCLGEVF_RESET_WAIT_US,
1720 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1721 else
1722 ret = readl_poll_timeout(hdev->hw.io_base +
1723 HCLGEVF_RST_ING, val,
1724 !(val & HCLGEVF_RST_ING_BITS),
1725 HCLGEVF_RESET_WAIT_US,
1726 HCLGEVF_RESET_WAIT_TIMEOUT_US);
1727
1728
1729 if (ret) {
1730 dev_err(&hdev->pdev->dev,
1731 "couldn't get reset done status from h/w, timeout!\n");
1732 return ret;
1733 }
1734
1735
1736
1737
1738
1739 msleep(5000);
1740
1741 return 0;
1742}
1743
1744static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
1745{
1746 u32 reg_val;
1747
1748 reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
1749 if (enable)
1750 reg_val |= HCLGEVF_NIC_SW_RST_RDY;
1751 else
1752 reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
1753
1754 hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
1755 reg_val);
1756}
1757
1758static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1759{
1760 int ret;
1761
1762
1763 ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1764 if (ret)
1765 return ret;
1766
1767
1768 ret = hclgevf_reset_hdev(hdev);
1769 if (ret) {
1770 dev_err(&hdev->pdev->dev,
1771 "hclge device re-init failed, VF is disabled!\n");
1772 return ret;
1773 }
1774
1775
1776 ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1777 if (ret)
1778 return ret;
1779
1780
1781 hclgevf_reset_handshake(hdev, false);
1782
1783
1784 return hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1785}
1786
1787static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1788{
1789#define HCLGEVF_RESET_SYNC_TIME 100
1790
1791 struct hclge_vf_to_pf_msg send_msg;
1792 int ret = 0;
1793
1794 if (hdev->reset_type == HNAE3_VF_FUNC_RESET) {
1795 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_RESET, 0);
1796 ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, NULL, 0);
1797 if (ret) {
1798 dev_err(&hdev->pdev->dev,
1799 "failed to assert VF reset, ret = %d\n", ret);
1800 return ret;
1801 }
1802 hdev->rst_stats.vf_func_rst_cnt++;
1803 }
1804
1805 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1806
1807 msleep(HCLGEVF_RESET_SYNC_TIME);
1808 hclgevf_reset_handshake(hdev, true);
1809 dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n",
1810 hdev->reset_type, ret);
1811
1812 return ret;
1813}
1814
1815static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
1816{
1817 dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
1818 hdev->rst_stats.vf_func_rst_cnt);
1819 dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1820 hdev->rst_stats.flr_rst_cnt);
1821 dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
1822 hdev->rst_stats.vf_rst_cnt);
1823 dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1824 hdev->rst_stats.rst_done_cnt);
1825 dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1826 hdev->rst_stats.hw_rst_done_cnt);
1827 dev_info(&hdev->pdev->dev, "reset count: %u\n",
1828 hdev->rst_stats.rst_cnt);
1829 dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1830 hdev->rst_stats.rst_fail_cnt);
1831 dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1832 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
1833 dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
1834 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
1835 dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1836 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
1837 dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1838 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
1839 dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1840}
1841
1842static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
1843{
1844
1845 hclgevf_reset_handshake(hdev, true);
1846 hdev->rst_stats.rst_fail_cnt++;
1847 dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
1848 hdev->rst_stats.rst_fail_cnt);
1849
1850 if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
1851 set_bit(hdev->reset_type, &hdev->reset_pending);
1852
1853 if (hclgevf_is_reset_pending(hdev)) {
1854 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1855 hclgevf_reset_task_schedule(hdev);
1856 } else {
1857 set_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1858 hclgevf_dump_rst_info(hdev);
1859 }
1860}
1861
1862static int hclgevf_reset_prepare(struct hclgevf_dev *hdev)
1863{
1864 int ret;
1865
1866 hdev->rst_stats.rst_cnt++;
1867
1868 rtnl_lock();
1869
1870 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1871 rtnl_unlock();
1872 if (ret)
1873 return ret;
1874
1875 return hclgevf_reset_prepare_wait(hdev);
1876}
1877
1878static int hclgevf_reset_rebuild(struct hclgevf_dev *hdev)
1879{
1880 int ret;
1881
1882 hdev->rst_stats.hw_rst_done_cnt++;
1883
1884 rtnl_lock();
1885
1886 ret = hclgevf_reset_stack(hdev);
1887 rtnl_unlock();
1888 if (ret) {
1889 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1890 return ret;
1891 }
1892
1893 hdev->last_reset_time = jiffies;
1894 hdev->rst_stats.rst_done_cnt++;
1895 hdev->rst_stats.rst_fail_cnt = 0;
1896 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
1897
1898 return 0;
1899}
1900
1901static void hclgevf_reset(struct hclgevf_dev *hdev)
1902{
1903 if (hclgevf_reset_prepare(hdev))
1904 goto err_reset;
1905
1906
1907
1908
1909 if (hclgevf_reset_wait(hdev)) {
1910
1911 dev_err(&hdev->pdev->dev,
1912 "failed to fetch H/W reset completion status\n");
1913 goto err_reset;
1914 }
1915
1916 if (hclgevf_reset_rebuild(hdev))
1917 goto err_reset;
1918
1919 return;
1920
1921err_reset:
1922 hclgevf_reset_err_handle(hdev);
1923}
1924
1925static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
1926 unsigned long *addr)
1927{
1928 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1929
1930
1931 if (test_bit(HNAE3_VF_RESET, addr)) {
1932 rst_level = HNAE3_VF_RESET;
1933 clear_bit(HNAE3_VF_RESET, addr);
1934 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1935 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1936 } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1937 rst_level = HNAE3_VF_FULL_RESET;
1938 clear_bit(HNAE3_VF_FULL_RESET, addr);
1939 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1940 } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1941 rst_level = HNAE3_VF_PF_FUNC_RESET;
1942 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1943 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1944 } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1945 rst_level = HNAE3_VF_FUNC_RESET;
1946 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1947 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
1948 rst_level = HNAE3_FLR_RESET;
1949 clear_bit(HNAE3_FLR_RESET, addr);
1950 }
1951
1952 return rst_level;
1953}
1954
1955static void hclgevf_reset_event(struct pci_dev *pdev,
1956 struct hnae3_handle *handle)
1957{
1958 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1959 struct hclgevf_dev *hdev = ae_dev->priv;
1960
1961 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1962
1963 if (hdev->default_reset_request)
1964 hdev->reset_level =
1965 hclgevf_get_reset_level(hdev,
1966 &hdev->default_reset_request);
1967 else
1968 hdev->reset_level = HNAE3_VF_FUNC_RESET;
1969
1970
1971 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1972 hclgevf_reset_task_schedule(hdev);
1973
1974 hdev->last_reset_time = jiffies;
1975}
1976
1977static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1978 enum hnae3_reset_type rst_type)
1979{
1980 struct hclgevf_dev *hdev = ae_dev->priv;
1981
1982 set_bit(rst_type, &hdev->default_reset_request);
1983}
1984
1985static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1986{
1987 writel(en ? 1 : 0, vector->addr);
1988}
1989
1990static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
1991{
1992#define HCLGEVF_FLR_RETRY_WAIT_MS 500
1993#define HCLGEVF_FLR_RETRY_CNT 5
1994
1995 struct hclgevf_dev *hdev = ae_dev->priv;
1996 int retry_cnt = 0;
1997 int ret;
1998
1999retry:
2000 down(&hdev->reset_sem);
2001 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2002 hdev->reset_type = HNAE3_FLR_RESET;
2003 ret = hclgevf_reset_prepare(hdev);
2004 if (ret) {
2005 dev_err(&hdev->pdev->dev, "fail to prepare FLR, ret=%d\n",
2006 ret);
2007 if (hdev->reset_pending ||
2008 retry_cnt++ < HCLGEVF_FLR_RETRY_CNT) {
2009 dev_err(&hdev->pdev->dev,
2010 "reset_pending:0x%lx, retry_cnt:%d\n",
2011 hdev->reset_pending, retry_cnt);
2012 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2013 up(&hdev->reset_sem);
2014 msleep(HCLGEVF_FLR_RETRY_WAIT_MS);
2015 goto retry;
2016 }
2017 }
2018
2019
2020 hclgevf_enable_vector(&hdev->misc_vector, false);
2021 hdev->rst_stats.flr_rst_cnt++;
2022}
2023
2024static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
2025{
2026 struct hclgevf_dev *hdev = ae_dev->priv;
2027 int ret;
2028
2029 hclgevf_enable_vector(&hdev->misc_vector, true);
2030
2031 ret = hclgevf_reset_rebuild(hdev);
2032 if (ret)
2033 dev_warn(&hdev->pdev->dev, "fail to rebuild, ret=%d\n",
2034 ret);
2035
2036 hdev->reset_type = HNAE3_NONE_RESET;
2037 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2038 up(&hdev->reset_sem);
2039}
2040
2041static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
2042{
2043 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2044
2045 return hdev->fw_version;
2046}
2047
2048static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
2049{
2050 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
2051
2052 vector->vector_irq = pci_irq_vector(hdev->pdev,
2053 HCLGEVF_MISC_VECTOR_NUM);
2054 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
2055
2056 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
2057 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
2058
2059 hdev->num_msi_left -= 1;
2060 hdev->num_msi_used += 1;
2061}
2062
2063void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
2064{
2065 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2066 !test_and_set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED,
2067 &hdev->state))
2068 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2069}
2070
2071void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
2072{
2073 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2074 !test_and_set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED,
2075 &hdev->state))
2076 mod_delayed_work(hclgevf_wq, &hdev->service_task, 0);
2077}
2078
2079static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
2080 unsigned long delay)
2081{
2082 if (!test_bit(HCLGEVF_STATE_REMOVING, &hdev->state) &&
2083 !test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state))
2084 mod_delayed_work(hclgevf_wq, &hdev->service_task, delay);
2085}
2086
2087static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
2088{
2089#define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
2090
2091 if (!test_and_clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state))
2092 return;
2093
2094 down(&hdev->reset_sem);
2095 set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2096
2097 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
2098 &hdev->reset_state)) {
2099
2100
2101
2102
2103
2104 hdev->reset_attempts = 0;
2105
2106 hdev->last_reset_time = jiffies;
2107 while ((hdev->reset_type =
2108 hclgevf_get_reset_level(hdev, &hdev->reset_pending))
2109 != HNAE3_NONE_RESET)
2110 hclgevf_reset(hdev);
2111 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
2112 &hdev->reset_state)) {
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136 if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
2137
2138 set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
2139
2140
2141 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2142 } else {
2143 hdev->reset_attempts++;
2144
2145 set_bit(hdev->reset_level, &hdev->reset_pending);
2146 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2147 }
2148 hclgevf_reset_task_schedule(hdev);
2149 }
2150
2151 hdev->reset_type = HNAE3_NONE_RESET;
2152 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2153 up(&hdev->reset_sem);
2154}
2155
2156static void hclgevf_mailbox_service_task(struct hclgevf_dev *hdev)
2157{
2158 if (!test_and_clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state))
2159 return;
2160
2161 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
2162 return;
2163
2164 hclgevf_mbx_async_handler(hdev);
2165
2166 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2167}
2168
2169static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
2170{
2171 struct hclge_vf_to_pf_msg send_msg;
2172 int ret;
2173
2174 if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
2175 return;
2176
2177 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
2178 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2179 if (ret)
2180 dev_err(&hdev->pdev->dev,
2181 "VF sends keep alive cmd failed(=%d)\n", ret);
2182}
2183
2184static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
2185{
2186 unsigned long delta = round_jiffies_relative(HZ);
2187 struct hnae3_handle *handle = &hdev->nic;
2188
2189 if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
2190 delta = jiffies - hdev->last_serv_processed;
2191
2192 if (delta < round_jiffies_relative(HZ)) {
2193 delta = round_jiffies_relative(HZ) - delta;
2194 goto out;
2195 }
2196 }
2197
2198 hdev->serv_processed_cnt++;
2199 if (!(hdev->serv_processed_cnt % HCLGEVF_KEEP_ALIVE_TASK_INTERVAL))
2200 hclgevf_keep_alive(hdev);
2201
2202 if (test_bit(HCLGEVF_STATE_DOWN, &hdev->state)) {
2203 hdev->last_serv_processed = jiffies;
2204 goto out;
2205 }
2206
2207 if (!(hdev->serv_processed_cnt % HCLGEVF_STATS_TIMER_INTERVAL))
2208 hclgevf_tqps_update_stats(handle);
2209
2210
2211
2212
2213 hclgevf_request_link_info(hdev);
2214
2215 hclgevf_update_link_mode(hdev);
2216
2217 hclgevf_sync_vlan_filter(hdev);
2218
2219 hclgevf_sync_mac_table(hdev);
2220
2221 hclgevf_sync_promisc_mode(hdev);
2222
2223 hdev->last_serv_processed = jiffies;
2224
2225out:
2226 hclgevf_task_schedule(hdev, delta);
2227}
2228
2229static void hclgevf_service_task(struct work_struct *work)
2230{
2231 struct hclgevf_dev *hdev = container_of(work, struct hclgevf_dev,
2232 service_task.work);
2233
2234 hclgevf_reset_service_task(hdev);
2235 hclgevf_mailbox_service_task(hdev);
2236 hclgevf_periodic_service_task(hdev);
2237
2238
2239
2240
2241
2242 hclgevf_reset_service_task(hdev);
2243 hclgevf_mailbox_service_task(hdev);
2244}
2245
2246static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
2247{
2248 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
2249}
2250
2251static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
2252 u32 *clearval)
2253{
2254 u32 val, cmdq_stat_reg, rst_ing_reg;
2255
2256
2257 cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
2258 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
2259
2260 if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
2261 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2262 dev_info(&hdev->pdev->dev,
2263 "receive reset interrupt 0x%x!\n", rst_ing_reg);
2264 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
2265 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
2266 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
2267 *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
2268 hdev->rst_stats.vf_rst_cnt++;
2269
2270
2271
2272 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_VF_RST_ING);
2273 hclgevf_write_dev(&hdev->hw, HCLGEVF_VF_RST_ING,
2274 val | HCLGEVF_VF_RST_ING_BIT);
2275 return HCLGEVF_VECTOR0_EVENT_RST;
2276 }
2277
2278
2279 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
2280
2281
2282
2283
2284
2285
2286
2287 if (hdev->pdev->revision >= 0x21)
2288 *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2289 else
2290 *clearval = cmdq_stat_reg &
2291 ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
2292
2293 return HCLGEVF_VECTOR0_EVENT_MBX;
2294 }
2295
2296
2297 dev_info(&hdev->pdev->dev,
2298 "vector 0 interrupt from unknown source, cmdq_src = %#x\n",
2299 cmdq_stat_reg);
2300
2301 return HCLGEVF_VECTOR0_EVENT_OTHER;
2302}
2303
2304static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
2305{
2306 enum hclgevf_evt_cause event_cause;
2307 struct hclgevf_dev *hdev = data;
2308 u32 clearval;
2309
2310 hclgevf_enable_vector(&hdev->misc_vector, false);
2311 event_cause = hclgevf_check_evt_cause(hdev, &clearval);
2312
2313 switch (event_cause) {
2314 case HCLGEVF_VECTOR0_EVENT_RST:
2315 hclgevf_reset_task_schedule(hdev);
2316 break;
2317 case HCLGEVF_VECTOR0_EVENT_MBX:
2318 hclgevf_mbx_handler(hdev);
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
2325 hclgevf_clear_event_cause(hdev, clearval);
2326 hclgevf_enable_vector(&hdev->misc_vector, true);
2327 }
2328
2329 return IRQ_HANDLED;
2330}
2331
2332static int hclgevf_configure(struct hclgevf_dev *hdev)
2333{
2334 int ret;
2335
2336
2337 ret = hclgevf_get_port_base_vlan_filter_state(hdev);
2338 if (ret)
2339 return ret;
2340
2341
2342 ret = hclgevf_get_queue_info(hdev);
2343 if (ret)
2344 return ret;
2345
2346
2347 ret = hclgevf_get_queue_depth(hdev);
2348 if (ret)
2349 return ret;
2350
2351 ret = hclgevf_get_pf_media_type(hdev);
2352 if (ret)
2353 return ret;
2354
2355
2356 return hclgevf_get_tc_info(hdev);
2357}
2358
2359static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
2360{
2361 struct pci_dev *pdev = ae_dev->pdev;
2362 struct hclgevf_dev *hdev;
2363
2364 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
2365 if (!hdev)
2366 return -ENOMEM;
2367
2368 hdev->pdev = pdev;
2369 hdev->ae_dev = ae_dev;
2370 ae_dev->priv = hdev;
2371
2372 return 0;
2373}
2374
2375static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
2376{
2377 struct hnae3_handle *roce = &hdev->roce;
2378 struct hnae3_handle *nic = &hdev->nic;
2379
2380 roce->rinfo.num_vectors = hdev->num_roce_msix;
2381
2382 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
2383 hdev->num_msi_left == 0)
2384 return -EINVAL;
2385
2386 roce->rinfo.base_vector = hdev->roce_base_vector;
2387
2388 roce->rinfo.netdev = nic->kinfo.netdev;
2389 roce->rinfo.roce_io_base = hdev->hw.io_base;
2390
2391 roce->pdev = nic->pdev;
2392 roce->ae_algo = nic->ae_algo;
2393 roce->numa_node_mask = nic->numa_node_mask;
2394
2395 return 0;
2396}
2397
2398static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
2399{
2400 struct hclgevf_cfg_gro_status_cmd *req;
2401 struct hclgevf_desc desc;
2402 int ret;
2403
2404 if (!hnae3_dev_gro_supported(hdev))
2405 return 0;
2406
2407 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
2408 false);
2409 req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
2410
2411 req->gro_en = en ? 1 : 0;
2412
2413 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2414 if (ret)
2415 dev_err(&hdev->pdev->dev,
2416 "VF GRO hardware config cmd failed, ret = %d.\n", ret);
2417
2418 return ret;
2419}
2420
2421static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
2422{
2423 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2424 struct hclgevf_rss_tuple_cfg *tuple_sets;
2425 u32 i;
2426
2427 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
2428 rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
2429 tuple_sets = &rss_cfg->rss_tuple_sets;
2430 if (hdev->pdev->revision >= 0x21) {
2431 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
2432 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
2433 HCLGEVF_RSS_KEY_SIZE);
2434
2435 tuple_sets->ipv4_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2436 tuple_sets->ipv4_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2437 tuple_sets->ipv4_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2438 tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2439 tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2440 tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2441 tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
2442 tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
2443 }
2444
2445
2446 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
2447 rss_cfg->rss_indirection_tbl[i] = i % rss_cfg->rss_size;
2448}
2449
2450static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
2451{
2452 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
2453 int ret;
2454
2455 if (hdev->pdev->revision >= 0x21) {
2456 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
2457 rss_cfg->rss_hash_key);
2458 if (ret)
2459 return ret;
2460
2461 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
2462 if (ret)
2463 return ret;
2464 }
2465
2466 ret = hclgevf_set_rss_indir_table(hdev);
2467 if (ret)
2468 return ret;
2469
2470 return hclgevf_set_rss_tc_mode(hdev, rss_cfg->rss_size);
2471}
2472
2473static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2474{
2475 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2476 false);
2477}
2478
2479static void hclgevf_flush_link_update(struct hclgevf_dev *hdev)
2480{
2481#define HCLGEVF_FLUSH_LINK_TIMEOUT 100000
2482
2483 unsigned long last = hdev->serv_processed_cnt;
2484 int i = 0;
2485
2486 while (test_bit(HCLGEVF_STATE_LINK_UPDATING, &hdev->state) &&
2487 i++ < HCLGEVF_FLUSH_LINK_TIMEOUT &&
2488 last == hdev->serv_processed_cnt)
2489 usleep_range(1, 1);
2490}
2491
2492static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2493{
2494 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2495
2496 if (enable) {
2497 hclgevf_task_schedule(hdev, 0);
2498 } else {
2499 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2500
2501
2502 smp_mb__before_atomic();
2503 hclgevf_flush_link_update(hdev);
2504 }
2505}
2506
2507static int hclgevf_ae_start(struct hnae3_handle *handle)
2508{
2509 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2510
2511 hclgevf_reset_tqp_stats(handle);
2512
2513 hclgevf_request_link_info(hdev);
2514
2515 hclgevf_update_link_mode(hdev);
2516
2517 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2518
2519 return 0;
2520}
2521
2522static void hclgevf_ae_stop(struct hnae3_handle *handle)
2523{
2524 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2525 int i;
2526
2527 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2528
2529 if (hdev->reset_type != HNAE3_VF_RESET)
2530 for (i = 0; i < handle->kinfo.num_tqps; i++)
2531 if (hclgevf_reset_tqp(handle, i))
2532 break;
2533
2534 hclgevf_reset_tqp_stats(handle);
2535 hclgevf_update_link_status(hdev, 0);
2536}
2537
2538static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2539{
2540#define HCLGEVF_STATE_ALIVE 1
2541#define HCLGEVF_STATE_NOT_ALIVE 0
2542
2543 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2544 struct hclge_vf_to_pf_msg send_msg;
2545
2546 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_ALIVE, 0);
2547 send_msg.data[0] = alive ? HCLGEVF_STATE_ALIVE :
2548 HCLGEVF_STATE_NOT_ALIVE;
2549 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2550}
2551
2552static int hclgevf_client_start(struct hnae3_handle *handle)
2553{
2554 int ret;
2555
2556 ret = hclgevf_set_alive(handle, true);
2557 if (ret)
2558 return ret;
2559
2560 return 0;
2561}
2562
2563static void hclgevf_client_stop(struct hnae3_handle *handle)
2564{
2565 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2566 int ret;
2567
2568 ret = hclgevf_set_alive(handle, false);
2569 if (ret)
2570 dev_warn(&hdev->pdev->dev,
2571 "%s failed %d\n", __func__, ret);
2572}
2573
2574static void hclgevf_state_init(struct hclgevf_dev *hdev)
2575{
2576 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2577 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2578 clear_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state);
2579
2580 INIT_DELAYED_WORK(&hdev->service_task, hclgevf_service_task);
2581
2582 mutex_init(&hdev->mbx_resp.mbx_mutex);
2583 sema_init(&hdev->reset_sem, 1);
2584
2585 spin_lock_init(&hdev->mac_table.mac_list_lock);
2586 INIT_LIST_HEAD(&hdev->mac_table.uc_mac_list);
2587 INIT_LIST_HEAD(&hdev->mac_table.mc_mac_list);
2588
2589
2590 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2591}
2592
2593static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2594{
2595 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2596 set_bit(HCLGEVF_STATE_REMOVING, &hdev->state);
2597
2598 if (hdev->service_task.work.func)
2599 cancel_delayed_work_sync(&hdev->service_task);
2600
2601 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2602}
2603
2604static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2605{
2606 struct pci_dev *pdev = hdev->pdev;
2607 int vectors;
2608 int i;
2609
2610 if (hnae3_dev_roce_supported(hdev))
2611 vectors = pci_alloc_irq_vectors(pdev,
2612 hdev->roce_base_msix_offset + 1,
2613 hdev->num_msi,
2614 PCI_IRQ_MSIX);
2615 else
2616 vectors = pci_alloc_irq_vectors(pdev, HNAE3_MIN_VECTOR_NUM,
2617 hdev->num_msi,
2618 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2619
2620 if (vectors < 0) {
2621 dev_err(&pdev->dev,
2622 "failed(%d) to allocate MSI/MSI-X vectors\n",
2623 vectors);
2624 return vectors;
2625 }
2626 if (vectors < hdev->num_msi)
2627 dev_warn(&hdev->pdev->dev,
2628 "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2629 hdev->num_msi, vectors);
2630
2631 hdev->num_msi = vectors;
2632 hdev->num_msi_left = vectors;
2633
2634 hdev->base_msi_vector = pdev->irq;
2635 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2636
2637 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2638 sizeof(u16), GFP_KERNEL);
2639 if (!hdev->vector_status) {
2640 pci_free_irq_vectors(pdev);
2641 return -ENOMEM;
2642 }
2643
2644 for (i = 0; i < hdev->num_msi; i++)
2645 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2646
2647 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2648 sizeof(int), GFP_KERNEL);
2649 if (!hdev->vector_irq) {
2650 devm_kfree(&pdev->dev, hdev->vector_status);
2651 pci_free_irq_vectors(pdev);
2652 return -ENOMEM;
2653 }
2654
2655 return 0;
2656}
2657
2658static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2659{
2660 struct pci_dev *pdev = hdev->pdev;
2661
2662 devm_kfree(&pdev->dev, hdev->vector_status);
2663 devm_kfree(&pdev->dev, hdev->vector_irq);
2664 pci_free_irq_vectors(pdev);
2665}
2666
2667static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2668{
2669 int ret;
2670
2671 hclgevf_get_misc_vector(hdev);
2672
2673 snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
2674 HCLGEVF_NAME, pci_name(hdev->pdev));
2675 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2676 0, hdev->misc_vector.name, hdev);
2677 if (ret) {
2678 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2679 hdev->misc_vector.vector_irq);
2680 return ret;
2681 }
2682
2683 hclgevf_clear_event_cause(hdev, 0);
2684
2685
2686 hclgevf_enable_vector(&hdev->misc_vector, true);
2687
2688 return ret;
2689}
2690
2691static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2692{
2693
2694 hclgevf_enable_vector(&hdev->misc_vector, false);
2695 synchronize_irq(hdev->misc_vector.vector_irq);
2696 free_irq(hdev->misc_vector.vector_irq, hdev);
2697 hclgevf_free_vector(hdev, 0);
2698}
2699
2700static void hclgevf_info_show(struct hclgevf_dev *hdev)
2701{
2702 struct device *dev = &hdev->pdev->dev;
2703
2704 dev_info(dev, "VF info begin:\n");
2705
2706 dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
2707 dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
2708 dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
2709 dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
2710 dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
2711 dev_info(dev, "PF media type of this VF: %u\n",
2712 hdev->hw.mac.media_type);
2713
2714 dev_info(dev, "VF info end.\n");
2715}
2716
2717static int hclgevf_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
2718 struct hnae3_client *client)
2719{
2720 struct hclgevf_dev *hdev = ae_dev->priv;
2721 int rst_cnt = hdev->rst_stats.rst_cnt;
2722 int ret;
2723
2724 ret = client->ops->init_instance(&hdev->nic);
2725 if (ret)
2726 return ret;
2727
2728 set_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2729 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
2730 rst_cnt != hdev->rst_stats.rst_cnt) {
2731 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2732
2733 client->ops->uninit_instance(&hdev->nic, 0);
2734 return -EBUSY;
2735 }
2736
2737 hnae3_set_client_init_flag(client, ae_dev, 1);
2738
2739 if (netif_msg_drv(&hdev->nic))
2740 hclgevf_info_show(hdev);
2741
2742 return 0;
2743}
2744
2745static int hclgevf_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
2746 struct hnae3_client *client)
2747{
2748 struct hclgevf_dev *hdev = ae_dev->priv;
2749 int ret;
2750
2751 if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
2752 !hdev->nic_client)
2753 return 0;
2754
2755 ret = hclgevf_init_roce_base_info(hdev);
2756 if (ret)
2757 return ret;
2758
2759 ret = client->ops->init_instance(&hdev->roce);
2760 if (ret)
2761 return ret;
2762
2763 hnae3_set_client_init_flag(client, ae_dev, 1);
2764
2765 return 0;
2766}
2767
2768static int hclgevf_init_client_instance(struct hnae3_client *client,
2769 struct hnae3_ae_dev *ae_dev)
2770{
2771 struct hclgevf_dev *hdev = ae_dev->priv;
2772 int ret;
2773
2774 switch (client->type) {
2775 case HNAE3_CLIENT_KNIC:
2776 hdev->nic_client = client;
2777 hdev->nic.client = client;
2778
2779 ret = hclgevf_init_nic_client_instance(ae_dev, client);
2780 if (ret)
2781 goto clear_nic;
2782
2783 ret = hclgevf_init_roce_client_instance(ae_dev,
2784 hdev->roce_client);
2785 if (ret)
2786 goto clear_roce;
2787
2788 break;
2789 case HNAE3_CLIENT_ROCE:
2790 if (hnae3_dev_roce_supported(hdev)) {
2791 hdev->roce_client = client;
2792 hdev->roce.client = client;
2793 }
2794
2795 ret = hclgevf_init_roce_client_instance(ae_dev, client);
2796 if (ret)
2797 goto clear_roce;
2798
2799 break;
2800 default:
2801 return -EINVAL;
2802 }
2803
2804 return 0;
2805
2806clear_nic:
2807 hdev->nic_client = NULL;
2808 hdev->nic.client = NULL;
2809 return ret;
2810clear_roce:
2811 hdev->roce_client = NULL;
2812 hdev->roce.client = NULL;
2813 return ret;
2814}
2815
2816static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2817 struct hnae3_ae_dev *ae_dev)
2818{
2819 struct hclgevf_dev *hdev = ae_dev->priv;
2820
2821
2822 if (hdev->roce_client) {
2823 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2824 hdev->roce_client = NULL;
2825 hdev->roce.client = NULL;
2826 }
2827
2828
2829 if (client->ops->uninit_instance && hdev->nic_client &&
2830 client->type != HNAE3_CLIENT_ROCE) {
2831 clear_bit(HCLGEVF_STATE_NIC_REGISTERED, &hdev->state);
2832
2833 client->ops->uninit_instance(&hdev->nic, 0);
2834 hdev->nic_client = NULL;
2835 hdev->nic.client = NULL;
2836 }
2837}
2838
2839static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2840{
2841 struct pci_dev *pdev = hdev->pdev;
2842 struct hclgevf_hw *hw;
2843 int ret;
2844
2845 ret = pci_enable_device(pdev);
2846 if (ret) {
2847 dev_err(&pdev->dev, "failed to enable PCI device\n");
2848 return ret;
2849 }
2850
2851 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2852 if (ret) {
2853 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2854 goto err_disable_device;
2855 }
2856
2857 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2858 if (ret) {
2859 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2860 goto err_disable_device;
2861 }
2862
2863 pci_set_master(pdev);
2864 hw = &hdev->hw;
2865 hw->hdev = hdev;
2866 hw->io_base = pci_iomap(pdev, 2, 0);
2867 if (!hw->io_base) {
2868 dev_err(&pdev->dev, "can't map configuration register space\n");
2869 ret = -ENOMEM;
2870 goto err_clr_master;
2871 }
2872
2873 return 0;
2874
2875err_clr_master:
2876 pci_clear_master(pdev);
2877 pci_release_regions(pdev);
2878err_disable_device:
2879 pci_disable_device(pdev);
2880
2881 return ret;
2882}
2883
2884static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2885{
2886 struct pci_dev *pdev = hdev->pdev;
2887
2888 pci_iounmap(pdev, hdev->hw.io_base);
2889 pci_clear_master(pdev);
2890 pci_release_regions(pdev);
2891 pci_disable_device(pdev);
2892}
2893
2894static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2895{
2896 struct hclgevf_query_res_cmd *req;
2897 struct hclgevf_desc desc;
2898 int ret;
2899
2900 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
2901 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2902 if (ret) {
2903 dev_err(&hdev->pdev->dev,
2904 "query vf resource failed, ret = %d.\n", ret);
2905 return ret;
2906 }
2907
2908 req = (struct hclgevf_query_res_cmd *)desc.data;
2909
2910 if (hnae3_dev_roce_supported(hdev)) {
2911 hdev->roce_base_msix_offset =
2912 hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
2913 HCLGEVF_MSIX_OFT_ROCEE_M,
2914 HCLGEVF_MSIX_OFT_ROCEE_S);
2915 hdev->num_roce_msix =
2916 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2917 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2918
2919
2920 hdev->num_nic_msix = hdev->num_roce_msix;
2921
2922
2923
2924
2925 hdev->num_msi = hdev->num_roce_msix +
2926 hdev->roce_base_msix_offset;
2927 } else {
2928 hdev->num_msi =
2929 hnae3_get_field(le16_to_cpu(req->vf_intr_vector_number),
2930 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2931
2932 hdev->num_nic_msix = hdev->num_msi;
2933 }
2934
2935 if (hdev->num_nic_msix < HNAE3_MIN_VECTOR_NUM) {
2936 dev_err(&hdev->pdev->dev,
2937 "Just %u msi resources, not enough for vf(min:2).\n",
2938 hdev->num_nic_msix);
2939 return -EINVAL;
2940 }
2941
2942 return 0;
2943}
2944
2945static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
2946{
2947 struct pci_dev *pdev = hdev->pdev;
2948 int ret = 0;
2949
2950 if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
2951 test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2952 hclgevf_misc_irq_uninit(hdev);
2953 hclgevf_uninit_msi(hdev);
2954 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2955 }
2956
2957 if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2958 pci_set_master(pdev);
2959 ret = hclgevf_init_msi(hdev);
2960 if (ret) {
2961 dev_err(&pdev->dev,
2962 "failed(%d) to init MSI/MSI-X\n", ret);
2963 return ret;
2964 }
2965
2966 ret = hclgevf_misc_irq_init(hdev);
2967 if (ret) {
2968 hclgevf_uninit_msi(hdev);
2969 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2970 ret);
2971 return ret;
2972 }
2973
2974 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2975 }
2976
2977 return ret;
2978}
2979
2980static int hclgevf_clear_vport_list(struct hclgevf_dev *hdev)
2981{
2982 struct hclge_vf_to_pf_msg send_msg;
2983
2984 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_HANDLE_VF_TBL,
2985 HCLGE_MBX_VPORT_LIST_CLEAR);
2986 return hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
2987}
2988
2989static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
2990{
2991 struct pci_dev *pdev = hdev->pdev;
2992 int ret;
2993
2994 ret = hclgevf_pci_reset(hdev);
2995 if (ret) {
2996 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
2997 return ret;
2998 }
2999
3000 ret = hclgevf_cmd_init(hdev);
3001 if (ret) {
3002 dev_err(&pdev->dev, "cmd failed %d\n", ret);
3003 return ret;
3004 }
3005
3006 ret = hclgevf_rss_init_hw(hdev);
3007 if (ret) {
3008 dev_err(&hdev->pdev->dev,
3009 "failed(%d) to initialize RSS\n", ret);
3010 return ret;
3011 }
3012
3013 ret = hclgevf_config_gro(hdev, true);
3014 if (ret)
3015 return ret;
3016
3017 ret = hclgevf_init_vlan_config(hdev);
3018 if (ret) {
3019 dev_err(&hdev->pdev->dev,
3020 "failed(%d) to initialize VLAN config\n", ret);
3021 return ret;
3022 }
3023
3024 set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
3025
3026 dev_info(&hdev->pdev->dev, "Reset done\n");
3027
3028 return 0;
3029}
3030
3031static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
3032{
3033 struct pci_dev *pdev = hdev->pdev;
3034 int ret;
3035
3036 ret = hclgevf_pci_init(hdev);
3037 if (ret)
3038 return ret;
3039
3040 ret = hclgevf_cmd_queue_init(hdev);
3041 if (ret)
3042 goto err_cmd_queue_init;
3043
3044 ret = hclgevf_cmd_init(hdev);
3045 if (ret)
3046 goto err_cmd_init;
3047
3048
3049 ret = hclgevf_query_vf_resource(hdev);
3050 if (ret)
3051 goto err_cmd_init;
3052
3053 ret = hclgevf_init_msi(hdev);
3054 if (ret) {
3055 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
3056 goto err_cmd_init;
3057 }
3058
3059 hclgevf_state_init(hdev);
3060 hdev->reset_level = HNAE3_VF_FUNC_RESET;
3061 hdev->reset_type = HNAE3_NONE_RESET;
3062
3063 ret = hclgevf_misc_irq_init(hdev);
3064 if (ret)
3065 goto err_misc_irq_init;
3066
3067 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3068
3069 ret = hclgevf_configure(hdev);
3070 if (ret) {
3071 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
3072 goto err_config;
3073 }
3074
3075 ret = hclgevf_alloc_tqps(hdev);
3076 if (ret) {
3077 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
3078 goto err_config;
3079 }
3080
3081 ret = hclgevf_set_handle_info(hdev);
3082 if (ret)
3083 goto err_config;
3084
3085 ret = hclgevf_config_gro(hdev, true);
3086 if (ret)
3087 goto err_config;
3088
3089
3090 hclgevf_rss_init_cfg(hdev);
3091 ret = hclgevf_rss_init_hw(hdev);
3092 if (ret) {
3093 dev_err(&hdev->pdev->dev,
3094 "failed(%d) to initialize RSS\n", ret);
3095 goto err_config;
3096 }
3097
3098
3099 ret = hclgevf_clear_vport_list(hdev);
3100 if (ret) {
3101 dev_err(&pdev->dev,
3102 "failed to clear tbl list configuration, ret = %d.\n",
3103 ret);
3104 goto err_config;
3105 }
3106
3107 ret = hclgevf_init_vlan_config(hdev);
3108 if (ret) {
3109 dev_err(&hdev->pdev->dev,
3110 "failed(%d) to initialize VLAN config\n", ret);
3111 goto err_config;
3112 }
3113
3114 hdev->last_reset_time = jiffies;
3115 dev_info(&hdev->pdev->dev, "finished initializing %s driver\n",
3116 HCLGEVF_DRIVER_NAME);
3117
3118 hclgevf_task_schedule(hdev, round_jiffies_relative(HZ));
3119
3120 return 0;
3121
3122err_config:
3123 hclgevf_misc_irq_uninit(hdev);
3124err_misc_irq_init:
3125 hclgevf_state_uninit(hdev);
3126 hclgevf_uninit_msi(hdev);
3127err_cmd_init:
3128 hclgevf_cmd_uninit(hdev);
3129err_cmd_queue_init:
3130 hclgevf_pci_uninit(hdev);
3131 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
3132 return ret;
3133}
3134
3135static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
3136{
3137 struct hclge_vf_to_pf_msg send_msg;
3138
3139 hclgevf_state_uninit(hdev);
3140
3141 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_VF_UNINIT, 0);
3142 hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3143
3144 if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
3145 hclgevf_misc_irq_uninit(hdev);
3146 hclgevf_uninit_msi(hdev);
3147 }
3148
3149 hclgevf_pci_uninit(hdev);
3150 hclgevf_cmd_uninit(hdev);
3151 hclgevf_uninit_mac_list(hdev);
3152}
3153
3154static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
3155{
3156 struct pci_dev *pdev = ae_dev->pdev;
3157 int ret;
3158
3159 ret = hclgevf_alloc_hdev(ae_dev);
3160 if (ret) {
3161 dev_err(&pdev->dev, "hclge device allocation failed\n");
3162 return ret;
3163 }
3164
3165 ret = hclgevf_init_hdev(ae_dev->priv);
3166 if (ret) {
3167 dev_err(&pdev->dev, "hclge device initialization failed\n");
3168 return ret;
3169 }
3170
3171 return 0;
3172}
3173
3174static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
3175{
3176 struct hclgevf_dev *hdev = ae_dev->priv;
3177
3178 hclgevf_uninit_hdev(hdev);
3179 ae_dev->priv = NULL;
3180}
3181
3182static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
3183{
3184 struct hnae3_handle *nic = &hdev->nic;
3185 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
3186
3187 return min_t(u32, hdev->rss_size_max,
3188 hdev->num_tqps / kinfo->num_tc);
3189}
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201static void hclgevf_get_channels(struct hnae3_handle *handle,
3202 struct ethtool_channels *ch)
3203{
3204 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3205
3206 ch->max_combined = hclgevf_get_max_channels(hdev);
3207 ch->other_count = 0;
3208 ch->max_other = 0;
3209 ch->combined_count = handle->kinfo.rss_size;
3210}
3211
3212static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
3213 u16 *alloc_tqps, u16 *max_rss_size)
3214{
3215 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3216
3217 *alloc_tqps = hdev->num_tqps;
3218 *max_rss_size = hdev->rss_size_max;
3219}
3220
3221static void hclgevf_update_rss_size(struct hnae3_handle *handle,
3222 u32 new_tqps_num)
3223{
3224 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3225 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3226 u16 max_rss_size;
3227
3228 kinfo->req_rss_size = new_tqps_num;
3229
3230 max_rss_size = min_t(u16, hdev->rss_size_max,
3231 hdev->num_tqps / kinfo->num_tc);
3232
3233
3234
3235
3236 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
3237 kinfo->req_rss_size <= max_rss_size)
3238 kinfo->rss_size = kinfo->req_rss_size;
3239 else if (kinfo->rss_size > max_rss_size ||
3240 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size))
3241 kinfo->rss_size = max_rss_size;
3242
3243 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
3244}
3245
3246static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
3247 bool rxfh_configured)
3248{
3249 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3250 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
3251 u16 cur_rss_size = kinfo->rss_size;
3252 u16 cur_tqps = kinfo->num_tqps;
3253 u32 *rss_indir;
3254 unsigned int i;
3255 int ret;
3256
3257 hclgevf_update_rss_size(handle, new_tqps_num);
3258
3259 ret = hclgevf_set_rss_tc_mode(hdev, kinfo->rss_size);
3260 if (ret)
3261 return ret;
3262
3263
3264 if (rxfh_configured)
3265 goto out;
3266
3267
3268 rss_indir = kcalloc(HCLGEVF_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3269 if (!rss_indir)
3270 return -ENOMEM;
3271
3272 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
3273 rss_indir[i] = i % kinfo->rss_size;
3274
3275 hdev->rss_cfg.rss_size = kinfo->rss_size;
3276
3277 ret = hclgevf_set_rss(handle, rss_indir, NULL, 0);
3278 if (ret)
3279 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
3280 ret);
3281
3282 kfree(rss_indir);
3283
3284out:
3285 if (!ret)
3286 dev_info(&hdev->pdev->dev,
3287 "Channels changed, rss_size from %u to %u, tqps from %u to %u",
3288 cur_rss_size, kinfo->rss_size,
3289 cur_tqps, kinfo->rss_size * kinfo->num_tc);
3290
3291 return ret;
3292}
3293
3294static int hclgevf_get_status(struct hnae3_handle *handle)
3295{
3296 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3297
3298 return hdev->hw.mac.link;
3299}
3300
3301static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
3302 u8 *auto_neg, u32 *speed,
3303 u8 *duplex)
3304{
3305 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3306
3307 if (speed)
3308 *speed = hdev->hw.mac.speed;
3309 if (duplex)
3310 *duplex = hdev->hw.mac.duplex;
3311 if (auto_neg)
3312 *auto_neg = AUTONEG_DISABLE;
3313}
3314
3315void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
3316 u8 duplex)
3317{
3318 hdev->hw.mac.speed = speed;
3319 hdev->hw.mac.duplex = duplex;
3320}
3321
3322static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
3323{
3324 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3325
3326 return hclgevf_config_gro(hdev, enable);
3327}
3328
3329static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
3330 u8 *module_type)
3331{
3332 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3333
3334 if (media_type)
3335 *media_type = hdev->hw.mac.media_type;
3336
3337 if (module_type)
3338 *module_type = hdev->hw.mac.module_type;
3339}
3340
3341static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
3342{
3343 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3344
3345 return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
3346}
3347
3348static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
3349{
3350 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3351
3352 return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
3353}
3354
3355static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
3356{
3357 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3358
3359 return hdev->rst_stats.hw_rst_done_cnt;
3360}
3361
3362static void hclgevf_get_link_mode(struct hnae3_handle *handle,
3363 unsigned long *supported,
3364 unsigned long *advertising)
3365{
3366 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3367
3368 *supported = hdev->hw.mac.supported;
3369 *advertising = hdev->hw.mac.advertising;
3370}
3371
3372#define MAX_SEPARATE_NUM 4
3373#define SEPARATOR_VALUE 0xFFFFFFFF
3374#define REG_NUM_PER_LINE 4
3375#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
3376
3377static int hclgevf_get_regs_len(struct hnae3_handle *handle)
3378{
3379 int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
3380 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3381
3382 cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
3383 common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
3384 ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
3385 tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
3386
3387 return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
3388 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
3389}
3390
3391static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
3392 void *data)
3393{
3394 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
3395 int i, j, reg_um, separator_num;
3396 u32 *reg = data;
3397
3398 *version = hdev->fw_version;
3399
3400
3401 reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
3402 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3403 for (i = 0; i < reg_um; i++)
3404 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
3405 for (i = 0; i < separator_num; i++)
3406 *reg++ = SEPARATOR_VALUE;
3407
3408 reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
3409 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3410 for (i = 0; i < reg_um; i++)
3411 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
3412 for (i = 0; i < separator_num; i++)
3413 *reg++ = SEPARATOR_VALUE;
3414
3415 reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
3416 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3417 for (j = 0; j < hdev->num_tqps; j++) {
3418 for (i = 0; i < reg_um; i++)
3419 *reg++ = hclgevf_read_dev(&hdev->hw,
3420 ring_reg_addr_list[i] +
3421 0x200 * j);
3422 for (i = 0; i < separator_num; i++)
3423 *reg++ = SEPARATOR_VALUE;
3424 }
3425
3426 reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
3427 separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
3428 for (j = 0; j < hdev->num_msi_used - 1; j++) {
3429 for (i = 0; i < reg_um; i++)
3430 *reg++ = hclgevf_read_dev(&hdev->hw,
3431 tqp_intr_reg_addr_list[i] +
3432 4 * j);
3433 for (i = 0; i < separator_num; i++)
3434 *reg++ = SEPARATOR_VALUE;
3435 }
3436}
3437
3438void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
3439 u8 *port_base_vlan_info, u8 data_size)
3440{
3441 struct hnae3_handle *nic = &hdev->nic;
3442 struct hclge_vf_to_pf_msg send_msg;
3443 int ret;
3444
3445 rtnl_lock();
3446
3447 if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state) ||
3448 test_bit(HCLGEVF_STATE_RST_FAIL, &hdev->state)) {
3449 dev_warn(&hdev->pdev->dev,
3450 "is resetting when updating port based vlan info\n");
3451 rtnl_unlock();
3452 return;
3453 }
3454
3455 ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
3456 if (ret) {
3457 rtnl_unlock();
3458 return;
3459 }
3460
3461
3462 hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_VLAN,
3463 HCLGE_MBX_PORT_BASE_VLAN_CFG);
3464 memcpy(send_msg.data, port_base_vlan_info, data_size);
3465 ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
3466 if (!ret) {
3467 if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
3468 nic->port_base_vlan_state = state;
3469 else
3470 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
3471 }
3472
3473 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
3474 rtnl_unlock();
3475}
3476
3477static const struct hnae3_ae_ops hclgevf_ops = {
3478 .init_ae_dev = hclgevf_init_ae_dev,
3479 .uninit_ae_dev = hclgevf_uninit_ae_dev,
3480 .flr_prepare = hclgevf_flr_prepare,
3481 .flr_done = hclgevf_flr_done,
3482 .init_client_instance = hclgevf_init_client_instance,
3483 .uninit_client_instance = hclgevf_uninit_client_instance,
3484 .start = hclgevf_ae_start,
3485 .stop = hclgevf_ae_stop,
3486 .client_start = hclgevf_client_start,
3487 .client_stop = hclgevf_client_stop,
3488 .map_ring_to_vector = hclgevf_map_ring_to_vector,
3489 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
3490 .get_vector = hclgevf_get_vector,
3491 .put_vector = hclgevf_put_vector,
3492 .reset_queue = hclgevf_reset_tqp,
3493 .get_mac_addr = hclgevf_get_mac_addr,
3494 .set_mac_addr = hclgevf_set_mac_addr,
3495 .add_uc_addr = hclgevf_add_uc_addr,
3496 .rm_uc_addr = hclgevf_rm_uc_addr,
3497 .add_mc_addr = hclgevf_add_mc_addr,
3498 .rm_mc_addr = hclgevf_rm_mc_addr,
3499 .get_stats = hclgevf_get_stats,
3500 .update_stats = hclgevf_update_stats,
3501 .get_strings = hclgevf_get_strings,
3502 .get_sset_count = hclgevf_get_sset_count,
3503 .get_rss_key_size = hclgevf_get_rss_key_size,
3504 .get_rss_indir_size = hclgevf_get_rss_indir_size,
3505 .get_rss = hclgevf_get_rss,
3506 .set_rss = hclgevf_set_rss,
3507 .get_rss_tuple = hclgevf_get_rss_tuple,
3508 .set_rss_tuple = hclgevf_set_rss_tuple,
3509 .get_tc_size = hclgevf_get_tc_size,
3510 .get_fw_version = hclgevf_get_fw_version,
3511 .set_vlan_filter = hclgevf_set_vlan_filter,
3512 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
3513 .reset_event = hclgevf_reset_event,
3514 .set_default_reset_request = hclgevf_set_def_reset_request,
3515 .set_channels = hclgevf_set_channels,
3516 .get_channels = hclgevf_get_channels,
3517 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
3518 .get_regs_len = hclgevf_get_regs_len,
3519 .get_regs = hclgevf_get_regs,
3520 .get_status = hclgevf_get_status,
3521 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
3522 .get_media_type = hclgevf_get_media_type,
3523 .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
3524 .ae_dev_resetting = hclgevf_ae_dev_resetting,
3525 .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
3526 .set_gro_en = hclgevf_gro_en,
3527 .set_mtu = hclgevf_set_mtu,
3528 .get_global_queue_id = hclgevf_get_qid_global,
3529 .set_timer_task = hclgevf_set_timer_task,
3530 .get_link_mode = hclgevf_get_link_mode,
3531 .set_promisc_mode = hclgevf_set_promisc_mode,
3532 .request_update_promisc_mode = hclgevf_request_update_promisc_mode,
3533};
3534
3535static struct hnae3_ae_algo ae_algovf = {
3536 .ops = &hclgevf_ops,
3537 .pdev_id_table = ae_algovf_pci_tbl,
3538};
3539
3540static int hclgevf_init(void)
3541{
3542 pr_info("%s is initializing\n", HCLGEVF_NAME);
3543
3544 hclgevf_wq = alloc_workqueue("%s", 0, 0, HCLGEVF_NAME);
3545 if (!hclgevf_wq) {
3546 pr_err("%s: failed to create workqueue\n", HCLGEVF_NAME);
3547 return -ENOMEM;
3548 }
3549
3550 hnae3_register_ae_algo(&ae_algovf);
3551
3552 return 0;
3553}
3554
3555static void hclgevf_exit(void)
3556{
3557 hnae3_unregister_ae_algo(&ae_algovf);
3558 destroy_workqueue(hclgevf_wq);
3559}
3560module_init(hclgevf_init);
3561module_exit(hclgevf_exit);
3562
3563MODULE_LICENSE("GPL");
3564MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3565MODULE_DESCRIPTION("HCLGEVF Driver");
3566MODULE_VERSION(HCLGEVF_MOD_VERSION);
3567