1
2
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/types.h>
7#include <linux/pci.h>
8#include <linux/netdevice.h>
9#include <linux/etherdevice.h>
10#include <linux/slab.h>
11#include <linux/device.h>
12#include <linux/skbuff.h>
13#include <linux/if_vlan.h>
14
15#include "pci.h"
16#include "core.h"
17#include "reg.h"
18#include "port.h"
19#include "trap.h"
20#include "txheader.h"
21#include "ib.h"
22
23static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
24static const char mlxsw_sx_driver_version[] = "1.0";
25
26struct mlxsw_sx_port;
27
28struct mlxsw_sx {
29 struct mlxsw_sx_port **ports;
30 struct mlxsw_core *core;
31 const struct mlxsw_bus_info *bus_info;
32 u8 hw_id[ETH_ALEN];
33};
34
35struct mlxsw_sx_port_pcpu_stats {
36 u64 rx_packets;
37 u64 rx_bytes;
38 u64 tx_packets;
39 u64 tx_bytes;
40 struct u64_stats_sync syncp;
41 u32 tx_dropped;
42};
43
44struct mlxsw_sx_port {
45 struct net_device *dev;
46 struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
47 struct mlxsw_sx *mlxsw_sx;
48 u8 local_port;
49 struct {
50 u8 module;
51 } mapping;
52};
53
54
55
56
57
58MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
59
60
61
62
63
64
65MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
66
67
68
69
70MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
71
72
73
74
75
76
77MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
78
79
80
81
82MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
83
84
85
86
87
88
89
90
91
92MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
93
94
95
96
97MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
98
99
100
101
102
103MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
104
105
106
107
108MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
109
110
111
112
113MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
114
115
116
117
118MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
119
120
121
122
123MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
124
125
126
127
128
129MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
130
131static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
132 const struct mlxsw_tx_info *tx_info)
133{
134 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
135 bool is_emad = tx_info->is_emad;
136
137 memset(txhdr, 0, MLXSW_TXHDR_LEN);
138
139
140 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
141 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
142 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
143 mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
144 MLXSW_TXHDR_ETCLASS_5);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
147 mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
148 mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
149 MLXSW_TXHDR_RDQ_OTHER);
150 mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
151 mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
152 mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
153 mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
154 MLXSW_TXHDR_NOT_EMAD);
155 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
156}
157
158static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
159 bool is_up)
160{
161 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
162 char paos_pl[MLXSW_REG_PAOS_LEN];
163
164 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
165 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
166 MLXSW_PORT_ADMIN_STATUS_DOWN);
167 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
168}
169
170static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
171 bool *p_is_up)
172{
173 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
174 char paos_pl[MLXSW_REG_PAOS_LEN];
175 u8 oper_status;
176 int err;
177
178 mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
179 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
180 if (err)
181 return err;
182 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
183 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP;
184 return 0;
185}
186
187static int __mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port,
188 u16 mtu)
189{
190 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
191 char pmtu_pl[MLXSW_REG_PMTU_LEN];
192 int max_mtu;
193 int err;
194
195 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
196 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
197 if (err)
198 return err;
199 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
200
201 if (mtu > max_mtu)
202 return -EINVAL;
203
204 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
205 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
206}
207
208static int mlxsw_sx_port_mtu_eth_set(struct mlxsw_sx_port *mlxsw_sx_port,
209 u16 mtu)
210{
211 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
212 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
213}
214
215static int mlxsw_sx_port_mtu_ib_set(struct mlxsw_sx_port *mlxsw_sx_port,
216 u16 mtu)
217{
218 return __mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
219}
220
221static int mlxsw_sx_port_ib_port_set(struct mlxsw_sx_port *mlxsw_sx_port,
222 u8 ib_port)
223{
224 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
225 char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
226 int err;
227
228 mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sx_port->local_port);
229 mlxsw_reg_plib_ib_port_set(plib_pl, ib_port);
230 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(plib), plib_pl);
231 return err;
232}
233
234static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
235{
236 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
237 char pspa_pl[MLXSW_REG_PSPA_LEN];
238
239 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
240 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
241}
242
243static int
244mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
245{
246 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
247 char sspr_pl[MLXSW_REG_SSPR_LEN];
248
249 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
250 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
251}
252
253static int mlxsw_sx_port_module_info_get(struct mlxsw_sx *mlxsw_sx,
254 u8 local_port, u8 *p_module,
255 u8 *p_width)
256{
257 char pmlp_pl[MLXSW_REG_PMLP_LEN];
258 int err;
259
260 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
261 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
262 if (err)
263 return err;
264 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
265 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
266 return 0;
267}
268
269static int mlxsw_sx_port_open(struct net_device *dev)
270{
271 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
272 int err;
273
274 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
275 if (err)
276 return err;
277 netif_start_queue(dev);
278 return 0;
279}
280
281static int mlxsw_sx_port_stop(struct net_device *dev)
282{
283 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
284
285 netif_stop_queue(dev);
286 return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
287}
288
289static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
290 struct net_device *dev)
291{
292 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
293 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
294 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
295 const struct mlxsw_tx_info tx_info = {
296 .local_port = mlxsw_sx_port->local_port,
297 .is_emad = false,
298 };
299 u64 len;
300 int err;
301
302 if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
303 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
304 dev_kfree_skb_any(skb);
305 return NETDEV_TX_OK;
306 }
307
308 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
309
310 if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
311 return NETDEV_TX_BUSY;
312
313 mlxsw_sx_txhdr_construct(skb, &tx_info);
314
315
316
317 len = skb->len - MLXSW_TXHDR_LEN;
318
319
320
321 err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
322
323 if (!err) {
324 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
325 u64_stats_update_begin(&pcpu_stats->syncp);
326 pcpu_stats->tx_packets++;
327 pcpu_stats->tx_bytes += len;
328 u64_stats_update_end(&pcpu_stats->syncp);
329 } else {
330 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
331 dev_kfree_skb_any(skb);
332 }
333 return NETDEV_TX_OK;
334}
335
336static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
337{
338 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
339 int err;
340
341 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, mtu);
342 if (err)
343 return err;
344 dev->mtu = mtu;
345 return 0;
346}
347
348static void
349mlxsw_sx_port_get_stats64(struct net_device *dev,
350 struct rtnl_link_stats64 *stats)
351{
352 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
353 struct mlxsw_sx_port_pcpu_stats *p;
354 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
355 u32 tx_dropped = 0;
356 unsigned int start;
357 int i;
358
359 for_each_possible_cpu(i) {
360 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
361 do {
362 start = u64_stats_fetch_begin_irq(&p->syncp);
363 rx_packets = p->rx_packets;
364 rx_bytes = p->rx_bytes;
365 tx_packets = p->tx_packets;
366 tx_bytes = p->tx_bytes;
367 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
368
369 stats->rx_packets += rx_packets;
370 stats->rx_bytes += rx_bytes;
371 stats->tx_packets += tx_packets;
372 stats->tx_bytes += tx_bytes;
373
374 tx_dropped += p->tx_dropped;
375 }
376 stats->tx_dropped = tx_dropped;
377}
378
379static struct devlink_port *
380mlxsw_sx_port_get_devlink_port(struct net_device *dev)
381{
382 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
383 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
384
385 return mlxsw_core_port_devlink_port_get(mlxsw_sx->core,
386 mlxsw_sx_port->local_port);
387}
388
389static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
390 .ndo_open = mlxsw_sx_port_open,
391 .ndo_stop = mlxsw_sx_port_stop,
392 .ndo_start_xmit = mlxsw_sx_port_xmit,
393 .ndo_change_mtu = mlxsw_sx_port_change_mtu,
394 .ndo_get_stats64 = mlxsw_sx_port_get_stats64,
395 .ndo_get_devlink_port = mlxsw_sx_port_get_devlink_port,
396};
397
398static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
399 struct ethtool_drvinfo *drvinfo)
400{
401 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
402 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
403
404 strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
405 strlcpy(drvinfo->version, mlxsw_sx_driver_version,
406 sizeof(drvinfo->version));
407 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
408 "%d.%d.%d",
409 mlxsw_sx->bus_info->fw_rev.major,
410 mlxsw_sx->bus_info->fw_rev.minor,
411 mlxsw_sx->bus_info->fw_rev.subminor);
412 strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
413 sizeof(drvinfo->bus_info));
414}
415
416struct mlxsw_sx_port_hw_stats {
417 char str[ETH_GSTRING_LEN];
418 u64 (*getter)(const char *payload);
419};
420
421static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
422 {
423 .str = "a_frames_transmitted_ok",
424 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
425 },
426 {
427 .str = "a_frames_received_ok",
428 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
429 },
430 {
431 .str = "a_frame_check_sequence_errors",
432 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
433 },
434 {
435 .str = "a_alignment_errors",
436 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
437 },
438 {
439 .str = "a_octets_transmitted_ok",
440 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
441 },
442 {
443 .str = "a_octets_received_ok",
444 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
445 },
446 {
447 .str = "a_multicast_frames_xmitted_ok",
448 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
449 },
450 {
451 .str = "a_broadcast_frames_xmitted_ok",
452 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
453 },
454 {
455 .str = "a_multicast_frames_received_ok",
456 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
457 },
458 {
459 .str = "a_broadcast_frames_received_ok",
460 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
461 },
462 {
463 .str = "a_in_range_length_errors",
464 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
465 },
466 {
467 .str = "a_out_of_range_length_field",
468 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
469 },
470 {
471 .str = "a_frame_too_long_errors",
472 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
473 },
474 {
475 .str = "a_symbol_error_during_carrier",
476 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
477 },
478 {
479 .str = "a_mac_control_frames_transmitted",
480 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
481 },
482 {
483 .str = "a_mac_control_frames_received",
484 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
485 },
486 {
487 .str = "a_unsupported_opcodes_received",
488 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
489 },
490 {
491 .str = "a_pause_mac_ctrl_frames_received",
492 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
493 },
494 {
495 .str = "a_pause_mac_ctrl_frames_xmitted",
496 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
497 },
498};
499
500#define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
501
502static void mlxsw_sx_port_get_strings(struct net_device *dev,
503 u32 stringset, u8 *data)
504{
505 u8 *p = data;
506 int i;
507
508 switch (stringset) {
509 case ETH_SS_STATS:
510 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
511 memcpy(p, mlxsw_sx_port_hw_stats[i].str,
512 ETH_GSTRING_LEN);
513 p += ETH_GSTRING_LEN;
514 }
515 break;
516 }
517}
518
519static void mlxsw_sx_port_get_stats(struct net_device *dev,
520 struct ethtool_stats *stats, u64 *data)
521{
522 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
523 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
524 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
525 int i;
526 int err;
527
528 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
529 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
530 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
531 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
532 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
533}
534
535static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
536{
537 switch (sset) {
538 case ETH_SS_STATS:
539 return MLXSW_SX_PORT_HW_STATS_LEN;
540 default:
541 return -EOPNOTSUPP;
542 }
543}
544
545struct mlxsw_sx_port_link_mode {
546 u32 mask;
547 u32 supported;
548 u32 advertised;
549 u32 speed;
550};
551
552static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
553 {
554 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
555 .supported = SUPPORTED_100baseT_Full,
556 .advertised = ADVERTISED_100baseT_Full,
557 .speed = 100,
558 },
559 {
560 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
561 .speed = 100,
562 },
563 {
564 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
565 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
566 .supported = SUPPORTED_1000baseKX_Full,
567 .advertised = ADVERTISED_1000baseKX_Full,
568 .speed = 1000,
569 },
570 {
571 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
572 .supported = SUPPORTED_10000baseT_Full,
573 .advertised = ADVERTISED_10000baseT_Full,
574 .speed = 10000,
575 },
576 {
577 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
578 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
579 .supported = SUPPORTED_10000baseKX4_Full,
580 .advertised = ADVERTISED_10000baseKX4_Full,
581 .speed = 10000,
582 },
583 {
584 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
585 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
586 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
587 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
588 .supported = SUPPORTED_10000baseKR_Full,
589 .advertised = ADVERTISED_10000baseKR_Full,
590 .speed = 10000,
591 },
592 {
593 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
594 .supported = SUPPORTED_20000baseKR2_Full,
595 .advertised = ADVERTISED_20000baseKR2_Full,
596 .speed = 20000,
597 },
598 {
599 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
600 .supported = SUPPORTED_40000baseCR4_Full,
601 .advertised = ADVERTISED_40000baseCR4_Full,
602 .speed = 40000,
603 },
604 {
605 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
606 .supported = SUPPORTED_40000baseKR4_Full,
607 .advertised = ADVERTISED_40000baseKR4_Full,
608 .speed = 40000,
609 },
610 {
611 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
612 .supported = SUPPORTED_40000baseSR4_Full,
613 .advertised = ADVERTISED_40000baseSR4_Full,
614 .speed = 40000,
615 },
616 {
617 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
618 .supported = SUPPORTED_40000baseLR4_Full,
619 .advertised = ADVERTISED_40000baseLR4_Full,
620 .speed = 40000,
621 },
622 {
623 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
624 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
625 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
626 .speed = 25000,
627 },
628 {
629 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
630 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
631 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
632 .speed = 50000,
633 },
634 {
635 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
636 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
637 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
638 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
639 .speed = 100000,
640 },
641};
642
643#define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
644#define MLXSW_SX_PORT_BASE_SPEED 10000
645
646static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
647{
648 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
649 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
650 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
651 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
652 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
653 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
654 return SUPPORTED_FIBRE;
655
656 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
657 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
658 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
659 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
660 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
661 return SUPPORTED_Backplane;
662 return 0;
663}
664
665static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
666{
667 u32 modes = 0;
668 int i;
669
670 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
671 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
672 modes |= mlxsw_sx_port_link_mode[i].supported;
673 }
674 return modes;
675}
676
677static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
678{
679 u32 modes = 0;
680 int i;
681
682 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
683 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
684 modes |= mlxsw_sx_port_link_mode[i].advertised;
685 }
686 return modes;
687}
688
689static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
690 struct ethtool_link_ksettings *cmd)
691{
692 u32 speed = SPEED_UNKNOWN;
693 u8 duplex = DUPLEX_UNKNOWN;
694 int i;
695
696 if (!carrier_ok)
697 goto out;
698
699 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
700 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
701 speed = mlxsw_sx_port_link_mode[i].speed;
702 duplex = DUPLEX_FULL;
703 break;
704 }
705 }
706out:
707 cmd->base.speed = speed;
708 cmd->base.duplex = duplex;
709}
710
711static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
712{
713 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
714 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
715 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
716 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
717 return PORT_FIBRE;
718
719 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
720 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
721 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
722 return PORT_DA;
723
724 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
725 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
726 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
727 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
728 return PORT_NONE;
729
730 return PORT_OTHER;
731}
732
733static int
734mlxsw_sx_port_get_link_ksettings(struct net_device *dev,
735 struct ethtool_link_ksettings *cmd)
736{
737 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
738 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
739 char ptys_pl[MLXSW_REG_PTYS_LEN];
740 u32 eth_proto_cap;
741 u32 eth_proto_admin;
742 u32 eth_proto_oper;
743 u32 supported, advertising, lp_advertising;
744 int err;
745
746 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
747 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
748 if (err) {
749 netdev_err(dev, "Failed to get proto");
750 return err;
751 }
752 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap,
753 ð_proto_admin, ð_proto_oper);
754
755 supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
756 mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
757 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
758 advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
759 mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
760 eth_proto_oper, cmd);
761
762 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
763 cmd->base.port = mlxsw_sx_port_connector_port(eth_proto_oper);
764 lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
765
766 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
767 supported);
768 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
769 advertising);
770 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
771 lp_advertising);
772
773 return 0;
774}
775
776static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
777{
778 u32 ptys_proto = 0;
779 int i;
780
781 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
782 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
783 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
784 }
785 return ptys_proto;
786}
787
788static u32 mlxsw_sx_to_ptys_speed(u32 speed)
789{
790 u32 ptys_proto = 0;
791 int i;
792
793 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
794 if (speed == mlxsw_sx_port_link_mode[i].speed)
795 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
796 }
797 return ptys_proto;
798}
799
800static u32 mlxsw_sx_to_ptys_upper_speed(u32 upper_speed)
801{
802 u32 ptys_proto = 0;
803 int i;
804
805 for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
806 if (mlxsw_sx_port_link_mode[i].speed <= upper_speed)
807 ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
808 }
809 return ptys_proto;
810}
811
812static int
813mlxsw_sx_port_set_link_ksettings(struct net_device *dev,
814 const struct ethtool_link_ksettings *cmd)
815{
816 struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
817 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
818 char ptys_pl[MLXSW_REG_PTYS_LEN];
819 u32 speed;
820 u32 eth_proto_new;
821 u32 eth_proto_cap;
822 u32 eth_proto_admin;
823 u32 advertising;
824 bool is_up;
825 int err;
826
827 speed = cmd->base.speed;
828
829 ethtool_convert_link_mode_to_legacy_u32(&advertising,
830 cmd->link_modes.advertising);
831
832 eth_proto_new = cmd->base.autoneg == AUTONEG_ENABLE ?
833 mlxsw_sx_to_ptys_advert_link(advertising) :
834 mlxsw_sx_to_ptys_speed(speed);
835
836 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port, 0, false);
837 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
838 if (err) {
839 netdev_err(dev, "Failed to get proto");
840 return err;
841 }
842 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin,
843 NULL);
844
845 eth_proto_new = eth_proto_new & eth_proto_cap;
846 if (!eth_proto_new) {
847 netdev_err(dev, "Not supported proto admin requested");
848 return -EINVAL;
849 }
850 if (eth_proto_new == eth_proto_admin)
851 return 0;
852
853 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
854 eth_proto_new, true);
855 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
856 if (err) {
857 netdev_err(dev, "Failed to set proto admin");
858 return err;
859 }
860
861 err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
862 if (err) {
863 netdev_err(dev, "Failed to get oper status");
864 return err;
865 }
866 if (!is_up)
867 return 0;
868
869 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
870 if (err) {
871 netdev_err(dev, "Failed to set admin status");
872 return err;
873 }
874
875 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
876 if (err) {
877 netdev_err(dev, "Failed to set admin status");
878 return err;
879 }
880
881 return 0;
882}
883
884static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
885 .get_drvinfo = mlxsw_sx_port_get_drvinfo,
886 .get_link = ethtool_op_get_link,
887 .get_strings = mlxsw_sx_port_get_strings,
888 .get_ethtool_stats = mlxsw_sx_port_get_stats,
889 .get_sset_count = mlxsw_sx_port_get_sset_count,
890 .get_link_ksettings = mlxsw_sx_port_get_link_ksettings,
891 .set_link_ksettings = mlxsw_sx_port_set_link_ksettings,
892};
893
894static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
895{
896 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
897 int err;
898
899 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
900 if (err)
901 return err;
902 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
903 return 0;
904}
905
906static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
907{
908 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
909 struct net_device *dev = mlxsw_sx_port->dev;
910 char ppad_pl[MLXSW_REG_PPAD_LEN];
911 int err;
912
913 mlxsw_reg_ppad_pack(ppad_pl, false, 0);
914 err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
915 if (err)
916 return err;
917 mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
918
919
920
921
922 dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
923 return 0;
924}
925
926static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
927 u16 vid, enum mlxsw_reg_spms_state state)
928{
929 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
930 char *spms_pl;
931 int err;
932
933 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
934 if (!spms_pl)
935 return -ENOMEM;
936 mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
937 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
938 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
939 kfree(spms_pl);
940 return err;
941}
942
943static int mlxsw_sx_port_ib_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
944 u16 speed, u16 width)
945{
946 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
947 char ptys_pl[MLXSW_REG_PTYS_LEN];
948
949 mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sx_port->local_port, speed,
950 width);
951 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
952}
953
954static int
955mlxsw_sx_port_speed_by_width_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 width)
956{
957 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
958 u32 upper_speed = MLXSW_SX_PORT_BASE_SPEED * width;
959 char ptys_pl[MLXSW_REG_PTYS_LEN];
960 u32 eth_proto_admin;
961
962 eth_proto_admin = mlxsw_sx_to_ptys_upper_speed(upper_speed);
963 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sx_port->local_port,
964 eth_proto_admin, true);
965 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
966}
967
968static int
969mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
970 enum mlxsw_reg_spmlr_learn_mode mode)
971{
972 struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
973 char spmlr_pl[MLXSW_REG_SPMLR_LEN];
974
975 mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
976 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
977}
978
979static int __mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
980 u8 module, u8 width)
981{
982 struct mlxsw_sx_port *mlxsw_sx_port;
983 struct net_device *dev;
984 int err;
985
986 dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
987 if (!dev)
988 return -ENOMEM;
989 SET_NETDEV_DEV(dev, mlxsw_sx->bus_info->dev);
990 dev_net_set(dev, mlxsw_core_net(mlxsw_sx->core));
991 mlxsw_sx_port = netdev_priv(dev);
992 mlxsw_sx_port->dev = dev;
993 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
994 mlxsw_sx_port->local_port = local_port;
995 mlxsw_sx_port->mapping.module = module;
996
997 mlxsw_sx_port->pcpu_stats =
998 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
999 if (!mlxsw_sx_port->pcpu_stats) {
1000 err = -ENOMEM;
1001 goto err_alloc_stats;
1002 }
1003
1004 dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
1005 dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
1006
1007 err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
1008 if (err) {
1009 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
1010 mlxsw_sx_port->local_port);
1011 goto err_dev_addr_get;
1012 }
1013
1014 netif_carrier_off(dev);
1015
1016 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1017 NETIF_F_VLAN_CHALLENGED;
1018
1019 dev->min_mtu = 0;
1020 dev->max_mtu = ETH_MAX_MTU;
1021
1022
1023
1024
1025 dev->needed_headroom = MLXSW_TXHDR_LEN;
1026
1027 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1028 if (err) {
1029 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1030 mlxsw_sx_port->local_port);
1031 goto err_port_system_port_mapping_set;
1032 }
1033
1034 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1035 if (err) {
1036 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1037 mlxsw_sx_port->local_port);
1038 goto err_port_swid_set;
1039 }
1040
1041 err = mlxsw_sx_port_speed_by_width_set(mlxsw_sx_port, width);
1042 if (err) {
1043 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1044 mlxsw_sx_port->local_port);
1045 goto err_port_speed_set;
1046 }
1047
1048 err = mlxsw_sx_port_mtu_eth_set(mlxsw_sx_port, ETH_DATA_LEN);
1049 if (err) {
1050 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1051 mlxsw_sx_port->local_port);
1052 goto err_port_mtu_set;
1053 }
1054
1055 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1056 if (err)
1057 goto err_port_admin_status_set;
1058
1059 err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1060 MLXSW_PORT_DEFAULT_VID,
1061 MLXSW_REG_SPMS_STATE_FORWARDING);
1062 if (err) {
1063 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1064 mlxsw_sx_port->local_port);
1065 goto err_port_stp_state_set;
1066 }
1067
1068 err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1069 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1070 if (err) {
1071 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1072 mlxsw_sx_port->local_port);
1073 goto err_port_mac_learning_mode_set;
1074 }
1075
1076 err = register_netdev(dev);
1077 if (err) {
1078 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1079 mlxsw_sx_port->local_port);
1080 goto err_register_netdev;
1081 }
1082
1083 mlxsw_core_port_eth_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1084 mlxsw_sx_port, dev);
1085 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1086 return 0;
1087
1088err_register_netdev:
1089err_port_mac_learning_mode_set:
1090err_port_stp_state_set:
1091err_port_admin_status_set:
1092err_port_mtu_set:
1093err_port_speed_set:
1094 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1095err_port_swid_set:
1096err_port_system_port_mapping_set:
1097err_dev_addr_get:
1098 free_percpu(mlxsw_sx_port->pcpu_stats);
1099err_alloc_stats:
1100 free_netdev(dev);
1101 return err;
1102}
1103
1104static int mlxsw_sx_port_eth_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1105 u8 module, u8 width)
1106{
1107 int err;
1108
1109 err = mlxsw_core_port_init(mlxsw_sx->core, local_port,
1110 module + 1, false, 0, false, 0,
1111 mlxsw_sx->hw_id, sizeof(mlxsw_sx->hw_id));
1112 if (err) {
1113 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1114 local_port);
1115 return err;
1116 }
1117 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module, width);
1118 if (err)
1119 goto err_port_create;
1120
1121 return 0;
1122
1123err_port_create:
1124 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1125 return err;
1126}
1127
1128static void __mlxsw_sx_port_eth_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1129{
1130 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1131
1132 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1133 unregister_netdev(mlxsw_sx_port->dev);
1134 mlxsw_sx->ports[local_port] = NULL;
1135 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1136 free_percpu(mlxsw_sx_port->pcpu_stats);
1137 free_netdev(mlxsw_sx_port->dev);
1138}
1139
1140static bool mlxsw_sx_port_created(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1141{
1142 return mlxsw_sx->ports[local_port] != NULL;
1143}
1144
1145static int __mlxsw_sx_port_ib_create(struct mlxsw_sx *mlxsw_sx, u8 local_port,
1146 u8 module, u8 width)
1147{
1148 struct mlxsw_sx_port *mlxsw_sx_port;
1149 int err;
1150
1151 mlxsw_sx_port = kzalloc(sizeof(*mlxsw_sx_port), GFP_KERNEL);
1152 if (!mlxsw_sx_port)
1153 return -ENOMEM;
1154 mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
1155 mlxsw_sx_port->local_port = local_port;
1156 mlxsw_sx_port->mapping.module = module;
1157
1158 err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1159 if (err) {
1160 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1161 mlxsw_sx_port->local_port);
1162 goto err_port_system_port_mapping_set;
1163 }
1164
1165
1166 err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 1);
1167 if (err) {
1168 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1169 mlxsw_sx_port->local_port);
1170 goto err_port_swid_set;
1171 }
1172
1173
1174 err = mlxsw_sx_port_ib_port_set(mlxsw_sx_port, module + 1);
1175 if (err) {
1176 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set IB port\n",
1177 mlxsw_sx_port->local_port);
1178 goto err_port_ib_set;
1179 }
1180
1181
1182
1183
1184 err = mlxsw_sx_port_ib_speed_set(mlxsw_sx_port,
1185 MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
1186 BIT(3) - 1);
1187 if (err) {
1188 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1189 mlxsw_sx_port->local_port);
1190 goto err_port_speed_set;
1191 }
1192
1193
1194
1195
1196 err = mlxsw_sx_port_mtu_ib_set(mlxsw_sx_port, MLXSW_IB_DEFAULT_MTU);
1197 if (err) {
1198 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1199 mlxsw_sx_port->local_port);
1200 goto err_port_mtu_set;
1201 }
1202
1203 err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
1204 if (err) {
1205 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
1206 mlxsw_sx_port->local_port);
1207 goto err_port_admin_set;
1208 }
1209
1210 mlxsw_core_port_ib_set(mlxsw_sx->core, mlxsw_sx_port->local_port,
1211 mlxsw_sx_port);
1212 mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1213 return 0;
1214
1215err_port_admin_set:
1216err_port_mtu_set:
1217err_port_speed_set:
1218err_port_ib_set:
1219 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1220err_port_swid_set:
1221err_port_system_port_mapping_set:
1222 kfree(mlxsw_sx_port);
1223 return err;
1224}
1225
1226static void __mlxsw_sx_port_ib_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1227{
1228 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1229
1230 mlxsw_core_port_clear(mlxsw_sx->core, local_port, mlxsw_sx);
1231 mlxsw_sx->ports[local_port] = NULL;
1232 mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1233 mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1234 kfree(mlxsw_sx_port);
1235}
1236
1237static void __mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1238{
1239 enum devlink_port_type port_type =
1240 mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1241
1242 if (port_type == DEVLINK_PORT_TYPE_ETH)
1243 __mlxsw_sx_port_eth_remove(mlxsw_sx, local_port);
1244 else if (port_type == DEVLINK_PORT_TYPE_IB)
1245 __mlxsw_sx_port_ib_remove(mlxsw_sx, local_port);
1246}
1247
1248static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1249{
1250 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1251 mlxsw_core_port_fini(mlxsw_sx->core, local_port);
1252}
1253
1254static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1255{
1256 int i;
1257
1258 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sx->core); i++)
1259 if (mlxsw_sx_port_created(mlxsw_sx, i))
1260 mlxsw_sx_port_remove(mlxsw_sx, i);
1261 kfree(mlxsw_sx->ports);
1262 mlxsw_sx->ports = NULL;
1263}
1264
1265static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1266{
1267 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sx->core);
1268 size_t alloc_size;
1269 u8 module, width;
1270 int i;
1271 int err;
1272
1273 alloc_size = sizeof(struct mlxsw_sx_port *) * max_ports;
1274 mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1275 if (!mlxsw_sx->ports)
1276 return -ENOMEM;
1277
1278 for (i = 1; i < max_ports; i++) {
1279 err = mlxsw_sx_port_module_info_get(mlxsw_sx, i, &module,
1280 &width);
1281 if (err)
1282 goto err_port_module_info_get;
1283 if (!width)
1284 continue;
1285 err = mlxsw_sx_port_eth_create(mlxsw_sx, i, module, width);
1286 if (err)
1287 goto err_port_create;
1288 }
1289 return 0;
1290
1291err_port_create:
1292err_port_module_info_get:
1293 for (i--; i >= 1; i--)
1294 if (mlxsw_sx_port_created(mlxsw_sx, i))
1295 mlxsw_sx_port_remove(mlxsw_sx, i);
1296 kfree(mlxsw_sx->ports);
1297 mlxsw_sx->ports = NULL;
1298 return err;
1299}
1300
1301static void mlxsw_sx_pude_eth_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1302 enum mlxsw_reg_pude_oper_status status)
1303{
1304 if (status == MLXSW_PORT_OPER_STATUS_UP) {
1305 netdev_info(mlxsw_sx_port->dev, "link up\n");
1306 netif_carrier_on(mlxsw_sx_port->dev);
1307 } else {
1308 netdev_info(mlxsw_sx_port->dev, "link down\n");
1309 netif_carrier_off(mlxsw_sx_port->dev);
1310 }
1311}
1312
1313static void mlxsw_sx_pude_ib_event_func(struct mlxsw_sx_port *mlxsw_sx_port,
1314 enum mlxsw_reg_pude_oper_status status)
1315{
1316 if (status == MLXSW_PORT_OPER_STATUS_UP)
1317 pr_info("ib link for port %d - up\n",
1318 mlxsw_sx_port->mapping.module + 1);
1319 else
1320 pr_info("ib link for port %d - down\n",
1321 mlxsw_sx_port->mapping.module + 1);
1322}
1323
1324static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1325 char *pude_pl, void *priv)
1326{
1327 struct mlxsw_sx *mlxsw_sx = priv;
1328 struct mlxsw_sx_port *mlxsw_sx_port;
1329 enum mlxsw_reg_pude_oper_status status;
1330 enum devlink_port_type port_type;
1331 u8 local_port;
1332
1333 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1334 mlxsw_sx_port = mlxsw_sx->ports[local_port];
1335 if (!mlxsw_sx_port) {
1336 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1337 local_port);
1338 return;
1339 }
1340
1341 status = mlxsw_reg_pude_oper_status_get(pude_pl);
1342 port_type = mlxsw_core_port_type_get(mlxsw_sx->core, local_port);
1343 if (port_type == DEVLINK_PORT_TYPE_ETH)
1344 mlxsw_sx_pude_eth_event_func(mlxsw_sx_port, status);
1345 else if (port_type == DEVLINK_PORT_TYPE_IB)
1346 mlxsw_sx_pude_ib_event_func(mlxsw_sx_port, status);
1347}
1348
1349static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1350 void *priv)
1351{
1352 struct mlxsw_sx *mlxsw_sx = priv;
1353 struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1354 struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1355
1356 if (unlikely(!mlxsw_sx_port)) {
1357 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1358 local_port);
1359 return;
1360 }
1361
1362 skb->dev = mlxsw_sx_port->dev;
1363
1364 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1365 u64_stats_update_begin(&pcpu_stats->syncp);
1366 pcpu_stats->rx_packets++;
1367 pcpu_stats->rx_bytes += skb->len;
1368 u64_stats_update_end(&pcpu_stats->syncp);
1369
1370 skb->protocol = eth_type_trans(skb, skb->dev);
1371 netif_receive_skb(skb);
1372}
1373
1374static int mlxsw_sx_port_type_set(struct mlxsw_core *mlxsw_core, u8 local_port,
1375 enum devlink_port_type new_type)
1376{
1377 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1378 u8 module, width;
1379 int err;
1380
1381 if (!mlxsw_sx->ports || !mlxsw_sx->ports[local_port]) {
1382 dev_err(mlxsw_sx->bus_info->dev, "Port number \"%d\" does not exist\n",
1383 local_port);
1384 return -EINVAL;
1385 }
1386
1387 if (new_type == DEVLINK_PORT_TYPE_AUTO)
1388 return -EOPNOTSUPP;
1389
1390 __mlxsw_sx_port_remove(mlxsw_sx, local_port);
1391 err = mlxsw_sx_port_module_info_get(mlxsw_sx, local_port, &module,
1392 &width);
1393 if (err)
1394 goto err_port_module_info_get;
1395
1396 if (new_type == DEVLINK_PORT_TYPE_ETH)
1397 err = __mlxsw_sx_port_eth_create(mlxsw_sx, local_port, module,
1398 width);
1399 else if (new_type == DEVLINK_PORT_TYPE_IB)
1400 err = __mlxsw_sx_port_ib_create(mlxsw_sx, local_port, module,
1401 width);
1402
1403err_port_module_info_get:
1404 return err;
1405}
1406
1407enum {
1408 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX = 1,
1409 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL = 2,
1410};
1411
1412#define MLXSW_SX_RXL(_trap_id) \
1413 MLXSW_RXL(mlxsw_sx_rx_listener_func, _trap_id, TRAP_TO_CPU, \
1414 false, SX2_RX, FORWARD)
1415
1416static const struct mlxsw_listener mlxsw_sx_listener[] = {
1417 MLXSW_EVENTL(mlxsw_sx_pude_event_func, PUDE, EMAD),
1418 MLXSW_SX_RXL(FDB_MC),
1419 MLXSW_SX_RXL(STP),
1420 MLXSW_SX_RXL(LACP),
1421 MLXSW_SX_RXL(EAPOL),
1422 MLXSW_SX_RXL(LLDP),
1423 MLXSW_SX_RXL(MMRP),
1424 MLXSW_SX_RXL(MVRP),
1425 MLXSW_SX_RXL(RPVST),
1426 MLXSW_SX_RXL(DHCP),
1427 MLXSW_SX_RXL(IGMP_QUERY),
1428 MLXSW_SX_RXL(IGMP_V1_REPORT),
1429 MLXSW_SX_RXL(IGMP_V2_REPORT),
1430 MLXSW_SX_RXL(IGMP_V2_LEAVE),
1431 MLXSW_SX_RXL(IGMP_V3_REPORT),
1432};
1433
1434static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1435{
1436 char htgt_pl[MLXSW_REG_HTGT_LEN];
1437 int i;
1438 int err;
1439
1440 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
1441 MLXSW_REG_HTGT_INVALID_POLICER,
1442 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1443 MLXSW_REG_HTGT_DEFAULT_TC);
1444 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1445 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX);
1446
1447 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1448 if (err)
1449 return err;
1450
1451 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
1452 MLXSW_REG_HTGT_INVALID_POLICER,
1453 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1454 MLXSW_REG_HTGT_DEFAULT_TC);
1455 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1456 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL);
1457
1458 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1459 if (err)
1460 return err;
1461
1462 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1463 err = mlxsw_core_trap_register(mlxsw_sx->core,
1464 &mlxsw_sx_listener[i],
1465 mlxsw_sx);
1466 if (err)
1467 goto err_listener_register;
1468
1469 }
1470 return 0;
1471
1472err_listener_register:
1473 for (i--; i >= 0; i--) {
1474 mlxsw_core_trap_unregister(mlxsw_sx->core,
1475 &mlxsw_sx_listener[i],
1476 mlxsw_sx);
1477 }
1478 return err;
1479}
1480
1481static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1482{
1483 int i;
1484
1485 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_listener); i++) {
1486 mlxsw_core_trap_unregister(mlxsw_sx->core,
1487 &mlxsw_sx_listener[i],
1488 mlxsw_sx);
1489 }
1490}
1491
1492static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1493{
1494 char sfgc_pl[MLXSW_REG_SFGC_LEN];
1495 char sgcr_pl[MLXSW_REG_SGCR_LEN];
1496 char *sftr_pl;
1497 int err;
1498
1499
1500 sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1501 if (!sftr_pl)
1502 return -ENOMEM;
1503 mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1504 MLXSW_PORT_CPU_PORT, true);
1505 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1506 kfree(sftr_pl);
1507 if (err)
1508 return err;
1509
1510
1511 mlxsw_reg_sfgc_pack(sfgc_pl,
1512 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1513 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1514 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1515 0);
1516 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1517 if (err)
1518 return err;
1519
1520 mlxsw_reg_sfgc_pack(sfgc_pl,
1521 MLXSW_REG_SFGC_TYPE_BROADCAST,
1522 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1523 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1524 0);
1525 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1526 if (err)
1527 return err;
1528
1529 mlxsw_reg_sfgc_pack(sfgc_pl,
1530 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1531 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1532 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1533 0);
1534 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1535 if (err)
1536 return err;
1537
1538 mlxsw_reg_sfgc_pack(sfgc_pl,
1539 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1540 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1541 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1542 0);
1543 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1544 if (err)
1545 return err;
1546
1547 mlxsw_reg_sfgc_pack(sfgc_pl,
1548 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1549 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1550 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1551 0);
1552 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1553 if (err)
1554 return err;
1555
1556 mlxsw_reg_sgcr_pack(sgcr_pl, true);
1557 return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1558}
1559
1560static int mlxsw_sx_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
1561{
1562 char htgt_pl[MLXSW_REG_HTGT_LEN];
1563
1564 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1565 MLXSW_REG_HTGT_INVALID_POLICER,
1566 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
1567 MLXSW_REG_HTGT_DEFAULT_TC);
1568 mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
1569 mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
1570 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD);
1571 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
1572}
1573
1574static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1575 const struct mlxsw_bus_info *mlxsw_bus_info,
1576 struct netlink_ext_ack *extack)
1577{
1578 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1579 int err;
1580
1581 mlxsw_sx->core = mlxsw_core;
1582 mlxsw_sx->bus_info = mlxsw_bus_info;
1583
1584 err = mlxsw_sx_hw_id_get(mlxsw_sx);
1585 if (err) {
1586 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1587 return err;
1588 }
1589
1590 err = mlxsw_sx_ports_create(mlxsw_sx);
1591 if (err) {
1592 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1593 return err;
1594 }
1595
1596 err = mlxsw_sx_traps_init(mlxsw_sx);
1597 if (err) {
1598 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps\n");
1599 goto err_listener_register;
1600 }
1601
1602 err = mlxsw_sx_flood_init(mlxsw_sx);
1603 if (err) {
1604 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1605 goto err_flood_init;
1606 }
1607
1608 return 0;
1609
1610err_flood_init:
1611 mlxsw_sx_traps_fini(mlxsw_sx);
1612err_listener_register:
1613 mlxsw_sx_ports_remove(mlxsw_sx);
1614 return err;
1615}
1616
1617static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1618{
1619 struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1620
1621 mlxsw_sx_traps_fini(mlxsw_sx);
1622 mlxsw_sx_ports_remove(mlxsw_sx);
1623}
1624
1625static const struct mlxsw_config_profile mlxsw_sx_config_profile = {
1626 .used_max_vepa_channels = 1,
1627 .max_vepa_channels = 0,
1628 .used_max_mid = 1,
1629 .max_mid = 7000,
1630 .used_max_pgt = 1,
1631 .max_pgt = 0,
1632 .used_max_system_port = 1,
1633 .max_system_port = 48000,
1634 .used_max_vlan_groups = 1,
1635 .max_vlan_groups = 127,
1636 .used_max_regions = 1,
1637 .max_regions = 400,
1638 .used_flood_tables = 1,
1639 .max_flood_tables = 2,
1640 .max_vid_flood_tables = 1,
1641 .used_flood_mode = 1,
1642 .flood_mode = 3,
1643 .used_max_ib_mc = 1,
1644 .max_ib_mc = 6,
1645 .used_max_pkey = 1,
1646 .max_pkey = 0,
1647 .swid_config = {
1648 {
1649 .used_type = 1,
1650 .type = MLXSW_PORT_SWID_TYPE_ETH,
1651 },
1652 {
1653 .used_type = 1,
1654 .type = MLXSW_PORT_SWID_TYPE_IB,
1655 }
1656 },
1657};
1658
1659static struct mlxsw_driver mlxsw_sx_driver = {
1660 .kind = mlxsw_sx_driver_name,
1661 .priv_size = sizeof(struct mlxsw_sx),
1662 .init = mlxsw_sx_init,
1663 .fini = mlxsw_sx_fini,
1664 .basic_trap_groups_set = mlxsw_sx_basic_trap_groups_set,
1665 .txhdr_construct = mlxsw_sx_txhdr_construct,
1666 .txhdr_len = MLXSW_TXHDR_LEN,
1667 .profile = &mlxsw_sx_config_profile,
1668 .port_type_set = mlxsw_sx_port_type_set,
1669};
1670
1671static const struct pci_device_id mlxsw_sx_pci_id_table[] = {
1672 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHX2), 0},
1673 {0, },
1674};
1675
1676static struct pci_driver mlxsw_sx_pci_driver = {
1677 .name = mlxsw_sx_driver_name,
1678 .id_table = mlxsw_sx_pci_id_table,
1679};
1680
1681static int __init mlxsw_sx_module_init(void)
1682{
1683 int err;
1684
1685 err = mlxsw_core_driver_register(&mlxsw_sx_driver);
1686 if (err)
1687 return err;
1688
1689 err = mlxsw_pci_driver_register(&mlxsw_sx_pci_driver);
1690 if (err)
1691 goto err_pci_driver_register;
1692
1693 return 0;
1694
1695err_pci_driver_register:
1696 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1697 return err;
1698}
1699
1700static void __exit mlxsw_sx_module_exit(void)
1701{
1702 mlxsw_pci_driver_unregister(&mlxsw_sx_pci_driver);
1703 mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1704}
1705
1706module_init(mlxsw_sx_module_init);
1707module_exit(mlxsw_sx_module_exit);
1708
1709MODULE_LICENSE("Dual BSD/GPL");
1710MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1711MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1712MODULE_DEVICE_TABLE(pci, mlxsw_sx_pci_id_table);
1713
