1
2
3
4#ifndef _IONIC_LIF_H_
5#define _IONIC_LIF_H_
6
7#include <linux/pci.h>
8#include "ionic_rx_filter.h"
9
10#define IONIC_ADMINQ_LENGTH 16
11#define IONIC_NOTIFYQ_LENGTH 64
12
13#define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1)
14#define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1)
15#define IONIC_RX_COPYBREAK_DEFAULT 256
16#define IONIC_TX_BUDGET_DEFAULT 256
17
18struct ionic_tx_stats {
19 u64 dma_map_err;
20 u64 pkts;
21 u64 bytes;
22 u64 clean;
23 u64 linearize;
24 u64 csum_none;
25 u64 csum;
26 u64 crc32_csum;
27 u64 tso;
28 u64 tso_bytes;
29 u64 frags;
30 u64 vlan_inserted;
31 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR];
32};
33
34struct ionic_rx_stats {
35 u64 dma_map_err;
36 u64 alloc_err;
37 u64 pkts;
38 u64 bytes;
39 u64 csum_none;
40 u64 csum_complete;
41 u64 csum_error;
42 u64 buffers_posted;
43 u64 dropped;
44 u64 vlan_stripped;
45};
46
47#define IONIC_QCQ_F_INITED BIT(0)
48#define IONIC_QCQ_F_SG BIT(1)
49#define IONIC_QCQ_F_INTR BIT(2)
50#define IONIC_QCQ_F_TX_STATS BIT(3)
51#define IONIC_QCQ_F_RX_STATS BIT(4)
52#define IONIC_QCQ_F_NOTIFYQ BIT(5)
53
54struct ionic_napi_stats {
55 u64 poll_count;
56 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR];
57};
58
59struct ionic_q_stats {
60 union {
61 struct ionic_tx_stats tx;
62 struct ionic_rx_stats rx;
63 };
64};
65
66struct ionic_qcq {
67 void *base;
68 dma_addr_t base_pa;
69 unsigned int total_size;
70 struct ionic_queue q;
71 struct ionic_cq cq;
72 struct ionic_intr_info intr;
73 struct napi_struct napi;
74 struct ionic_napi_stats napi_stats;
75 struct ionic_q_stats *stats;
76 unsigned int flags;
77 struct dentry *dentry;
78};
79
80struct ionic_qcqst {
81 struct ionic_qcq *qcq;
82 struct ionic_q_stats *stats;
83};
84
85#define q_to_qcq(q) container_of(q, struct ionic_qcq, q)
86#define q_to_tx_stats(q) (&q_to_qcq(q)->stats->tx)
87#define q_to_rx_stats(q) (&q_to_qcq(q)->stats->rx)
88#define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi)
89#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
90
91enum ionic_deferred_work_type {
92 IONIC_DW_TYPE_RX_MODE,
93 IONIC_DW_TYPE_RX_ADDR_ADD,
94 IONIC_DW_TYPE_RX_ADDR_DEL,
95 IONIC_DW_TYPE_LINK_STATUS,
96 IONIC_DW_TYPE_LIF_RESET,
97};
98
99struct ionic_deferred_work {
100 struct list_head list;
101 enum ionic_deferred_work_type type;
102 union {
103 unsigned int rx_mode;
104 u8 addr[ETH_ALEN];
105 u8 fw_status;
106 };
107};
108
109struct ionic_deferred {
110 spinlock_t lock;
111 struct list_head list;
112 struct work_struct work;
113};
114
115struct ionic_lif_sw_stats {
116 u64 tx_packets;
117 u64 tx_bytes;
118 u64 rx_packets;
119 u64 rx_bytes;
120 u64 tx_tso;
121 u64 tx_tso_bytes;
122 u64 tx_csum_none;
123 u64 tx_csum;
124 u64 rx_csum_none;
125 u64 rx_csum_complete;
126 u64 rx_csum_error;
127 u64 hw_tx_dropped;
128 u64 hw_rx_dropped;
129 u64 hw_rx_over_errors;
130 u64 hw_rx_missed_errors;
131 u64 hw_tx_aborted_errors;
132};
133
134enum ionic_lif_state_flags {
135 IONIC_LIF_F_INITED,
136 IONIC_LIF_F_SW_DEBUG_STATS,
137 IONIC_LIF_F_UP,
138 IONIC_LIF_F_LINK_CHECK_REQUESTED,
139 IONIC_LIF_F_FW_RESET,
140 IONIC_LIF_F_SPLIT_INTR,
141
142
143 IONIC_LIF_F_STATE_SIZE
144};
145
146struct ionic_qtype_info {
147 u8 version;
148 u8 supported;
149 u64 features;
150 u16 desc_sz;
151 u16 comp_sz;
152 u16 sg_desc_sz;
153 u16 max_sg_elems;
154 u16 sg_desc_stride;
155};
156
157#define IONIC_LIF_NAME_MAX_SZ 32
158struct ionic_lif {
159 char name[IONIC_LIF_NAME_MAX_SZ];
160 struct list_head list;
161 struct net_device *netdev;
162 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE);
163 struct ionic *ionic;
164 bool registered;
165 unsigned int index;
166 unsigned int hw_index;
167 unsigned int kern_pid;
168 u64 __iomem *kern_dbpage;
169 struct mutex queue_lock;
170 spinlock_t adminq_lock;
171 struct ionic_qcq *adminqcq;
172 struct ionic_qcq *notifyqcq;
173 struct ionic_qcqst *txqcqs;
174 struct ionic_qcqst *rxqcqs;
175 u64 last_eid;
176 unsigned int neqs;
177 unsigned int nxqs;
178 unsigned int ntxq_descs;
179 unsigned int nrxq_descs;
180 u32 rx_copybreak;
181 u32 tx_budget;
182 unsigned int rx_mode;
183 u64 hw_features;
184 bool mc_overflow;
185 unsigned int nmcast;
186 bool uc_overflow;
187 u16 lif_type;
188 unsigned int nucast;
189
190 union ionic_lif_identity *identity;
191 struct ionic_lif_info *info;
192 dma_addr_t info_pa;
193 u32 info_sz;
194 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX];
195
196 u16 rss_types;
197 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE];
198 u8 *rss_ind_tbl;
199 dma_addr_t rss_ind_tbl_pa;
200 u32 rss_ind_tbl_sz;
201
202 struct ionic_rx_filters rx_filters;
203 struct ionic_deferred deferred;
204 unsigned long *dbid_inuse;
205 unsigned int dbid_count;
206 struct dentry *dentry;
207 u32 rx_coalesce_usecs;
208 u32 rx_coalesce_hw;
209 u32 tx_coalesce_usecs;
210 u32 tx_coalesce_hw;
211
212 struct work_struct tx_timeout_work;
213};
214
215#define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq)
216#define lif_to_rxqcq(lif, i) ((lif)->rxqcqs[i].qcq)
217#define lif_to_txstats(lif, i) ((lif)->txqcqs[i].stats->tx)
218#define lif_to_rxstats(lif, i) ((lif)->rxqcqs[i].stats->rx)
219#define lif_to_txq(lif, i) (&lif_to_txqcq((lif), i)->q)
220#define lif_to_rxq(lif, i) (&lif_to_txqcq((lif), i)->q)
221
222static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs)
223{
224 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult);
225 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div);
226
227
228 if (!div || !mult)
229 return 0;
230
231
232 usecs += (div / mult) >> 1;
233
234
235 return (usecs * mult) / div;
236}
237
238typedef void (*ionic_reset_cb)(struct ionic_lif *lif, void *arg);
239
240void ionic_link_status_check_request(struct ionic_lif *lif);
241void ionic_get_stats64(struct net_device *netdev,
242 struct rtnl_link_stats64 *ns);
243void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
244 struct ionic_deferred_work *work);
245int ionic_lifs_alloc(struct ionic *ionic);
246void ionic_lifs_free(struct ionic *ionic);
247void ionic_lifs_deinit(struct ionic *ionic);
248int ionic_lifs_init(struct ionic *ionic);
249int ionic_lifs_register(struct ionic *ionic);
250void ionic_lifs_unregister(struct ionic *ionic);
251int ionic_lif_identify(struct ionic *ionic, u8 lif_type,
252 union ionic_lif_identity *lif_ident);
253int ionic_lifs_size(struct ionic *ionic);
254int ionic_lif_rss_config(struct ionic_lif *lif, u16 types,
255 const u8 *key, const u32 *indir);
256
257int ionic_open(struct net_device *netdev);
258int ionic_stop(struct net_device *netdev);
259int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg);
260
261static inline void debug_stats_txq_post(struct ionic_qcq *qcq,
262 struct ionic_txq_desc *desc, bool dbell)
263{
264 u8 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT)
265 & IONIC_TXQ_DESC_NSGE_MASK);
266
267 qcq->q.dbell_count += dbell;
268
269 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1))
270 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1;
271
272 qcq->stats->tx.sg_cntr[num_sg_elems]++;
273}
274
275static inline void debug_stats_napi_poll(struct ionic_qcq *qcq,
276 unsigned int work_done)
277{
278 qcq->napi_stats.poll_count++;
279
280 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1))
281 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1;
282
283 qcq->napi_stats.work_done_cntr[work_done]++;
284}
285
286#define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++)
287#define DEBUG_STATS_RX_BUFF_CNT(qcq) ((qcq)->stats->rx.buffers_posted++)
288#define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++)
289#define DEBUG_STATS_TXQ_POST(qcq, txdesc, dbell) \
290 debug_stats_txq_post(qcq, txdesc, dbell)
291#define DEBUG_STATS_NAPI_POLL(qcq, work_done) \
292 debug_stats_napi_poll(qcq, work_done)
293
294#endif
295
