linux/drivers/net/ethernet/realtek/8139too.c
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   1/*
   2
   3        8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
   4
   5        Maintained by Jeff Garzik <jgarzik@pobox.com>
   6        Copyright 2000-2002 Jeff Garzik
   7
   8        Much code comes from Donald Becker's rtl8139.c driver,
   9        versions 1.13 and older.  This driver was originally based
  10        on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
  11
  12        -----<snip>-----
  13
  14                Written 1997-2001 by Donald Becker.
  15                This software may be used and distributed according to the
  16                terms of the GNU General Public License (GPL), incorporated
  17                herein by reference.  Drivers based on or derived from this
  18                code fall under the GPL and must retain the authorship,
  19                copyright and license notice.  This file is not a complete
  20                program and may only be used when the entire operating
  21                system is licensed under the GPL.
  22
  23                This driver is for boards based on the RTL8129 and RTL8139
  24                PCI ethernet chips.
  25
  26                The author may be reached as becker@scyld.com, or C/O Scyld
  27                Computing Corporation 410 Severn Ave., Suite 210 Annapolis
  28                MD 21403
  29
  30                Support and updates available at
  31                http://www.scyld.com/network/rtl8139.html
  32
  33                Twister-tuning table provided by Kinston
  34                <shangh@realtek.com.tw>.
  35
  36        -----<snip>-----
  37
  38        This software may be used and distributed according to the terms
  39        of the GNU General Public License, incorporated herein by reference.
  40
  41        Contributors:
  42
  43                Donald Becker - he wrote the original driver, kudos to him!
  44                (but please don't e-mail him for support, this isn't his driver)
  45
  46                Tigran Aivazian - bug fixes, skbuff free cleanup
  47
  48                Martin Mares - suggestions for PCI cleanup
  49
  50                David S. Miller - PCI DMA and softnet updates
  51
  52                Ernst Gill - fixes ported from BSD driver
  53
  54                Daniel Kobras - identified specific locations of
  55                        posted MMIO write bugginess
  56
  57                Gerard Sharp - bug fix, testing and feedback
  58
  59                David Ford - Rx ring wrap fix
  60
  61                Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
  62                to find and fix a crucial bug on older chipsets.
  63
  64                Donald Becker/Chris Butterworth/Marcus Westergren -
  65                Noticed various Rx packet size-related buglets.
  66
  67                Santiago Garcia Mantinan - testing and feedback
  68
  69                Jens David - 2.2.x kernel backports
  70
  71                Martin Dennett - incredibly helpful insight on undocumented
  72                features of the 8139 chips
  73
  74                Jean-Jacques Michel - bug fix
  75
  76                Tobias Ringström - Rx interrupt status checking suggestion
  77
  78                Andrew Morton - Clear blocked signals, avoid
  79                buffer overrun setting current->comm.
  80
  81                Kalle Olavi Niemitalo - Wake-on-LAN ioctls
  82
  83                Robert Kuebel - Save kernel thread from dying on any signal.
  84
  85        Submitting bug reports:
  86
  87                "rtl8139-diag -mmmaaavvveefN" output
  88                enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
  89
  90*/
  91
  92#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  93
  94#define DRV_NAME        "8139too"
  95#define DRV_VERSION     "0.9.28"
  96
  97
  98#include <linux/module.h>
  99#include <linux/kernel.h>
 100#include <linux/compiler.h>
 101#include <linux/pci.h>
 102#include <linux/init.h>
 103#include <linux/interrupt.h>
 104#include <linux/netdevice.h>
 105#include <linux/etherdevice.h>
 106#include <linux/rtnetlink.h>
 107#include <linux/delay.h>
 108#include <linux/ethtool.h>
 109#include <linux/mii.h>
 110#include <linux/completion.h>
 111#include <linux/crc32.h>
 112#include <linux/io.h>
 113#include <linux/uaccess.h>
 114#include <linux/gfp.h>
 115#include <linux/if_vlan.h>
 116#include <asm/irq.h>
 117
 118#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION
 119
 120/* Default Message level */
 121#define RTL8139_DEF_MSG_ENABLE   (NETIF_MSG_DRV   | \
 122                                 NETIF_MSG_PROBE  | \
 123                                 NETIF_MSG_LINK)
 124
 125
 126/* define to 1, 2 or 3 to enable copious debugging info */
 127#define RTL8139_DEBUG 0
 128
 129/* define to 1 to disable lightweight runtime debugging checks */
 130#undef RTL8139_NDEBUG
 131
 132
 133#ifdef RTL8139_NDEBUG
 134#  define assert(expr) do {} while (0)
 135#else
 136#  define assert(expr) \
 137        if (unlikely(!(expr))) {                                \
 138                pr_err("Assertion failed! %s,%s,%s,line=%d\n",  \
 139                       #expr, __FILE__, __func__, __LINE__);    \
 140        }
 141#endif
 142
 143
 144/* A few user-configurable values. */
 145/* media options */
 146#define MAX_UNITS 8
 147static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 148static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 149
 150/* Whether to use MMIO or PIO. Default to MMIO. */
 151#ifdef CONFIG_8139TOO_PIO
 152static bool use_io = true;
 153#else
 154static bool use_io = false;
 155#endif
 156
 157/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 158   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
 159static int multicast_filter_limit = 32;
 160
 161/* bitmapped message enable number */
 162static int debug = -1;
 163
 164/*
 165 * Receive ring size
 166 * Warning: 64K ring has hardware issues and may lock up.
 167 */
 168#if defined(CONFIG_SH_DREAMCAST)
 169#define RX_BUF_IDX 0    /* 8K ring */
 170#else
 171#define RX_BUF_IDX      2       /* 32K ring */
 172#endif
 173#define RX_BUF_LEN      (8192 << RX_BUF_IDX)
 174#define RX_BUF_PAD      16
 175#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
 176
 177#if RX_BUF_LEN == 65536
 178#define RX_BUF_TOT_LEN  RX_BUF_LEN
 179#else
 180#define RX_BUF_TOT_LEN  (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
 181#endif
 182
 183/* Number of Tx descriptor registers. */
 184#define NUM_TX_DESC     4
 185
 186/* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/
 187#define MAX_ETH_FRAME_SIZE      1792
 188
 189/* max supported payload size */
 190#define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN)
 191
 192/* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */
 193#define TX_BUF_SIZE     MAX_ETH_FRAME_SIZE
 194#define TX_BUF_TOT_LEN  (TX_BUF_SIZE * NUM_TX_DESC)
 195
 196/* PCI Tuning Parameters
 197   Threshold is bytes transferred to chip before transmission starts. */
 198#define TX_FIFO_THRESH 256      /* In bytes, rounded down to 32 byte units. */
 199
 200/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
 201#define RX_FIFO_THRESH  7       /* Rx buffer level before first PCI xfer.  */
 202#define RX_DMA_BURST    7       /* Maximum PCI burst, '6' is 1024 */
 203#define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 204#define TX_RETRY        8       /* 0-15.  retries = 16 + (TX_RETRY * 16) */
 205
 206/* Operational parameters that usually are not changed. */
 207/* Time in jiffies before concluding the transmitter is hung. */
 208#define TX_TIMEOUT  (6*HZ)
 209
 210
 211enum {
 212        HAS_MII_XCVR = 0x010000,
 213        HAS_CHIP_XCVR = 0x020000,
 214        HAS_LNK_CHNG = 0x040000,
 215};
 216
 217#define RTL_NUM_STATS 4         /* number of ETHTOOL_GSTATS u64's */
 218#define RTL_REGS_VER 1          /* version of reg. data in ETHTOOL_GREGS */
 219#define RTL_MIN_IO_SIZE 0x80
 220#define RTL8139B_IO_SIZE 256
 221
 222#define RTL8129_CAPS    HAS_MII_XCVR
 223#define RTL8139_CAPS    (HAS_CHIP_XCVR|HAS_LNK_CHNG)
 224
 225typedef enum {
 226        RTL8139 = 0,
 227        RTL8129,
 228} board_t;
 229
 230
 231/* indexed by board_t, above */
 232static const struct {
 233        const char *name;
 234        u32 hw_flags;
 235} board_info[] = {
 236        { "RealTek RTL8139", RTL8139_CAPS },
 237        { "RealTek RTL8129", RTL8129_CAPS },
 238};
 239
 240
 241static const struct pci_device_id rtl8139_pci_tbl[] = {
 242        {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 243        {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 244        {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 245        {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 246        {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 247        {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 248        {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 249        {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 250        {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 251        {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 252        {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 253        {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 254        {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 255        {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 256        {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 257        {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 258        {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 259        {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 260        {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 261        {0x16ec, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 262
 263#ifdef CONFIG_SH_SECUREEDGE5410
 264        /* Bogus 8139 silicon reports 8129 without external PROM :-( */
 265        {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
 266#endif
 267#ifdef CONFIG_8139TOO_8129
 268        {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
 269#endif
 270
 271        /* some crazy cards report invalid vendor ids like
 272         * 0x0001 here.  The other ids are valid and constant,
 273         * so we simply don't match on the main vendor id.
 274         */
 275        {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
 276        {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
 277        {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
 278
 279        {0,}
 280};
 281MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
 282
 283static struct {
 284        const char str[ETH_GSTRING_LEN];
 285} ethtool_stats_keys[] = {
 286        { "early_rx" },
 287        { "tx_buf_mapped" },
 288        { "tx_timeouts" },
 289        { "rx_lost_in_ring" },
 290};
 291
 292/* The rest of these values should never change. */
 293
 294/* Symbolic offsets to registers. */
 295enum RTL8139_registers {
 296        MAC0            = 0,     /* Ethernet hardware address. */
 297        MAR0            = 8,     /* Multicast filter. */
 298        TxStatus0       = 0x10,  /* Transmit status (Four 32bit registers). */
 299        TxAddr0         = 0x20,  /* Tx descriptors (also four 32bit). */
 300        RxBuf           = 0x30,
 301        ChipCmd         = 0x37,
 302        RxBufPtr        = 0x38,
 303        RxBufAddr       = 0x3A,
 304        IntrMask        = 0x3C,
 305        IntrStatus      = 0x3E,
 306        TxConfig        = 0x40,
 307        RxConfig        = 0x44,
 308        Timer           = 0x48,  /* A general-purpose counter. */
 309        RxMissed        = 0x4C,  /* 24 bits valid, write clears. */
 310        Cfg9346         = 0x50,
 311        Config0         = 0x51,
 312        Config1         = 0x52,
 313        TimerInt        = 0x54,
 314        MediaStatus     = 0x58,
 315        Config3         = 0x59,
 316        Config4         = 0x5A,  /* absent on RTL-8139A */
 317        HltClk          = 0x5B,
 318        MultiIntr       = 0x5C,
 319        TxSummary       = 0x60,
 320        BasicModeCtrl   = 0x62,
 321        BasicModeStatus = 0x64,
 322        NWayAdvert      = 0x66,
 323        NWayLPAR        = 0x68,
 324        NWayExpansion   = 0x6A,
 325        /* Undocumented registers, but required for proper operation. */
 326        FIFOTMS         = 0x70,  /* FIFO Control and test. */
 327        CSCR            = 0x74,  /* Chip Status and Configuration Register. */
 328        PARA78          = 0x78,
 329        FlashReg        = 0xD4, /* Communication with Flash ROM, four bytes. */
 330        PARA7c          = 0x7c,  /* Magic transceiver parameter register. */
 331        Config5         = 0xD8,  /* absent on RTL-8139A */
 332};
 333
 334enum ClearBitMasks {
 335        MultiIntrClear  = 0xF000,
 336        ChipCmdClear    = 0xE2,
 337        Config1Clear    = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
 338};
 339
 340enum ChipCmdBits {
 341        CmdReset        = 0x10,
 342        CmdRxEnb        = 0x08,
 343        CmdTxEnb        = 0x04,
 344        RxBufEmpty      = 0x01,
 345};
 346
 347/* Interrupt register bits, using my own meaningful names. */
 348enum IntrStatusBits {
 349        PCIErr          = 0x8000,
 350        PCSTimeout      = 0x4000,
 351        RxFIFOOver      = 0x40,
 352        RxUnderrun      = 0x20,
 353        RxOverflow      = 0x10,
 354        TxErr           = 0x08,
 355        TxOK            = 0x04,
 356        RxErr           = 0x02,
 357        RxOK            = 0x01,
 358
 359        RxAckBits       = RxFIFOOver | RxOverflow | RxOK,
 360};
 361
 362enum TxStatusBits {
 363        TxHostOwns      = 0x2000,
 364        TxUnderrun      = 0x4000,
 365        TxStatOK        = 0x8000,
 366        TxOutOfWindow   = 0x20000000,
 367        TxAborted       = 0x40000000,
 368        TxCarrierLost   = 0x80000000,
 369};
 370enum RxStatusBits {
 371        RxMulticast     = 0x8000,
 372        RxPhysical      = 0x4000,
 373        RxBroadcast     = 0x2000,
 374        RxBadSymbol     = 0x0020,
 375        RxRunt          = 0x0010,
 376        RxTooLong       = 0x0008,
 377        RxCRCErr        = 0x0004,
 378        RxBadAlign      = 0x0002,
 379        RxStatusOK      = 0x0001,
 380};
 381
 382/* Bits in RxConfig. */
 383enum rx_mode_bits {
 384        AcceptErr       = 0x20,
 385        AcceptRunt      = 0x10,
 386        AcceptBroadcast = 0x08,
 387        AcceptMulticast = 0x04,
 388        AcceptMyPhys    = 0x02,
 389        AcceptAllPhys   = 0x01,
 390};
 391
 392/* Bits in TxConfig. */
 393enum tx_config_bits {
 394        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
 395        TxIFGShift      = 24,
 396        TxIFG84         = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
 397        TxIFG88         = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
 398        TxIFG92         = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
 399        TxIFG96         = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
 400
 401        TxLoopBack      = (1 << 18) | (1 << 17), /* enable loopback test mode */
 402        TxCRC           = (1 << 16),    /* DISABLE Tx pkt CRC append */
 403        TxClearAbt      = (1 << 0),     /* Clear abort (WO) */
 404        TxDMAShift      = 8, /* DMA burst value (0-7) is shifted X many bits */
 405        TxRetryShift    = 4, /* TXRR value (0-15) is shifted X many bits */
 406
 407        TxVersionMask   = 0x7C800000, /* mask out version bits 30-26, 23 */
 408};
 409
 410/* Bits in Config1 */
 411enum Config1Bits {
 412        Cfg1_PM_Enable  = 0x01,
 413        Cfg1_VPD_Enable = 0x02,
 414        Cfg1_PIO        = 0x04,
 415        Cfg1_MMIO       = 0x08,
 416        LWAKE           = 0x10,         /* not on 8139, 8139A */
 417        Cfg1_Driver_Load = 0x20,
 418        Cfg1_LED0       = 0x40,
 419        Cfg1_LED1       = 0x80,
 420        SLEEP           = (1 << 1),     /* only on 8139, 8139A */
 421        PWRDN           = (1 << 0),     /* only on 8139, 8139A */
 422};
 423
 424/* Bits in Config3 */
 425enum Config3Bits {
 426        Cfg3_FBtBEn     = (1 << 0), /* 1        = Fast Back to Back */
 427        Cfg3_FuncRegEn  = (1 << 1), /* 1        = enable CardBus Function registers */
 428        Cfg3_CLKRUN_En  = (1 << 2), /* 1        = enable CLKRUN */
 429        Cfg3_CardB_En   = (1 << 3), /* 1        = enable CardBus registers */
 430        Cfg3_LinkUp     = (1 << 4), /* 1        = wake up on link up */
 431        Cfg3_Magic      = (1 << 5), /* 1        = wake up on Magic Packet (tm) */
 432        Cfg3_PARM_En    = (1 << 6), /* 0        = software can set twister parameters */
 433        Cfg3_GNTSel     = (1 << 7), /* 1        = delay 1 clock from PCI GNT signal */
 434};
 435
 436/* Bits in Config4 */
 437enum Config4Bits {
 438        LWPTN   = (1 << 2),     /* not on 8139, 8139A */
 439};
 440
 441/* Bits in Config5 */
 442enum Config5Bits {
 443        Cfg5_PME_STS    = (1 << 0), /* 1        = PCI reset resets PME_Status */
 444        Cfg5_LANWake    = (1 << 1), /* 1        = enable LANWake signal */
 445        Cfg5_LDPS       = (1 << 2), /* 0        = save power when link is down */
 446        Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */
 447        Cfg5_UWF        = (1 << 4), /* 1 = accept unicast wakeup frame */
 448        Cfg5_MWF        = (1 << 5), /* 1 = accept multicast wakeup frame */
 449        Cfg5_BWF        = (1 << 6), /* 1 = accept broadcast wakeup frame */
 450};
 451
 452enum RxConfigBits {
 453        /* rx fifo threshold */
 454        RxCfgFIFOShift  = 13,
 455        RxCfgFIFONone   = (7 << RxCfgFIFOShift),
 456
 457        /* Max DMA burst */
 458        RxCfgDMAShift   = 8,
 459        RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
 460
 461        /* rx ring buffer length */
 462        RxCfgRcv8K      = 0,
 463        RxCfgRcv16K     = (1 << 11),
 464        RxCfgRcv32K     = (1 << 12),
 465        RxCfgRcv64K     = (1 << 11) | (1 << 12),
 466
 467        /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
 468        RxNoWrap        = (1 << 7),
 469};
 470
 471/* Twister tuning parameters from RealTek.
 472   Completely undocumented, but required to tune bad links on some boards. */
 473enum CSCRBits {
 474        CSCR_LinkOKBit          = 0x0400,
 475        CSCR_LinkChangeBit      = 0x0800,
 476        CSCR_LinkStatusBits     = 0x0f000,
 477        CSCR_LinkDownOffCmd     = 0x003c0,
 478        CSCR_LinkDownCmd        = 0x0f3c0,
 479};
 480
 481enum Cfg9346Bits {
 482        Cfg9346_Lock    = 0x00,
 483        Cfg9346_Unlock  = 0xC0,
 484};
 485
 486typedef enum {
 487        CH_8139 = 0,
 488        CH_8139_K,
 489        CH_8139A,
 490        CH_8139A_G,
 491        CH_8139B,
 492        CH_8130,
 493        CH_8139C,
 494        CH_8100,
 495        CH_8100B_8139D,
 496        CH_8101,
 497} chip_t;
 498
 499enum chip_flags {
 500        HasHltClk       = (1 << 0),
 501        HasLWake        = (1 << 1),
 502};
 503
 504#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
 505        (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
 506#define HW_REVID_MASK   HW_REVID(1, 1, 1, 1, 1, 1, 1)
 507
 508/* directly indexed by chip_t, above */
 509static const struct {
 510        const char *name;
 511        u32 version; /* from RTL8139C/RTL8139D docs */
 512        u32 flags;
 513} rtl_chip_info[] = {
 514        { "RTL-8139",
 515          HW_REVID(1, 0, 0, 0, 0, 0, 0),
 516          HasHltClk,
 517        },
 518
 519        { "RTL-8139 rev K",
 520          HW_REVID(1, 1, 0, 0, 0, 0, 0),
 521          HasHltClk,
 522        },
 523
 524        { "RTL-8139A",
 525          HW_REVID(1, 1, 1, 0, 0, 0, 0),
 526          HasHltClk, /* XXX undocumented? */
 527        },
 528
 529        { "RTL-8139A rev G",
 530          HW_REVID(1, 1, 1, 0, 0, 1, 0),
 531          HasHltClk, /* XXX undocumented? */
 532        },
 533
 534        { "RTL-8139B",
 535          HW_REVID(1, 1, 1, 1, 0, 0, 0),
 536          HasLWake,
 537        },
 538
 539        { "RTL-8130",
 540          HW_REVID(1, 1, 1, 1, 1, 0, 0),
 541          HasLWake,
 542        },
 543
 544        { "RTL-8139C",
 545          HW_REVID(1, 1, 1, 0, 1, 0, 0),
 546          HasLWake,
 547        },
 548
 549        { "RTL-8100",
 550          HW_REVID(1, 1, 1, 1, 0, 1, 0),
 551          HasLWake,
 552        },
 553
 554        { "RTL-8100B/8139D",
 555          HW_REVID(1, 1, 1, 0, 1, 0, 1),
 556          HasHltClk /* XXX undocumented? */
 557        | HasLWake,
 558        },
 559
 560        { "RTL-8101",
 561          HW_REVID(1, 1, 1, 0, 1, 1, 1),
 562          HasLWake,
 563        },
 564};
 565
 566struct rtl_extra_stats {
 567        unsigned long early_rx;
 568        unsigned long tx_buf_mapped;
 569        unsigned long tx_timeouts;
 570        unsigned long rx_lost_in_ring;
 571};
 572
 573struct rtl8139_stats {
 574        u64     packets;
 575        u64     bytes;
 576        struct u64_stats_sync   syncp;
 577};
 578
 579struct rtl8139_private {
 580        void __iomem            *mmio_addr;
 581        int                     drv_flags;
 582        struct pci_dev          *pci_dev;
 583        u32                     msg_enable;
 584        struct napi_struct      napi;
 585        struct net_device       *dev;
 586
 587        unsigned char           *rx_ring;
 588        unsigned int            cur_rx; /* RX buf index of next pkt */
 589        struct rtl8139_stats    rx_stats;
 590        dma_addr_t              rx_ring_dma;
 591
 592        unsigned int            tx_flag;
 593        unsigned long           cur_tx;
 594        unsigned long           dirty_tx;
 595        struct rtl8139_stats    tx_stats;
 596        unsigned char           *tx_buf[NUM_TX_DESC];   /* Tx bounce buffers */
 597        unsigned char           *tx_bufs;       /* Tx bounce buffer region. */
 598        dma_addr_t              tx_bufs_dma;
 599
 600        signed char             phys[4];        /* MII device addresses. */
 601
 602                                /* Twister tune state. */
 603        char                    twistie, twist_row, twist_col;
 604
 605        unsigned int            watchdog_fired : 1;
 606        unsigned int            default_port : 4; /* Last dev->if_port value. */
 607        unsigned int            have_thread : 1;
 608
 609        spinlock_t              lock;
 610        spinlock_t              rx_lock;
 611
 612        chip_t                  chipset;
 613        u32                     rx_config;
 614        struct rtl_extra_stats  xstats;
 615
 616        struct delayed_work     thread;
 617
 618        struct mii_if_info      mii;
 619        unsigned int            regs_len;
 620        unsigned long           fifo_copy_timeout;
 621};
 622
 623MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
 624MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
 625MODULE_LICENSE("GPL");
 626MODULE_VERSION(DRV_VERSION);
 627
 628module_param(use_io, bool, 0);
 629MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO");
 630module_param(multicast_filter_limit, int, 0);
 631module_param_array(media, int, NULL, 0);
 632module_param_array(full_duplex, int, NULL, 0);
 633module_param(debug, int, 0);
 634MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
 635MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
 636MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
 637MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
 638
 639static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
 640static int rtl8139_open (struct net_device *dev);
 641static int mdio_read (struct net_device *dev, int phy_id, int location);
 642static void mdio_write (struct net_device *dev, int phy_id, int location,
 643                        int val);
 644static void rtl8139_start_thread(struct rtl8139_private *tp);
 645static void rtl8139_tx_timeout (struct net_device *dev, unsigned int txqueue);
 646static void rtl8139_init_ring (struct net_device *dev);
 647static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
 648                                       struct net_device *dev);
 649#ifdef CONFIG_NET_POLL_CONTROLLER
 650static void rtl8139_poll_controller(struct net_device *dev);
 651#endif
 652static int rtl8139_set_mac_address(struct net_device *dev, void *p);
 653static int rtl8139_poll(struct napi_struct *napi, int budget);
 654static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance);
 655static int rtl8139_close (struct net_device *dev);
 656static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
 657static void rtl8139_get_stats64(struct net_device *dev,
 658                                struct rtnl_link_stats64 *stats);
 659static void rtl8139_set_rx_mode (struct net_device *dev);
 660static void __set_rx_mode (struct net_device *dev);
 661static void rtl8139_hw_start (struct net_device *dev);
 662static void rtl8139_thread (struct work_struct *work);
 663static void rtl8139_tx_timeout_task(struct work_struct *work);
 664static const struct ethtool_ops rtl8139_ethtool_ops;
 665
 666/* write MMIO register, with flush */
 667/* Flush avoids rtl8139 bug w/ posted MMIO writes */
 668#define RTL_W8_F(reg, val8)     do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
 669#define RTL_W16_F(reg, val16)   do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
 670#define RTL_W32_F(reg, val32)   do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
 671
 672/* write MMIO register */
 673#define RTL_W8(reg, val8)       iowrite8 ((val8), ioaddr + (reg))
 674#define RTL_W16(reg, val16)     iowrite16 ((val16), ioaddr + (reg))
 675#define RTL_W32(reg, val32)     iowrite32 ((val32), ioaddr + (reg))
 676
 677/* read MMIO register */
 678#define RTL_R8(reg)             ioread8 (ioaddr + (reg))
 679#define RTL_R16(reg)            ioread16 (ioaddr + (reg))
 680#define RTL_R32(reg)            ioread32 (ioaddr + (reg))
 681
 682
 683static const u16 rtl8139_intr_mask =
 684        PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
 685        TxErr | TxOK | RxErr | RxOK;
 686
 687static const u16 rtl8139_norx_intr_mask =
 688        PCIErr | PCSTimeout | RxUnderrun |
 689        TxErr | TxOK | RxErr ;
 690
 691#if RX_BUF_IDX == 0
 692static const unsigned int rtl8139_rx_config =
 693        RxCfgRcv8K | RxNoWrap |
 694        (RX_FIFO_THRESH << RxCfgFIFOShift) |
 695        (RX_DMA_BURST << RxCfgDMAShift);
 696#elif RX_BUF_IDX == 1
 697static const unsigned int rtl8139_rx_config =
 698        RxCfgRcv16K | RxNoWrap |
 699        (RX_FIFO_THRESH << RxCfgFIFOShift) |
 700        (RX_DMA_BURST << RxCfgDMAShift);
 701#elif RX_BUF_IDX == 2
 702static const unsigned int rtl8139_rx_config =
 703        RxCfgRcv32K | RxNoWrap |
 704        (RX_FIFO_THRESH << RxCfgFIFOShift) |
 705        (RX_DMA_BURST << RxCfgDMAShift);
 706#elif RX_BUF_IDX == 3
 707static const unsigned int rtl8139_rx_config =
 708        RxCfgRcv64K |
 709        (RX_FIFO_THRESH << RxCfgFIFOShift) |
 710        (RX_DMA_BURST << RxCfgDMAShift);
 711#else
 712#error "Invalid configuration for 8139_RXBUF_IDX"
 713#endif
 714
 715static const unsigned int rtl8139_tx_config =
 716        TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
 717
 718static void __rtl8139_cleanup_dev (struct net_device *dev)
 719{
 720        struct rtl8139_private *tp = netdev_priv(dev);
 721        struct pci_dev *pdev;
 722
 723        assert (dev != NULL);
 724        assert (tp->pci_dev != NULL);
 725        pdev = tp->pci_dev;
 726
 727        if (tp->mmio_addr)
 728                pci_iounmap (pdev, tp->mmio_addr);
 729
 730        /* it's ok to call this even if we have no regions to free */
 731        pci_release_regions (pdev);
 732
 733        free_netdev(dev);
 734}
 735
 736
 737static void rtl8139_chip_reset (void __iomem *ioaddr)
 738{
 739        int i;
 740
 741        /* Soft reset the chip. */
 742        RTL_W8 (ChipCmd, CmdReset);
 743
 744        /* Check that the chip has finished the reset. */
 745        for (i = 1000; i > 0; i--) {
 746                barrier();
 747                if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
 748                        break;
 749                udelay (10);
 750        }
 751}
 752
 753
 754static struct net_device *rtl8139_init_board(struct pci_dev *pdev)
 755{
 756        struct device *d = &pdev->dev;
 757        void __iomem *ioaddr;
 758        struct net_device *dev;
 759        struct rtl8139_private *tp;
 760        u8 tmp8;
 761        int rc, disable_dev_on_err = 0;
 762        unsigned int i, bar;
 763        unsigned long io_len;
 764        u32 version;
 765        static const struct {
 766                unsigned long mask;
 767                char *type;
 768        } res[] = {
 769                { IORESOURCE_IO,  "PIO" },
 770                { IORESOURCE_MEM, "MMIO" }
 771        };
 772
 773        assert (pdev != NULL);
 774
 775        /* dev and priv zeroed in alloc_etherdev */
 776        dev = alloc_etherdev (sizeof (*tp));
 777        if (dev == NULL)
 778                return ERR_PTR(-ENOMEM);
 779
 780        SET_NETDEV_DEV(dev, &pdev->dev);
 781
 782        tp = netdev_priv(dev);
 783        tp->pci_dev = pdev;
 784
 785        /* enable device (incl. PCI PM wakeup and hotplug setup) */
 786        rc = pci_enable_device (pdev);
 787        if (rc)
 788                goto err_out;
 789
 790        disable_dev_on_err = 1;
 791        rc = pci_request_regions (pdev, DRV_NAME);
 792        if (rc)
 793                goto err_out;
 794
 795        pci_set_master (pdev);
 796
 797        u64_stats_init(&tp->rx_stats.syncp);
 798        u64_stats_init(&tp->tx_stats.syncp);
 799
 800retry:
 801        /* PIO bar register comes first. */
 802        bar = !use_io;
 803
 804        io_len = pci_resource_len(pdev, bar);
 805
 806        dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len);
 807
 808        if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) {
 809                dev_err(d, "region #%d not a %s resource, aborting\n", bar,
 810                        res[bar].type);
 811                rc = -ENODEV;
 812                goto err_out;
 813        }
 814        if (io_len < RTL_MIN_IO_SIZE) {
 815                dev_err(d, "Invalid PCI %s region size(s), aborting\n",
 816                        res[bar].type);
 817                rc = -ENODEV;
 818                goto err_out;
 819        }
 820
 821        ioaddr = pci_iomap(pdev, bar, 0);
 822        if (!ioaddr) {
 823                dev_err(d, "cannot map %s\n", res[bar].type);
 824                if (!use_io) {
 825                        use_io = true;
 826                        goto retry;
 827                }
 828                rc = -ENODEV;
 829                goto err_out;
 830        }
 831        tp->regs_len = io_len;
 832        tp->mmio_addr = ioaddr;
 833
 834        /* Bring old chips out of low-power mode. */
 835        RTL_W8 (HltClk, 'R');
 836
 837        /* check for missing/broken hardware */
 838        if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
 839                dev_err(&pdev->dev, "Chip not responding, ignoring board\n");
 840                rc = -EIO;
 841                goto err_out;
 842        }
 843
 844        /* identify chip attached to board */
 845        version = RTL_R32 (TxConfig) & HW_REVID_MASK;
 846        for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
 847                if (version == rtl_chip_info[i].version) {
 848                        tp->chipset = i;
 849                        goto match;
 850                }
 851
 852        /* if unknown chip, assume array element #0, original RTL-8139 in this case */
 853        i = 0;
 854        dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n");
 855        dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig));
 856        tp->chipset = 0;
 857
 858match:
 859        pr_debug("chipset id (%d) == index %d, '%s'\n",
 860                 version, i, rtl_chip_info[i].name);
 861
 862        if (tp->chipset >= CH_8139B) {
 863                u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
 864                pr_debug("PCI PM wakeup\n");
 865                if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
 866                    (tmp8 & LWAKE))
 867                        new_tmp8 &= ~LWAKE;
 868                new_tmp8 |= Cfg1_PM_Enable;
 869                if (new_tmp8 != tmp8) {
 870                        RTL_W8 (Cfg9346, Cfg9346_Unlock);
 871                        RTL_W8 (Config1, tmp8);
 872                        RTL_W8 (Cfg9346, Cfg9346_Lock);
 873                }
 874                if (rtl_chip_info[tp->chipset].flags & HasLWake) {
 875                        tmp8 = RTL_R8 (Config4);
 876                        if (tmp8 & LWPTN) {
 877                                RTL_W8 (Cfg9346, Cfg9346_Unlock);
 878                                RTL_W8 (Config4, tmp8 & ~LWPTN);
 879                                RTL_W8 (Cfg9346, Cfg9346_Lock);
 880                        }
 881                }
 882        } else {
 883                pr_debug("Old chip wakeup\n");
 884                tmp8 = RTL_R8 (Config1);
 885                tmp8 &= ~(SLEEP | PWRDN);
 886                RTL_W8 (Config1, tmp8);
 887        }
 888
 889        rtl8139_chip_reset (ioaddr);
 890
 891        return dev;
 892
 893err_out:
 894        __rtl8139_cleanup_dev (dev);
 895        if (disable_dev_on_err)
 896                pci_disable_device (pdev);
 897        return ERR_PTR(rc);
 898}
 899
 900static int rtl8139_set_features(struct net_device *dev, netdev_features_t features)
 901{
 902        struct rtl8139_private *tp = netdev_priv(dev);
 903        unsigned long flags;
 904        netdev_features_t changed = features ^ dev->features;
 905        void __iomem *ioaddr = tp->mmio_addr;
 906
 907        if (!(changed & (NETIF_F_RXALL)))
 908                return 0;
 909
 910        spin_lock_irqsave(&tp->lock, flags);
 911
 912        if (changed & NETIF_F_RXALL) {
 913                int rx_mode = tp->rx_config;
 914                if (features & NETIF_F_RXALL)
 915                        rx_mode |= (AcceptErr | AcceptRunt);
 916                else
 917                        rx_mode &= ~(AcceptErr | AcceptRunt);
 918                tp->rx_config = rtl8139_rx_config | rx_mode;
 919                RTL_W32_F(RxConfig, tp->rx_config);
 920        }
 921
 922        spin_unlock_irqrestore(&tp->lock, flags);
 923
 924        return 0;
 925}
 926
 927static const struct net_device_ops rtl8139_netdev_ops = {
 928        .ndo_open               = rtl8139_open,
 929        .ndo_stop               = rtl8139_close,
 930        .ndo_get_stats64        = rtl8139_get_stats64,
 931        .ndo_validate_addr      = eth_validate_addr,
 932        .ndo_set_mac_address    = rtl8139_set_mac_address,
 933        .ndo_start_xmit         = rtl8139_start_xmit,
 934        .ndo_set_rx_mode        = rtl8139_set_rx_mode,
 935        .ndo_do_ioctl           = netdev_ioctl,
 936        .ndo_tx_timeout         = rtl8139_tx_timeout,
 937#ifdef CONFIG_NET_POLL_CONTROLLER
 938        .ndo_poll_controller    = rtl8139_poll_controller,
 939#endif
 940        .ndo_set_features       = rtl8139_set_features,
 941};
 942
 943static int rtl8139_init_one(struct pci_dev *pdev,
 944                            const struct pci_device_id *ent)
 945{
 946        struct net_device *dev = NULL;
 947        struct rtl8139_private *tp;
 948        int i, addr_len, option;
 949        void __iomem *ioaddr;
 950        static int board_idx = -1;
 951
 952        assert (pdev != NULL);
 953        assert (ent != NULL);
 954
 955        board_idx++;
 956
 957        /* when we're built into the kernel, the driver version message
 958         * is only printed if at least one 8139 board has been found
 959         */
 960#ifndef MODULE
 961        {
 962                static int printed_version;
 963                if (!printed_version++)
 964                        pr_info(RTL8139_DRIVER_NAME "\n");
 965        }
 966#endif
 967
 968        if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
 969            pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) {
 970                dev_info(&pdev->dev,
 971                           "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n",
 972                           pdev->vendor, pdev->device, pdev->revision);
 973                return -ENODEV;
 974        }
 975
 976        if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
 977            pdev->device == PCI_DEVICE_ID_REALTEK_8139 &&
 978            pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS &&
 979            pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) {
 980                pr_info("OQO Model 2 detected. Forcing PIO\n");
 981                use_io = 1;
 982        }
 983
 984        dev = rtl8139_init_board (pdev);
 985        if (IS_ERR(dev))
 986                return PTR_ERR(dev);
 987
 988        assert (dev != NULL);
 989        tp = netdev_priv(dev);
 990        tp->dev = dev;
 991
 992        ioaddr = tp->mmio_addr;
 993        assert (ioaddr != NULL);
 994
 995        addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
 996        for (i = 0; i < 3; i++)
 997                ((__le16 *) (dev->dev_addr))[i] =
 998                    cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len));
 999
1000        /* The Rtl8139-specific entries in the device structure. */
1001        dev->netdev_ops = &rtl8139_netdev_ops;
1002        dev->ethtool_ops = &rtl8139_ethtool_ops;
1003        dev->watchdog_timeo = TX_TIMEOUT;
1004        netif_napi_add(dev, &tp->napi, rtl8139_poll, 64);
1005
1006        /* note: the hardware is not capable of sg/csum/highdma, however
1007         * through the use of skb_copy_and_csum_dev we enable these
1008         * features
1009         */
1010        dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1011        dev->vlan_features = dev->features;
1012
1013        dev->hw_features |= NETIF_F_RXALL;
1014        dev->hw_features |= NETIF_F_RXFCS;
1015
1016        /* MTU range: 68 - 1770 */
1017        dev->min_mtu = ETH_MIN_MTU;
1018        dev->max_mtu = MAX_ETH_DATA_SIZE;
1019
1020        /* tp zeroed and aligned in alloc_etherdev */
1021        tp = netdev_priv(dev);
1022
1023        /* note: tp->chipset set in rtl8139_init_board */
1024        tp->drv_flags = board_info[ent->driver_data].hw_flags;
1025        tp->mmio_addr = ioaddr;
1026        tp->msg_enable =
1027                (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1028        spin_lock_init (&tp->lock);
1029        spin_lock_init (&tp->rx_lock);
1030        INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1031        tp->mii.dev = dev;
1032        tp->mii.mdio_read = mdio_read;
1033        tp->mii.mdio_write = mdio_write;
1034        tp->mii.phy_id_mask = 0x3f;
1035        tp->mii.reg_num_mask = 0x1f;
1036
1037        /* dev is fully set up and ready to use now */
1038        pr_debug("about to register device named %s (%p)...\n",
1039                 dev->name, dev);
1040        i = register_netdev (dev);
1041        if (i) goto err_out;
1042
1043        pci_set_drvdata (pdev, dev);
1044
1045        netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n",
1046                    board_info[ent->driver_data].name,
1047                    ioaddr, dev->dev_addr, pdev->irq);
1048
1049        netdev_dbg(dev, "Identified 8139 chip type '%s'\n",
1050                   rtl_chip_info[tp->chipset].name);
1051
1052        /* Find the connected MII xcvrs.
1053           Doing this in open() would allow detecting external xcvrs later, but
1054           takes too much time. */
1055#ifdef CONFIG_8139TOO_8129
1056        if (tp->drv_flags & HAS_MII_XCVR) {
1057                int phy, phy_idx = 0;
1058                for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1059                        int mii_status = mdio_read(dev, phy, 1);
1060                        if (mii_status != 0xffff  &&  mii_status != 0x0000) {
1061                                u16 advertising = mdio_read(dev, phy, 4);
1062                                tp->phys[phy_idx++] = phy;
1063                                netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n",
1064                                            phy, mii_status, advertising);
1065                        }
1066                }
1067                if (phy_idx == 0) {
1068                        netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n");
1069                        tp->phys[0] = 32;
1070                }
1071        } else
1072#endif
1073                tp->phys[0] = 32;
1074        tp->mii.phy_id = tp->phys[0];
1075
1076        /* The lower four bits are the media type. */
1077        option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1078        if (option > 0) {
1079                tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1080                tp->default_port = option & 0xFF;
1081                if (tp->default_port)
1082                        tp->mii.force_media = 1;
1083        }
1084        if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)
1085                tp->mii.full_duplex = full_duplex[board_idx];
1086        if (tp->mii.full_duplex) {
1087                netdev_info(dev, "Media type forced to Full Duplex\n");
1088                /* Changing the MII-advertised media because might prevent
1089                   re-connection. */
1090                tp->mii.force_media = 1;
1091        }
1092        if (tp->default_port) {
1093                netdev_info(dev, "  Forcing %dMbps %s-duplex operation\n",
1094                            (option & 0x20 ? 100 : 10),
1095                            (option & 0x10 ? "full" : "half"));
1096                mdio_write(dev, tp->phys[0], 0,
1097                                   ((option & 0x20) ? 0x2000 : 0) |     /* 100Mbps? */
1098                                   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1099        }
1100
1101        /* Put the chip into low-power mode. */
1102        if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1103                RTL_W8 (HltClk, 'H');   /* 'R' would leave the clock running. */
1104
1105        return 0;
1106
1107err_out:
1108        __rtl8139_cleanup_dev (dev);
1109        pci_disable_device (pdev);
1110        return i;
1111}
1112
1113
1114static void rtl8139_remove_one(struct pci_dev *pdev)
1115{
1116        struct net_device *dev = pci_get_drvdata (pdev);
1117        struct rtl8139_private *tp = netdev_priv(dev);
1118
1119        assert (dev != NULL);
1120
1121        cancel_delayed_work_sync(&tp->thread);
1122
1123        unregister_netdev (dev);
1124
1125        __rtl8139_cleanup_dev (dev);
1126        pci_disable_device (pdev);
1127}
1128
1129
1130/* Serial EEPROM section. */
1131
1132/*  EEPROM_Ctrl bits. */
1133#define EE_SHIFT_CLK    0x04    /* EEPROM shift clock. */
1134#define EE_CS                   0x08    /* EEPROM chip select. */
1135#define EE_DATA_WRITE   0x02    /* EEPROM chip data in. */
1136#define EE_WRITE_0              0x00
1137#define EE_WRITE_1              0x02
1138#define EE_DATA_READ    0x01    /* EEPROM chip data out. */
1139#define EE_ENB                  (0x80 | EE_CS)
1140
1141/* Delay between EEPROM clock transitions.
1142   No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1143 */
1144
1145#define eeprom_delay()  (void)RTL_R8(Cfg9346)
1146
1147/* The EEPROM commands include the alway-set leading bit. */
1148#define EE_WRITE_CMD    (5)
1149#define EE_READ_CMD             (6)
1150#define EE_ERASE_CMD    (7)
1151
1152static int read_eeprom(void __iomem *ioaddr, int location, int addr_len)
1153{
1154        int i;
1155        unsigned retval = 0;
1156        int read_cmd = location | (EE_READ_CMD << addr_len);
1157
1158        RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1159        RTL_W8 (Cfg9346, EE_ENB);
1160        eeprom_delay ();
1161
1162        /* Shift the read command bits out. */
1163        for (i = 4 + addr_len; i >= 0; i--) {
1164                int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1165                RTL_W8 (Cfg9346, EE_ENB | dataval);
1166                eeprom_delay ();
1167                RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1168                eeprom_delay ();
1169        }
1170        RTL_W8 (Cfg9346, EE_ENB);
1171        eeprom_delay ();
1172
1173        for (i = 16; i > 0; i--) {
1174                RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1175                eeprom_delay ();
1176                retval =
1177                    (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1178                                     0);
1179                RTL_W8 (Cfg9346, EE_ENB);
1180                eeprom_delay ();
1181        }
1182
1183        /* Terminate the EEPROM access. */
1184        RTL_W8(Cfg9346, 0);
1185        eeprom_delay ();
1186
1187        return retval;
1188}
1189
1190/* MII serial management: mostly bogus for now. */
1191/* Read and write the MII management registers using software-generated
1192   serial MDIO protocol.
1193   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
1194   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1195   "overclocking" issues. */
1196#define MDIO_DIR                0x80
1197#define MDIO_DATA_OUT   0x04
1198#define MDIO_DATA_IN    0x02
1199#define MDIO_CLK                0x01
1200#define MDIO_WRITE0 (MDIO_DIR)
1201#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1202
1203#define mdio_delay()    RTL_R8(Config4)
1204
1205
1206static const char mii_2_8139_map[8] = {
1207        BasicModeCtrl,
1208        BasicModeStatus,
1209        0,
1210        0,
1211        NWayAdvert,
1212        NWayLPAR,
1213        NWayExpansion,
1214        0
1215};
1216
1217
1218#ifdef CONFIG_8139TOO_8129
1219/* Syncronize the MII management interface by shifting 32 one bits out. */
1220static void mdio_sync (void __iomem *ioaddr)
1221{
1222        int i;
1223
1224        for (i = 32; i >= 0; i--) {
1225                RTL_W8 (Config4, MDIO_WRITE1);
1226                mdio_delay ();
1227                RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1228                mdio_delay ();
1229        }
1230}
1231#endif
1232
1233static int mdio_read (struct net_device *dev, int phy_id, int location)
1234{
1235        struct rtl8139_private *tp = netdev_priv(dev);
1236        int retval = 0;
1237#ifdef CONFIG_8139TOO_8129
1238        void __iomem *ioaddr = tp->mmio_addr;
1239        int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1240        int i;
1241#endif
1242
1243        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
1244                void __iomem *ioaddr = tp->mmio_addr;
1245                return location < 8 && mii_2_8139_map[location] ?
1246                    RTL_R16 (mii_2_8139_map[location]) : 0;
1247        }
1248
1249#ifdef CONFIG_8139TOO_8129
1250        mdio_sync (ioaddr);
1251        /* Shift the read command bits out. */
1252        for (i = 15; i >= 0; i--) {
1253                int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1254
1255                RTL_W8 (Config4, MDIO_DIR | dataval);
1256                mdio_delay ();
1257                RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1258                mdio_delay ();
1259        }
1260
1261        /* Read the two transition, 16 data, and wire-idle bits. */
1262        for (i = 19; i > 0; i--) {
1263                RTL_W8 (Config4, 0);
1264                mdio_delay ();
1265                retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1266                RTL_W8 (Config4, MDIO_CLK);
1267                mdio_delay ();
1268        }
1269#endif
1270
1271        return (retval >> 1) & 0xffff;
1272}
1273
1274
1275static void mdio_write (struct net_device *dev, int phy_id, int location,
1276                        int value)
1277{
1278        struct rtl8139_private *tp = netdev_priv(dev);
1279#ifdef CONFIG_8139TOO_8129
1280        void __iomem *ioaddr = tp->mmio_addr;
1281        int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1282        int i;
1283#endif
1284
1285        if (phy_id > 31) {      /* Really a 8139.  Use internal registers. */
1286                void __iomem *ioaddr = tp->mmio_addr;
1287                if (location == 0) {
1288                        RTL_W8 (Cfg9346, Cfg9346_Unlock);
1289                        RTL_W16 (BasicModeCtrl, value);
1290                        RTL_W8 (Cfg9346, Cfg9346_Lock);
1291                } else if (location < 8 && mii_2_8139_map[location])
1292                        RTL_W16 (mii_2_8139_map[location], value);
1293                return;
1294        }
1295
1296#ifdef CONFIG_8139TOO_8129
1297        mdio_sync (ioaddr);
1298
1299        /* Shift the command bits out. */
1300        for (i = 31; i >= 0; i--) {
1301                int dataval =
1302                    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1303                RTL_W8 (Config4, dataval);
1304                mdio_delay ();
1305                RTL_W8 (Config4, dataval | MDIO_CLK);
1306                mdio_delay ();
1307        }
1308        /* Clear out extra bits. */
1309        for (i = 2; i > 0; i--) {
1310                RTL_W8 (Config4, 0);
1311                mdio_delay ();
1312                RTL_W8 (Config4, MDIO_CLK);
1313                mdio_delay ();
1314        }
1315#endif
1316}
1317
1318
1319static int rtl8139_open (struct net_device *dev)
1320{
1321        struct rtl8139_private *tp = netdev_priv(dev);
1322        void __iomem *ioaddr = tp->mmio_addr;
1323        const int irq = tp->pci_dev->irq;
1324        int retval;
1325
1326        retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev);
1327        if (retval)
1328                return retval;
1329
1330        tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1331                                           &tp->tx_bufs_dma, GFP_KERNEL);
1332        tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1333                                           &tp->rx_ring_dma, GFP_KERNEL);
1334        if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1335                free_irq(irq, dev);
1336
1337                if (tp->tx_bufs)
1338                        dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
1339                                            tp->tx_bufs, tp->tx_bufs_dma);
1340                if (tp->rx_ring)
1341                        dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
1342                                            tp->rx_ring, tp->rx_ring_dma);
1343
1344                return -ENOMEM;
1345
1346        }
1347
1348        napi_enable(&tp->napi);
1349
1350        tp->mii.full_duplex = tp->mii.force_media;
1351        tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1352
1353        rtl8139_init_ring (dev);
1354        rtl8139_hw_start (dev);
1355        netif_start_queue (dev);
1356
1357        netif_dbg(tp, ifup, dev,
1358                  "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n",
1359                  __func__,
1360                  (unsigned long long)pci_resource_start (tp->pci_dev, 1),
1361                  irq, RTL_R8 (MediaStatus),
1362                  tp->mii.full_duplex ? "full" : "half");
1363
1364        rtl8139_start_thread(tp);
1365
1366        return 0;
1367}
1368
1369
1370static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1371{
1372        struct rtl8139_private *tp = netdev_priv(dev);
1373
1374        if (tp->phys[0] >= 0) {
1375                mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1376        }
1377}
1378
1379/* Start the hardware at open or resume. */
1380static void rtl8139_hw_start (struct net_device *dev)
1381{
1382        struct rtl8139_private *tp = netdev_priv(dev);
1383        void __iomem *ioaddr = tp->mmio_addr;
1384        u32 i;
1385        u8 tmp;
1386
1387        /* Bring old chips out of low-power mode. */
1388        if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1389                RTL_W8 (HltClk, 'R');
1390
1391        rtl8139_chip_reset (ioaddr);
1392
1393        /* unlock Config[01234] and BMCR register writes */
1394        RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1395        /* Restore our idea of the MAC address. */
1396        RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1397        RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4)));
1398
1399        tp->cur_rx = 0;
1400
1401        /* init Rx ring buffer DMA address */
1402        RTL_W32_F (RxBuf, tp->rx_ring_dma);
1403
1404        /* Must enable Tx/Rx before setting transfer thresholds! */
1405        RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1406
1407        tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1408        RTL_W32 (RxConfig, tp->rx_config);
1409        RTL_W32 (TxConfig, rtl8139_tx_config);
1410
1411        rtl_check_media (dev, 1);
1412
1413        if (tp->chipset >= CH_8139B) {
1414                /* Disable magic packet scanning, which is enabled
1415                 * when PM is enabled in Config1.  It can be reenabled
1416                 * via ETHTOOL_SWOL if desired.  */
1417                RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1418        }
1419
1420        netdev_dbg(dev, "init buffer addresses\n");
1421
1422        /* Lock Config[01234] and BMCR register writes */
1423        RTL_W8 (Cfg9346, Cfg9346_Lock);
1424
1425        /* init Tx buffer DMA addresses */
1426        for (i = 0; i < NUM_TX_DESC; i++)
1427                RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1428
1429        RTL_W32 (RxMissed, 0);
1430
1431        rtl8139_set_rx_mode (dev);
1432
1433        /* no early-rx interrupts */
1434        RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1435
1436        /* make sure RxTx has started */
1437        tmp = RTL_R8 (ChipCmd);
1438        if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1439                RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1440
1441        /* Enable all known interrupts by setting the interrupt mask. */
1442        RTL_W16 (IntrMask, rtl8139_intr_mask);
1443}
1444
1445
1446/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1447static void rtl8139_init_ring (struct net_device *dev)
1448{
1449        struct rtl8139_private *tp = netdev_priv(dev);
1450        int i;
1451
1452        tp->cur_rx = 0;
1453        tp->cur_tx = 0;
1454        tp->dirty_tx = 0;
1455
1456        for (i = 0; i < NUM_TX_DESC; i++)
1457                tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1458}
1459
1460
1461/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1462static int next_tick = 3 * HZ;
1463
1464#ifndef CONFIG_8139TOO_TUNE_TWISTER
1465static inline void rtl8139_tune_twister (struct net_device *dev,
1466                                  struct rtl8139_private *tp) {}
1467#else
1468enum TwisterParamVals {
1469        PARA78_default  = 0x78fa8388,
1470        PARA7c_default  = 0xcb38de43,   /* param[0][3] */
1471        PARA7c_xxx      = 0xcb38de43,
1472};
1473
1474static const unsigned long param[4][4] = {
1475        {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1476        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1477        {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1478        {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1479};
1480
1481static void rtl8139_tune_twister (struct net_device *dev,
1482                                  struct rtl8139_private *tp)
1483{
1484        int linkcase;
1485        void __iomem *ioaddr = tp->mmio_addr;
1486
1487        /* This is a complicated state machine to configure the "twister" for
1488           impedance/echos based on the cable length.
1489           All of this is magic and undocumented.
1490         */
1491        switch (tp->twistie) {
1492        case 1:
1493                if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1494                        /* We have link beat, let us tune the twister. */
1495                        RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1496                        tp->twistie = 2;        /* Change to state 2. */
1497                        next_tick = HZ / 10;
1498                } else {
1499                        /* Just put in some reasonable defaults for when beat returns. */
1500                        RTL_W16 (CSCR, CSCR_LinkDownCmd);
1501                        RTL_W32 (FIFOTMS, 0x20);        /* Turn on cable test mode. */
1502                        RTL_W32 (PARA78, PARA78_default);
1503                        RTL_W32 (PARA7c, PARA7c_default);
1504                        tp->twistie = 0;        /* Bail from future actions. */
1505                }
1506                break;
1507        case 2:
1508                /* Read how long it took to hear the echo. */
1509                linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1510                if (linkcase == 0x7000)
1511                        tp->twist_row = 3;
1512                else if (linkcase == 0x3000)
1513                        tp->twist_row = 2;
1514                else if (linkcase == 0x1000)
1515                        tp->twist_row = 1;
1516                else
1517                        tp->twist_row = 0;
1518                tp->twist_col = 0;
1519                tp->twistie = 3;        /* Change to state 2. */
1520                next_tick = HZ / 10;
1521                break;
1522        case 3:
1523                /* Put out four tuning parameters, one per 100msec. */
1524                if (tp->twist_col == 0)
1525                        RTL_W16 (FIFOTMS, 0);
1526                RTL_W32 (PARA7c, param[(int) tp->twist_row]
1527                         [(int) tp->twist_col]);
1528                next_tick = HZ / 10;
1529                if (++tp->twist_col >= 4) {
1530                        /* For short cables we are done.
1531                           For long cables (row == 3) check for mistune. */
1532                        tp->twistie =
1533                            (tp->twist_row == 3) ? 4 : 0;
1534                }
1535                break;
1536        case 4:
1537                /* Special case for long cables: check for mistune. */
1538                if ((RTL_R16 (CSCR) &
1539                     CSCR_LinkStatusBits) == 0x7000) {
1540                        tp->twistie = 0;
1541                        break;
1542                } else {
1543                        RTL_W32 (PARA7c, 0xfb38de03);
1544                        tp->twistie = 5;
1545                        next_tick = HZ / 10;
1546                }
1547                break;
1548        case 5:
1549                /* Retune for shorter cable (column 2). */
1550                RTL_W32 (FIFOTMS, 0x20);
1551                RTL_W32 (PARA78, PARA78_default);
1552                RTL_W32 (PARA7c, PARA7c_default);
1553                RTL_W32 (FIFOTMS, 0x00);
1554                tp->twist_row = 2;
1555                tp->twist_col = 0;
1556                tp->twistie = 3;
1557                next_tick = HZ / 10;
1558                break;
1559
1560        default:
1561                /* do nothing */
1562                break;
1563        }
1564}
1565#endif /* CONFIG_8139TOO_TUNE_TWISTER */
1566
1567static inline void rtl8139_thread_iter (struct net_device *dev,
1568                                 struct rtl8139_private *tp,
1569                                 void __iomem *ioaddr)
1570{
1571        int mii_lpa;
1572
1573        mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1574
1575        if (!tp->mii.force_media && mii_lpa != 0xffff) {
1576                int duplex = ((mii_lpa & LPA_100FULL) ||
1577                              (mii_lpa & 0x01C0) == 0x0040);
1578                if (tp->mii.full_duplex != duplex) {
1579                        tp->mii.full_duplex = duplex;
1580
1581                        if (mii_lpa) {
1582                                netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n",
1583                                            tp->mii.full_duplex ? "full" : "half",
1584                                            tp->phys[0], mii_lpa);
1585                        } else {
1586                                netdev_info(dev, "media is unconnected, link down, or incompatible connection\n");
1587                        }
1588#if 0
1589                        RTL_W8 (Cfg9346, Cfg9346_Unlock);
1590                        RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1591                        RTL_W8 (Cfg9346, Cfg9346_Lock);
1592#endif
1593                }
1594        }
1595
1596        next_tick = HZ * 60;
1597
1598        rtl8139_tune_twister (dev, tp);
1599
1600        netdev_dbg(dev, "Media selection tick, Link partner %04x\n",
1601                   RTL_R16(NWayLPAR));
1602        netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n",
1603                   RTL_R16(IntrMask), RTL_R16(IntrStatus));
1604        netdev_dbg(dev, "Chip config %02x %02x\n",
1605                   RTL_R8(Config0), RTL_R8(Config1));
1606}
1607
1608static void rtl8139_thread (struct work_struct *work)
1609{
1610        struct rtl8139_private *tp =
1611                container_of(work, struct rtl8139_private, thread.work);
1612        struct net_device *dev = tp->mii.dev;
1613        unsigned long thr_delay = next_tick;
1614
1615        rtnl_lock();
1616
1617        if (!netif_running(dev))
1618                goto out_unlock;
1619
1620        if (tp->watchdog_fired) {
1621                tp->watchdog_fired = 0;
1622                rtl8139_tx_timeout_task(work);
1623        } else
1624                rtl8139_thread_iter(dev, tp, tp->mmio_addr);
1625
1626        if (tp->have_thread)
1627                schedule_delayed_work(&tp->thread, thr_delay);
1628out_unlock:
1629        rtnl_unlock ();
1630}
1631
1632static void rtl8139_start_thread(struct rtl8139_private *tp)
1633{
1634        tp->twistie = 0;
1635        if (tp->chipset == CH_8139_K)
1636                tp->twistie = 1;
1637        else if (tp->drv_flags & HAS_LNK_CHNG)
1638                return;
1639
1640        tp->have_thread = 1;
1641        tp->watchdog_fired = 0;
1642
1643        schedule_delayed_work(&tp->thread, next_tick);
1644}
1645
1646static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1647{
1648        tp->cur_tx = 0;
1649        tp->dirty_tx = 0;
1650
1651        /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1652}
1653
1654static void rtl8139_tx_timeout_task (struct work_struct *work)
1655{
1656        struct rtl8139_private *tp =
1657                container_of(work, struct rtl8139_private, thread.work);
1658        struct net_device *dev = tp->mii.dev;
1659        void __iomem *ioaddr = tp->mmio_addr;
1660        int i;
1661        u8 tmp8;
1662
1663        napi_disable(&tp->napi);
1664        netif_stop_queue(dev);
1665        synchronize_rcu();
1666
1667        netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n",
1668                   RTL_R8(ChipCmd), RTL_R16(IntrStatus),
1669                   RTL_R16(IntrMask), RTL_R8(MediaStatus));
1670        /* Emit info to figure out what went wrong. */
1671        netdev_dbg(dev, "Tx queue start entry %ld  dirty entry %ld\n",
1672                   tp->cur_tx, tp->dirty_tx);
1673        for (i = 0; i < NUM_TX_DESC; i++)
1674                netdev_dbg(dev, "Tx descriptor %d is %08x%s\n",
1675                           i, RTL_R32(TxStatus0 + (i * 4)),
1676                           i == tp->dirty_tx % NUM_TX_DESC ?
1677                           " (queue head)" : "");
1678
1679        tp->xstats.tx_timeouts++;
1680
1681        /* disable Tx ASAP, if not already */
1682        tmp8 = RTL_R8 (ChipCmd);
1683        if (tmp8 & CmdTxEnb)
1684                RTL_W8 (ChipCmd, CmdRxEnb);
1685
1686        spin_lock_bh(&tp->rx_lock);
1687        /* Disable interrupts by clearing the interrupt mask. */
1688        RTL_W16 (IntrMask, 0x0000);
1689
1690        /* Stop a shared interrupt from scavenging while we are. */
1691        spin_lock_irq(&tp->lock);
1692        rtl8139_tx_clear (tp);
1693        spin_unlock_irq(&tp->lock);
1694
1695        /* ...and finally, reset everything */
1696        napi_enable(&tp->napi);
1697        rtl8139_hw_start(dev);
1698        netif_wake_queue(dev);
1699
1700        spin_unlock_bh(&tp->rx_lock);
1701}
1702
1703static void rtl8139_tx_timeout(struct net_device *dev, unsigned int txqueue)
1704{
1705        struct rtl8139_private *tp = netdev_priv(dev);
1706
1707        tp->watchdog_fired = 1;
1708        if (!tp->have_thread) {
1709                INIT_DELAYED_WORK(&tp->thread, rtl8139_thread);
1710                schedule_delayed_work(&tp->thread, next_tick);
1711        }
1712}
1713
1714static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb,
1715                                             struct net_device *dev)
1716{
1717        struct rtl8139_private *tp = netdev_priv(dev);
1718        void __iomem *ioaddr = tp->mmio_addr;
1719        unsigned int entry;
1720        unsigned int len = skb->len;
1721        unsigned long flags;
1722
1723        /* Calculate the next Tx descriptor entry. */
1724        entry = tp->cur_tx % NUM_TX_DESC;
1725
1726        /* Note: the chip doesn't have auto-pad! */
1727        if (likely(len < TX_BUF_SIZE)) {
1728                if (len < ETH_ZLEN)
1729                        memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1730                skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1731                dev_kfree_skb_any(skb);
1732        } else {
1733                dev_kfree_skb_any(skb);
1734                dev->stats.tx_dropped++;
1735                return NETDEV_TX_OK;
1736        }
1737
1738        spin_lock_irqsave(&tp->lock, flags);
1739        /*
1740         * Writing to TxStatus triggers a DMA transfer of the data
1741         * copied to tp->tx_buf[entry] above. Use a memory barrier
1742         * to make sure that the device sees the updated data.
1743         */
1744        wmb();
1745        RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1746                   tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1747
1748        tp->cur_tx++;
1749
1750        if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1751                netif_stop_queue (dev);
1752        spin_unlock_irqrestore(&tp->lock, flags);
1753
1754        netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n",
1755                  len, entry);
1756
1757        return NETDEV_TX_OK;
1758}
1759
1760
1761static void rtl8139_tx_interrupt (struct net_device *dev,
1762                                  struct rtl8139_private *tp,
1763                                  void __iomem *ioaddr)
1764{
1765        unsigned long dirty_tx, tx_left;
1766
1767        assert (dev != NULL);
1768        assert (ioaddr != NULL);
1769
1770        dirty_tx = tp->dirty_tx;
1771        tx_left = tp->cur_tx - dirty_tx;
1772        while (tx_left > 0) {
1773                int entry = dirty_tx % NUM_TX_DESC;
1774                int txstatus;
1775
1776                txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1777
1778                if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1779                        break;  /* It still hasn't been Txed */
1780
1781                /* Note: TxCarrierLost is always asserted at 100mbps. */
1782                if (txstatus & (TxOutOfWindow | TxAborted)) {
1783                        /* There was an major error, log it. */
1784                        netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n",
1785                                  txstatus);
1786                        dev->stats.tx_errors++;
1787                        if (txstatus & TxAborted) {
1788                                dev->stats.tx_aborted_errors++;
1789                                RTL_W32 (TxConfig, TxClearAbt);
1790                                RTL_W16 (IntrStatus, TxErr);
1791                                wmb();
1792                        }
1793                        if (txstatus & TxCarrierLost)
1794                                dev->stats.tx_carrier_errors++;
1795                        if (txstatus & TxOutOfWindow)
1796                                dev->stats.tx_window_errors++;
1797                } else {
1798                        if (txstatus & TxUnderrun) {
1799                                /* Add 64 to the Tx FIFO threshold. */
1800                                if (tp->tx_flag < 0x00300000)
1801                                        tp->tx_flag += 0x00020000;
1802                                dev->stats.tx_fifo_errors++;
1803                        }
1804                        dev->stats.collisions += (txstatus >> 24) & 15;
1805                        u64_stats_update_begin(&tp->tx_stats.syncp);
1806                        tp->tx_stats.packets++;
1807                        tp->tx_stats.bytes += txstatus & 0x7ff;
1808                        u64_stats_update_end(&tp->tx_stats.syncp);
1809                }
1810
1811                dirty_tx++;
1812                tx_left--;
1813        }
1814
1815#ifndef RTL8139_NDEBUG
1816        if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1817                netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n",
1818                           dirty_tx, tp->cur_tx);
1819                dirty_tx += NUM_TX_DESC;
1820        }
1821#endif /* RTL8139_NDEBUG */
1822
1823        /* only wake the queue if we did work, and the queue is stopped */
1824        if (tp->dirty_tx != dirty_tx) {
1825                tp->dirty_tx = dirty_tx;
1826                mb();
1827                netif_wake_queue (dev);
1828        }
1829}
1830
1831
1832/* TODO: clean this up!  Rx reset need not be this intensive */
1833static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1834                            struct rtl8139_private *tp, void __iomem *ioaddr)
1835{
1836        u8 tmp8;
1837#ifdef CONFIG_8139_OLD_RX_RESET
1838        int tmp_work;
1839#endif
1840
1841        netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n",
1842                  rx_status);
1843        dev->stats.rx_errors++;
1844        if (!(rx_status & RxStatusOK)) {
1845                if (rx_status & RxTooLong) {
1846                        netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n",
1847                                   rx_status);
1848                        /* A.C.: The chip hangs here. */
1849                }
1850                if (rx_status & (RxBadSymbol | RxBadAlign))
1851                        dev->stats.rx_frame_errors++;
1852                if (rx_status & (RxRunt | RxTooLong))
1853                        dev->stats.rx_length_errors++;
1854                if (rx_status & RxCRCErr)
1855                        dev->stats.rx_crc_errors++;
1856        } else {
1857                tp->xstats.rx_lost_in_ring++;
1858        }
1859
1860#ifndef CONFIG_8139_OLD_RX_RESET
1861        tmp8 = RTL_R8 (ChipCmd);
1862        RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1863        RTL_W8 (ChipCmd, tmp8);
1864        RTL_W32 (RxConfig, tp->rx_config);
1865        tp->cur_rx = 0;
1866#else
1867        /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1868
1869        /* disable receive */
1870        RTL_W8_F (ChipCmd, CmdTxEnb);
1871        tmp_work = 200;
1872        while (--tmp_work > 0) {
1873                udelay(1);
1874                tmp8 = RTL_R8 (ChipCmd);
1875                if (!(tmp8 & CmdRxEnb))
1876                        break;
1877        }
1878        if (tmp_work <= 0)
1879                netdev_warn(dev, "rx stop wait too long\n");
1880        /* restart receive */
1881        tmp_work = 200;
1882        while (--tmp_work > 0) {
1883                RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1884                udelay(1);
1885                tmp8 = RTL_R8 (ChipCmd);
1886                if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1887                        break;
1888        }
1889        if (tmp_work <= 0)
1890                netdev_warn(dev, "tx/rx enable wait too long\n");
1891
1892        /* and reinitialize all rx related registers */
1893        RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1894        /* Must enable Tx/Rx before setting transfer thresholds! */
1895        RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1896
1897        tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1898        RTL_W32 (RxConfig, tp->rx_config);
1899        tp->cur_rx = 0;
1900
1901        netdev_dbg(dev, "init buffer addresses\n");
1902
1903        /* Lock Config[01234] and BMCR register writes */
1904        RTL_W8 (Cfg9346, Cfg9346_Lock);
1905
1906        /* init Rx ring buffer DMA address */
1907        RTL_W32_F (RxBuf, tp->rx_ring_dma);
1908
1909        /* A.C.: Reset the multicast list. */
1910        __set_rx_mode (dev);
1911#endif
1912}
1913
1914#if RX_BUF_IDX == 3
1915static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1916                                 u32 offset, unsigned int size)
1917{
1918        u32 left = RX_BUF_LEN - offset;
1919
1920        if (size > left) {
1921                skb_copy_to_linear_data(skb, ring + offset, left);
1922                skb_copy_to_linear_data_offset(skb, left, ring, size - left);
1923        } else
1924                skb_copy_to_linear_data(skb, ring + offset, size);
1925}
1926#endif
1927
1928static void rtl8139_isr_ack(struct rtl8139_private *tp)
1929{
1930        void __iomem *ioaddr = tp->mmio_addr;
1931        u16 status;
1932
1933        status = RTL_R16 (IntrStatus) & RxAckBits;
1934
1935        /* Clear out errors and receive interrupts */
1936        if (likely(status != 0)) {
1937                if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1938                        tp->dev->stats.rx_errors++;
1939                        if (status & RxFIFOOver)
1940                                tp->dev->stats.rx_fifo_errors++;
1941                }
1942                RTL_W16_F (IntrStatus, RxAckBits);
1943        }
1944}
1945
1946static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1947                      int budget)
1948{
1949        void __iomem *ioaddr = tp->mmio_addr;
1950        int received = 0;
1951        unsigned char *rx_ring = tp->rx_ring;
1952        unsigned int cur_rx = tp->cur_rx;
1953        unsigned int rx_size = 0;
1954
1955        netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
1956                   __func__, (u16)cur_rx,
1957                   RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
1958
1959        while (netif_running(dev) && received < budget &&
1960               (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1961                u32 ring_offset = cur_rx % RX_BUF_LEN;
1962                u32 rx_status;
1963                unsigned int pkt_size;
1964                struct sk_buff *skb;
1965
1966                rmb();
1967
1968                /* read size+status of next frame from DMA ring buffer */
1969                rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset));
1970                rx_size = rx_status >> 16;
1971                if (likely(!(dev->features & NETIF_F_RXFCS)))
1972                        pkt_size = rx_size - 4;
1973                else
1974                        pkt_size = rx_size;
1975
1976                netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n",
1977                          __func__, rx_status, rx_size, cur_rx);
1978#if RTL8139_DEBUG > 2
1979                print_hex_dump(KERN_DEBUG, "Frame contents: ",
1980                               DUMP_PREFIX_OFFSET, 16, 1,
1981                               &rx_ring[ring_offset], 70, true);
1982#endif
1983
1984                /* Packet copy from FIFO still in progress.
1985                 * Theoretically, this should never happen
1986                 * since EarlyRx is disabled.
1987                 */
1988                if (unlikely(rx_size == 0xfff0)) {
1989                        if (!tp->fifo_copy_timeout)
1990                                tp->fifo_copy_timeout = jiffies + 2;
1991                        else if (time_after(jiffies, tp->fifo_copy_timeout)) {
1992                                netdev_dbg(dev, "hung FIFO. Reset\n");
1993                                rx_size = 0;
1994                                goto no_early_rx;
1995                        }
1996                        netif_dbg(tp, intr, dev, "fifo copy in progress\n");
1997                        tp->xstats.early_rx++;
1998                        break;
1999                }
2000
2001no_early_rx:
2002                tp->fifo_copy_timeout = 0;
2003
2004                /* If Rx err or invalid rx_size/rx_status received
2005                 * (which happens if we get lost in the ring),
2006                 * Rx process gets reset, so we abort any further
2007                 * Rx processing.
2008                 */
2009                if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2010                             (rx_size < 8) ||
2011                             (!(rx_status & RxStatusOK)))) {
2012                        if ((dev->features & NETIF_F_RXALL) &&
2013                            (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) &&
2014                            (rx_size >= 8) &&
2015                            (!(rx_status & RxStatusOK))) {
2016                                /* Length is at least mostly OK, but pkt has
2017                                 * error.  I'm hoping we can handle some of these
2018                                 * errors without resetting the chip. --Ben
2019                                 */
2020                                dev->stats.rx_errors++;
2021                                if (rx_status & RxCRCErr) {
2022                                        dev->stats.rx_crc_errors++;
2023                                        goto keep_pkt;
2024                                }
2025                                if (rx_status & RxRunt) {
2026                                        dev->stats.rx_length_errors++;
2027                                        goto keep_pkt;
2028                                }
2029                        }
2030                        rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2031                        received = -1;
2032                        goto out;
2033                }
2034
2035keep_pkt:
2036                /* Malloc up new buffer, compatible with net-2e. */
2037                /* Omit the four octet CRC from the length. */
2038
2039                skb = napi_alloc_skb(&tp->napi, pkt_size);
2040                if (likely(skb)) {
2041#if RX_BUF_IDX == 3
2042                        wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2043#else
2044                        skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
2045#endif
2046                        skb_put (skb, pkt_size);
2047
2048                        skb->protocol = eth_type_trans (skb, dev);
2049
2050                        u64_stats_update_begin(&tp->rx_stats.syncp);
2051                        tp->rx_stats.packets++;
2052                        tp->rx_stats.bytes += pkt_size;
2053                        u64_stats_update_end(&tp->rx_stats.syncp);
2054
2055                        netif_receive_skb (skb);
2056                } else {
2057                        dev->stats.rx_dropped++;
2058                }
2059                received++;
2060
2061                cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2062                RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2063
2064                rtl8139_isr_ack(tp);
2065        }
2066
2067        if (unlikely(!received || rx_size == 0xfff0))
2068                rtl8139_isr_ack(tp);
2069
2070        netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n",
2071                   __func__, cur_rx,
2072                   RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd));
2073
2074        tp->cur_rx = cur_rx;
2075
2076        /*
2077         * The receive buffer should be mostly empty.
2078         * Tell NAPI to reenable the Rx irq.
2079         */
2080        if (tp->fifo_copy_timeout)
2081                received = budget;
2082
2083out:
2084        return received;
2085}
2086
2087
2088static void rtl8139_weird_interrupt (struct net_device *dev,
2089                                     struct rtl8139_private *tp,
2090                                     void __iomem *ioaddr,
2091                                     int status, int link_changed)
2092{
2093        netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status);
2094
2095        assert (dev != NULL);
2096        assert (tp != NULL);
2097        assert (ioaddr != NULL);
2098
2099        /* Update the error count. */
2100        dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2101        RTL_W32 (RxMissed, 0);
2102
2103        if ((status & RxUnderrun) && link_changed &&
2104            (tp->drv_flags & HAS_LNK_CHNG)) {
2105                rtl_check_media(dev, 0);
2106                status &= ~RxUnderrun;
2107        }
2108
2109        if (status & (RxUnderrun | RxErr))
2110                dev->stats.rx_errors++;
2111
2112        if (status & PCSTimeout)
2113                dev->stats.rx_length_errors++;
2114        if (status & RxUnderrun)
2115                dev->stats.rx_fifo_errors++;
2116        if (status & PCIErr) {
2117                u16 pci_cmd_status;
2118                pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2119                pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2120
2121                netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status);
2122        }
2123}
2124
2125static int rtl8139_poll(struct napi_struct *napi, int budget)
2126{
2127        struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi);
2128        struct net_device *dev = tp->dev;
2129        void __iomem *ioaddr = tp->mmio_addr;
2130        int work_done;
2131
2132        spin_lock(&tp->rx_lock);
2133        work_done = 0;
2134        if (likely(RTL_R16(IntrStatus) & RxAckBits))
2135                work_done += rtl8139_rx(dev, tp, budget);
2136
2137        if (work_done < budget) {
2138                unsigned long flags;
2139
2140                spin_lock_irqsave(&tp->lock, flags);
2141                if (napi_complete_done(napi, work_done))
2142                        RTL_W16_F(IntrMask, rtl8139_intr_mask);
2143                spin_unlock_irqrestore(&tp->lock, flags);
2144        }
2145        spin_unlock(&tp->rx_lock);
2146
2147        return work_done;
2148}
2149
2150/* The interrupt handler does all of the Rx thread work and cleans up
2151   after the Tx thread. */
2152static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance)
2153{
2154        struct net_device *dev = (struct net_device *) dev_instance;
2155        struct rtl8139_private *tp = netdev_priv(dev);
2156        void __iomem *ioaddr = tp->mmio_addr;
2157        u16 status, ackstat;
2158        int link_changed = 0; /* avoid bogus "uninit" warning */
2159        int handled = 0;
2160
2161        spin_lock (&tp->lock);
2162        status = RTL_R16 (IntrStatus);
2163
2164        /* shared irq? */
2165        if (unlikely((status & rtl8139_intr_mask) == 0))
2166                goto out;
2167
2168        handled = 1;
2169
2170        /* h/w no longer present (hotplug?) or major error, bail */
2171        if (unlikely(status == 0xFFFF))
2172                goto out;
2173
2174        /* close possible race's with dev_close */
2175        if (unlikely(!netif_running(dev))) {
2176                RTL_W16 (IntrMask, 0);
2177                goto out;
2178        }
2179
2180        /* Acknowledge all of the current interrupt sources ASAP, but
2181           an first get an additional status bit from CSCR. */
2182        if (unlikely(status & RxUnderrun))
2183                link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2184
2185        ackstat = status & ~(RxAckBits | TxErr);
2186        if (ackstat)
2187                RTL_W16 (IntrStatus, ackstat);
2188
2189        /* Receive packets are processed by poll routine.
2190           If not running start it now. */
2191        if (status & RxAckBits){
2192                if (napi_schedule_prep(&tp->napi)) {
2193                        RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2194                        __napi_schedule(&tp->napi);
2195                }
2196        }
2197
2198        /* Check uncommon events with one test. */
2199        if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2200                rtl8139_weird_interrupt (dev, tp, ioaddr,
2201                                         status, link_changed);
2202
2203        if (status & (TxOK | TxErr)) {
2204                rtl8139_tx_interrupt (dev, tp, ioaddr);
2205                if (status & TxErr)
2206                        RTL_W16 (IntrStatus, TxErr);
2207        }
2208 out:
2209        spin_unlock (&tp->lock);
2210
2211        netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n",
2212                   RTL_R16(IntrStatus));
2213        return IRQ_RETVAL(handled);
2214}
2215
2216#ifdef CONFIG_NET_POLL_CONTROLLER
2217/*
2218 * Polling receive - used by netconsole and other diagnostic tools
2219 * to allow network i/o with interrupts disabled.
2220 */
2221static void rtl8139_poll_controller(struct net_device *dev)
2222{
2223        struct rtl8139_private *tp = netdev_priv(dev);
2224        const int irq = tp->pci_dev->irq;
2225
2226        disable_irq_nosync(irq);
2227        rtl8139_interrupt(irq, dev);
2228        enable_irq(irq);
2229}
2230#endif
2231
2232static int rtl8139_set_mac_address(struct net_device *dev, void *p)
2233{
2234        struct rtl8139_private *tp = netdev_priv(dev);
2235        void __iomem *ioaddr = tp->mmio_addr;
2236        struct sockaddr *addr = p;
2237
2238        if (!is_valid_ether_addr(addr->sa_data))
2239                return -EADDRNOTAVAIL;
2240
2241        memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2242
2243        spin_lock_irq(&tp->lock);
2244
2245        RTL_W8_F(Cfg9346, Cfg9346_Unlock);
2246        RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
2247        RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
2248        RTL_W8_F(Cfg9346, Cfg9346_Lock);
2249
2250        spin_unlock_irq(&tp->lock);
2251
2252        return 0;
2253}
2254
2255static int rtl8139_close (struct net_device *dev)
2256{
2257        struct rtl8139_private *tp = netdev_priv(dev);
2258        void __iomem *ioaddr = tp->mmio_addr;
2259        unsigned long flags;
2260
2261        netif_stop_queue(dev);
2262        napi_disable(&tp->napi);
2263
2264        netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n",
2265                  RTL_R16(IntrStatus));
2266
2267        spin_lock_irqsave (&tp->lock, flags);
2268
2269        /* Stop the chip's Tx and Rx DMA processes. */
2270        RTL_W8 (ChipCmd, 0);
2271
2272        /* Disable interrupts by clearing the interrupt mask. */
2273        RTL_W16 (IntrMask, 0);
2274
2275        /* Update the error counts. */
2276        dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2277        RTL_W32 (RxMissed, 0);
2278
2279        spin_unlock_irqrestore (&tp->lock, flags);
2280
2281        free_irq(tp->pci_dev->irq, dev);
2282
2283        rtl8139_tx_clear (tp);
2284
2285        dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN,
2286                          tp->rx_ring, tp->rx_ring_dma);
2287        dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN,
2288                          tp->tx_bufs, tp->tx_bufs_dma);
2289        tp->rx_ring = NULL;
2290        tp->tx_bufs = NULL;
2291
2292        /* Green! Put the chip in low-power mode. */
2293        RTL_W8 (Cfg9346, Cfg9346_Unlock);
2294
2295        if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2296                RTL_W8 (HltClk, 'H');   /* 'R' would leave the clock running. */
2297
2298        return 0;
2299}
2300
2301
2302/* Get the ethtool Wake-on-LAN settings.  Assumes that wol points to
2303   kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2304   other threads or interrupts aren't messing with the 8139.  */
2305static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2306{
2307        struct rtl8139_private *tp = netdev_priv(dev);
2308        void __iomem *ioaddr = tp->mmio_addr;
2309
2310        spin_lock_irq(&tp->lock);
2311        if (rtl_chip_info[tp->chipset].flags & HasLWake) {
2312                u8 cfg3 = RTL_R8 (Config3);
2313                u8 cfg5 = RTL_R8 (Config5);
2314
2315                wol->supported = WAKE_PHY | WAKE_MAGIC
2316                        | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2317
2318                wol->wolopts = 0;
2319                if (cfg3 & Cfg3_LinkUp)
2320                        wol->wolopts |= WAKE_PHY;
2321                if (cfg3 & Cfg3_Magic)
2322                        wol->wolopts |= WAKE_MAGIC;
2323                /* (KON)FIXME: See how netdev_set_wol() handles the
2324                   following constants.  */
2325                if (cfg5 & Cfg5_UWF)
2326                        wol->wolopts |= WAKE_UCAST;
2327                if (cfg5 & Cfg5_MWF)
2328                        wol->wolopts |= WAKE_MCAST;
2329                if (cfg5 & Cfg5_BWF)
2330                        wol->wolopts |= WAKE_BCAST;
2331        }
2332        spin_unlock_irq(&tp->lock);
2333}
2334
2335
2336/* Set the ethtool Wake-on-LAN settings.  Return 0 or -errno.  Assumes
2337   that wol points to kernel memory and other threads or interrupts
2338   aren't messing with the 8139.  */
2339static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2340{
2341        struct rtl8139_private *tp = netdev_priv(dev);
2342        void __iomem *ioaddr = tp->mmio_addr;
2343        u32 support;
2344        u8 cfg3, cfg5;
2345
2346        support = ((rtl_chip_info[tp->chipset].flags & HasLWake)
2347                   ? (WAKE_PHY | WAKE_MAGIC
2348                      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2349                   : 0);
2350        if (wol->wolopts & ~support)
2351                return -EINVAL;
2352
2353        spin_lock_irq(&tp->lock);
2354        cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2355        if (wol->wolopts & WAKE_PHY)
2356                cfg3 |= Cfg3_LinkUp;
2357        if (wol->wolopts & WAKE_MAGIC)
2358                cfg3 |= Cfg3_Magic;
2359        RTL_W8 (Cfg9346, Cfg9346_Unlock);
2360        RTL_W8 (Config3, cfg3);
2361        RTL_W8 (Cfg9346, Cfg9346_Lock);
2362
2363        cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2364        /* (KON)FIXME: These are untested.  We may have to set the
2365           CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2366           documentation.  */
2367        if (wol->wolopts & WAKE_UCAST)
2368                cfg5 |= Cfg5_UWF;
2369        if (wol->wolopts & WAKE_MCAST)
2370                cfg5 |= Cfg5_MWF;
2371        if (wol->wolopts & WAKE_BCAST)
2372                cfg5 |= Cfg5_BWF;
2373        RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2374        spin_unlock_irq(&tp->lock);
2375
2376        return 0;
2377}
2378
2379static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2380{
2381        struct rtl8139_private *tp = netdev_priv(dev);
2382        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2383        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2384        strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
2385}
2386
2387static int rtl8139_get_link_ksettings(struct net_device *dev,
2388                                      struct ethtool_link_ksettings *cmd)
2389{
2390        struct rtl8139_private *tp = netdev_priv(dev);
2391        spin_lock_irq(&tp->lock);
2392        mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2393        spin_unlock_irq(&tp->lock);
2394        return 0;
2395}
2396
2397static int rtl8139_set_link_ksettings(struct net_device *dev,
2398                                      const struct ethtool_link_ksettings *cmd)
2399{
2400        struct rtl8139_private *tp = netdev_priv(dev);
2401        int rc;
2402        spin_lock_irq(&tp->lock);
2403        rc = mii_ethtool_set_link_ksettings(&tp->mii, cmd);
2404        spin_unlock_irq(&tp->lock);
2405        return rc;
2406}
2407
2408static int rtl8139_nway_reset(struct net_device *dev)
2409{
2410        struct rtl8139_private *tp = netdev_priv(dev);
2411        return mii_nway_restart(&tp->mii);
2412}
2413
2414static u32 rtl8139_get_link(struct net_device *dev)
2415{
2416        struct rtl8139_private *tp = netdev_priv(dev);
2417        return mii_link_ok(&tp->mii);
2418}
2419
2420static u32 rtl8139_get_msglevel(struct net_device *dev)
2421{
2422        struct rtl8139_private *tp = netdev_priv(dev);
2423        return tp->msg_enable;
2424}
2425
2426static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2427{
2428        struct rtl8139_private *tp = netdev_priv(dev);
2429        tp->msg_enable = datum;
2430}
2431
2432static int rtl8139_get_regs_len(struct net_device *dev)
2433{
2434        struct rtl8139_private *tp;
2435        /* TODO: we are too slack to do reg dumping for pio, for now */
2436        if (use_io)
2437                return 0;
2438        tp = netdev_priv(dev);
2439        return tp->regs_len;
2440}
2441
2442static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2443{
2444        struct rtl8139_private *tp;
2445
2446        /* TODO: we are too slack to do reg dumping for pio, for now */
2447        if (use_io)
2448                return;
2449        tp = netdev_priv(dev);
2450
2451        regs->version = RTL_REGS_VER;
2452
2453        spin_lock_irq(&tp->lock);
2454        memcpy_fromio(regbuf, tp->mmio_addr, regs->len);
2455        spin_unlock_irq(&tp->lock);
2456}
2457
2458static int rtl8139_get_sset_count(struct net_device *dev, int sset)
2459{
2460        switch (sset) {
2461        case ETH_SS_STATS:
2462                return RTL_NUM_STATS;
2463        default:
2464                return -EOPNOTSUPP;
2465        }
2466}
2467
2468static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2469{
2470        struct rtl8139_private *tp = netdev_priv(dev);
2471
2472        data[0] = tp->xstats.early_rx;
2473        data[1] = tp->xstats.tx_buf_mapped;
2474        data[2] = tp->xstats.tx_timeouts;
2475        data[3] = tp->xstats.rx_lost_in_ring;
2476}
2477
2478static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2479{
2480        memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2481}
2482
2483static const struct ethtool_ops rtl8139_ethtool_ops = {
2484        .get_drvinfo            = rtl8139_get_drvinfo,
2485        .get_regs_len           = rtl8139_get_regs_len,
2486        .get_regs               = rtl8139_get_regs,
2487        .nway_reset             = rtl8139_nway_reset,
2488        .get_link               = rtl8139_get_link,
2489        .get_msglevel           = rtl8139_get_msglevel,
2490        .set_msglevel           = rtl8139_set_msglevel,
2491        .get_wol                = rtl8139_get_wol,
2492        .set_wol                = rtl8139_set_wol,
2493        .get_strings            = rtl8139_get_strings,
2494        .get_sset_count         = rtl8139_get_sset_count,
2495        .get_ethtool_stats      = rtl8139_get_ethtool_stats,
2496        .get_link_ksettings     = rtl8139_get_link_ksettings,
2497        .set_link_ksettings     = rtl8139_set_link_ksettings,
2498};
2499
2500static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2501{
2502        struct rtl8139_private *tp = netdev_priv(dev);
2503        int rc;
2504
2505        if (!netif_running(dev))
2506                return -EINVAL;
2507
2508        spin_lock_irq(&tp->lock);
2509        rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL);
2510        spin_unlock_irq(&tp->lock);
2511
2512        return rc;
2513}
2514
2515
2516static void
2517rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
2518{
2519        struct rtl8139_private *tp = netdev_priv(dev);
2520        void __iomem *ioaddr = tp->mmio_addr;
2521        unsigned long flags;
2522        unsigned int start;
2523
2524        if (netif_running(dev)) {
2525                spin_lock_irqsave (&tp->lock, flags);
2526                dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2527                RTL_W32 (RxMissed, 0);
2528                spin_unlock_irqrestore (&tp->lock, flags);
2529        }
2530
2531        netdev_stats_to_stats64(stats, &dev->stats);
2532
2533        do {
2534                start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
2535                stats->rx_packets = tp->rx_stats.packets;
2536                stats->rx_bytes = tp->rx_stats.bytes;
2537        } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
2538
2539        do {
2540                start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
2541                stats->tx_packets = tp->tx_stats.packets;
2542                stats->tx_bytes = tp->tx_stats.bytes;
2543        } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
2544}
2545
2546/* Set or clear the multicast filter for this adaptor.
2547   This routine is not state sensitive and need not be SMP locked. */
2548
2549static void __set_rx_mode (struct net_device *dev)
2550{
2551        struct rtl8139_private *tp = netdev_priv(dev);
2552        void __iomem *ioaddr = tp->mmio_addr;
2553        u32 mc_filter[2];       /* Multicast hash filter */
2554        int rx_mode;
2555        u32 tmp;
2556
2557        netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n",
2558                   dev->flags, RTL_R32(RxConfig));
2559
2560        /* Note: do not reorder, GCC is clever about common statements. */
2561        if (dev->flags & IFF_PROMISC) {
2562                rx_mode =
2563                    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2564                    AcceptAllPhys;
2565                mc_filter[1] = mc_filter[0] = 0xffffffff;
2566        } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
2567                   (dev->flags & IFF_ALLMULTI)) {
2568                /* Too many to filter perfectly -- accept all multicasts. */
2569                rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2570                mc_filter[1] = mc_filter[0] = 0xffffffff;
2571        } else {
2572                struct netdev_hw_addr *ha;
2573                rx_mode = AcceptBroadcast | AcceptMyPhys;
2574                mc_filter[1] = mc_filter[0] = 0;
2575                netdev_for_each_mc_addr(ha, dev) {
2576                        int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2577
2578                        mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2579                        rx_mode |= AcceptMulticast;
2580                }
2581        }
2582
2583        if (dev->features & NETIF_F_RXALL)
2584                rx_mode |= (AcceptErr | AcceptRunt);
2585
2586        /* We can safely update without stopping the chip. */
2587        tmp = rtl8139_rx_config | rx_mode;
2588        if (tp->rx_config != tmp) {
2589                RTL_W32_F (RxConfig, tmp);
2590                tp->rx_config = tmp;
2591        }
2592        RTL_W32_F (MAR0 + 0, mc_filter[0]);
2593        RTL_W32_F (MAR0 + 4, mc_filter[1]);
2594}
2595
2596static void rtl8139_set_rx_mode (struct net_device *dev)
2597{
2598        unsigned long flags;
2599        struct rtl8139_private *tp = netdev_priv(dev);
2600
2601        spin_lock_irqsave (&tp->lock, flags);
2602        __set_rx_mode(dev);
2603        spin_unlock_irqrestore (&tp->lock, flags);
2604}
2605
2606static int __maybe_unused rtl8139_suspend(struct device *device)
2607{
2608        struct net_device *dev = dev_get_drvdata(device);
2609        struct rtl8139_private *tp = netdev_priv(dev);
2610        void __iomem *ioaddr = tp->mmio_addr;
2611        unsigned long flags;
2612
2613        if (!netif_running (dev))
2614                return 0;
2615
2616        netif_device_detach (dev);
2617
2618        spin_lock_irqsave (&tp->lock, flags);
2619
2620        /* Disable interrupts, stop Tx and Rx. */
2621        RTL_W16 (IntrMask, 0);
2622        RTL_W8 (ChipCmd, 0);
2623
2624        /* Update the error counts. */
2625        dev->stats.rx_missed_errors += RTL_R32 (RxMissed);
2626        RTL_W32 (RxMissed, 0);
2627
2628        spin_unlock_irqrestore (&tp->lock, flags);
2629
2630        return 0;
2631}
2632
2633static int __maybe_unused rtl8139_resume(struct device *device)
2634{
2635        struct net_device *dev = dev_get_drvdata(device);
2636
2637        if (!netif_running (dev))
2638                return 0;
2639
2640        rtl8139_init_ring (dev);
2641        rtl8139_hw_start (dev);
2642        netif_device_attach (dev);
2643        return 0;
2644}
2645
2646static SIMPLE_DEV_PM_OPS(rtl8139_pm_ops, rtl8139_suspend, rtl8139_resume);
2647
2648static struct pci_driver rtl8139_pci_driver = {
2649        .name           = DRV_NAME,
2650        .id_table       = rtl8139_pci_tbl,
2651        .probe          = rtl8139_init_one,
2652        .remove         = rtl8139_remove_one,
2653        .driver.pm      = &rtl8139_pm_ops,
2654};
2655
2656
2657static int __init rtl8139_init_module (void)
2658{
2659        /* when we're a module, we always print a version message,
2660         * even if no 8139 board is found.
2661         */
2662#ifdef MODULE
2663        pr_info(RTL8139_DRIVER_NAME "\n");
2664#endif
2665
2666        return pci_register_driver(&rtl8139_pci_driver);
2667}
2668
2669
2670static void __exit rtl8139_cleanup_module (void)
2671{
2672        pci_unregister_driver (&rtl8139_pci_driver);
2673}
2674
2675
2676module_init(rtl8139_init_module);
2677module_exit(rtl8139_cleanup_module);
2678