LXR linux/drivers/net/ethernet/realtek/r8169

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4 *
   5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7 * Copyright (c) a lot of people too. Please respect their work.
   8 *
   9 * See MAINTAINERS file for support contact information.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/pci.h>
  14#include <linux/netdevice.h>
  15#include <linux/etherdevice.h>
  16#include <linux/clk.h>
  17#include <linux/delay.h>
  18#include <linux/ethtool.h>
  19#include <linux/phy.h>
  20#include <linux/if_vlan.h>
  21#include <linux/in.h>
  22#include <linux/io.h>
  23#include <linux/ip.h>
  24#include <linux/tcp.h>
  25#include <linux/interrupt.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/bitfield.h>
  29#include <linux/prefetch.h>
  30#include <linux/ipv6.h>
  31#include <net/ip6_checksum.h>
  32
  33#include "r8169.h"
  34#include "r8169_firmware.h"
  35
  36#define MODULENAME "r8169"
  37
  38#define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39#define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40#define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41#define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42#define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43#define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44#define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45#define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46#define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47#define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48#define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49#define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50#define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51#define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52#define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53#define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54#define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55#define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  56#define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57#define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58#define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  59#define FIRMWARE_8125B_2        "rtl_nic/rtl8125b-2.fw"
  60
  61/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  62   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  63#define MC_FILTER_LIMIT 32
  64
  65#define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  66#define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  67
  68#define R8169_REGS_SIZE         256
  69#define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  70#define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  71#define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  72#define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  73#define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  74
  75#define OCP_STD_PHY_BASE        0xa400
  76
  77#define RTL_CFG_NO_GBIT 1
  78
  79/* write/read MMIO register */
  80#define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83#define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84#define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85#define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87#define JUMBO_4K        (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  88#define JUMBO_6K        (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  89#define JUMBO_7K        (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  90#define JUMBO_9K        (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
  91
  92static const struct {
  93        const char *name;
  94        const char *fw_name;
  95} rtl_chip_infos[] = {
  96        /* PCI devices. */
  97        [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
  98        [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
  99        [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 100        [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 101        [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 102        /* PCI-E devices. */
 103        [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 104        [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 105        [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 106        [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 107        [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 108        [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 109        [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e"                    },
 110        [RTL_GIGA_MAC_VER_14] = {"RTL8401"                              },
 111        [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 112        [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 113        [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 114        [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 115        [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 116        [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 117        [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 118        [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 119        [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 120        [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 121        [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 122        [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 123        [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 124        [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 125        [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 126        [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 127        [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 128        [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 129        [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 130        [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 131        [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 132        [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 133        [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 134        [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 135        [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 136        [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 137        [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 138        [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 139        [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 140        [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 141        [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 142        [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 143        [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 144        [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 145        [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 146        [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 147        [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 148        [RTL_GIGA_MAC_VER_60] = {"RTL8125A"                             },
 149        [RTL_GIGA_MAC_VER_61] = {"RTL8125A",            FIRMWARE_8125A_3},
 150        /* reserve 62 for CFG_METHOD_4 in the vendor driver */
 151        [RTL_GIGA_MAC_VER_63] = {"RTL8125B",            FIRMWARE_8125B_2},
 152};
 153
 154static const struct pci_device_id rtl8169_pci_tbl[] = {
 155        { PCI_VDEVICE(REALTEK,  0x2502) },
 156        { PCI_VDEVICE(REALTEK,  0x2600) },
 157        { PCI_VDEVICE(REALTEK,  0x8129) },
 158        { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 159        { PCI_VDEVICE(REALTEK,  0x8161) },
 160        { PCI_VDEVICE(REALTEK,  0x8167) },
 161        { PCI_VDEVICE(REALTEK,  0x8168) },
 162        { PCI_VDEVICE(NCUBE,    0x8168) },
 163        { PCI_VDEVICE(REALTEK,  0x8169) },
 164        { PCI_VENDOR_ID_DLINK,  0x4300,
 165                PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 166        { PCI_VDEVICE(DLINK,    0x4300) },
 167        { PCI_VDEVICE(DLINK,    0x4302) },
 168        { PCI_VDEVICE(AT,       0xc107) },
 169        { PCI_VDEVICE(USR,      0x0116) },
 170        { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 171        { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 172        { PCI_VDEVICE(REALTEK,  0x8125) },
 173        { PCI_VDEVICE(REALTEK,  0x3000) },
 174        {}
 175};
 176
 177MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 178
 179enum rtl_registers {
 180        MAC0            = 0,    /* Ethernet hardware address. */
 181        MAC4            = 4,
 182        MAR0            = 8,    /* Multicast filter. */
 183        CounterAddrLow          = 0x10,
 184        CounterAddrHigh         = 0x14,
 185        TxDescStartAddrLow      = 0x20,
 186        TxDescStartAddrHigh     = 0x24,
 187        TxHDescStartAddrLow     = 0x28,
 188        TxHDescStartAddrHigh    = 0x2c,
 189        FLASH           = 0x30,
 190        ERSR            = 0x36,
 191        ChipCmd         = 0x37,
 192        TxPoll          = 0x38,
 193        IntrMask        = 0x3c,
 194        IntrStatus      = 0x3e,
 195
 196        TxConfig        = 0x40,
 197#define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 198#define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 199
 200        RxConfig        = 0x44,
 201#define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 202#define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 203#define RXCFG_FIFO_SHIFT                13
 204                                        /* No threshold before first PCI xfer */
 205#define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 206#define RX_EARLY_OFF                    (1 << 11)
 207#define RXCFG_DMA_SHIFT                 8
 208                                        /* Unlimited maximum PCI burst. */
 209#define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 210
 211        Cfg9346         = 0x50,
 212        Config0         = 0x51,
 213        Config1         = 0x52,
 214        Config2         = 0x53,
 215#define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 216
 217        Config3         = 0x54,
 218        Config4         = 0x55,
 219        Config5         = 0x56,
 220        PHYAR           = 0x60,
 221        PHYstatus       = 0x6c,
 222        RxMaxSize       = 0xda,
 223        CPlusCmd        = 0xe0,
 224        IntrMitigate    = 0xe2,
 225
 226#define RTL_COALESCE_TX_USECS   GENMASK(15, 12)
 227#define RTL_COALESCE_TX_FRAMES  GENMASK(11, 8)
 228#define RTL_COALESCE_RX_USECS   GENMASK(7, 4)
 229#define RTL_COALESCE_RX_FRAMES  GENMASK(3, 0)
 230
 231#define RTL_COALESCE_T_MAX      0x0fU
 232#define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_T_MAX * 4)
 233
 234        RxDescAddrLow   = 0xe4,
 235        RxDescAddrHigh  = 0xe8,
 236        EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 237
 238#define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 239
 240        MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 241
 242#define TxPacketMax     (8064 >> 7)
 243#define EarlySize       0x27
 244
 245        FuncEvent       = 0xf0,
 246        FuncEventMask   = 0xf4,
 247        FuncPresetState = 0xf8,
 248        IBCR0           = 0xf8,
 249        IBCR2           = 0xf9,
 250        IBIMR0          = 0xfa,
 251        IBISR0          = 0xfb,
 252        FuncForceEvent  = 0xfc,
 253};
 254
 255enum rtl8168_8101_registers {
 256        CSIDR                   = 0x64,
 257        CSIAR                   = 0x68,
 258#define CSIAR_FLAG                      0x80000000
 259#define CSIAR_WRITE_CMD                 0x80000000
 260#define CSIAR_BYTE_ENABLE               0x0000f000
 261#define CSIAR_ADDR_MASK                 0x00000fff
 262        PMCH                    = 0x6f,
 263        EPHYAR                  = 0x80,
 264#define EPHYAR_FLAG                     0x80000000
 265#define EPHYAR_WRITE_CMD                0x80000000
 266#define EPHYAR_REG_MASK                 0x1f
 267#define EPHYAR_REG_SHIFT                16
 268#define EPHYAR_DATA_MASK                0xffff
 269        DLLPR                   = 0xd0,
 270#define PFM_EN                          (1 << 6)
 271#define TX_10M_PS_EN                    (1 << 7)
 272        DBG_REG                 = 0xd1,
 273#define FIX_NAK_1                       (1 << 4)
 274#define FIX_NAK_2                       (1 << 3)
 275        TWSI                    = 0xd2,
 276        MCU                     = 0xd3,
 277#define NOW_IS_OOB                      (1 << 7)
 278#define TX_EMPTY                        (1 << 5)
 279#define RX_EMPTY                        (1 << 4)
 280#define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 281#define EN_NDP                          (1 << 3)
 282#define EN_OOB_RESET                    (1 << 2)
 283#define LINK_LIST_RDY                   (1 << 1)
 284        EFUSEAR                 = 0xdc,
 285#define EFUSEAR_FLAG                    0x80000000
 286#define EFUSEAR_WRITE_CMD               0x80000000
 287#define EFUSEAR_READ_CMD                0x00000000
 288#define EFUSEAR_REG_MASK                0x03ff
 289#define EFUSEAR_REG_SHIFT               8
 290#define EFUSEAR_DATA_MASK               0xff
 291        MISC_1                  = 0xf2,
 292#define PFM_D3COLD_EN                   (1 << 6)
 293};
 294
 295enum rtl8168_registers {
 296        LED_FREQ                = 0x1a,
 297        EEE_LED                 = 0x1b,
 298        ERIDR                   = 0x70,
 299        ERIAR                   = 0x74,
 300#define ERIAR_FLAG                      0x80000000
 301#define ERIAR_WRITE_CMD                 0x80000000
 302#define ERIAR_READ_CMD                  0x00000000
 303#define ERIAR_ADDR_BYTE_ALIGN           4
 304#define ERIAR_TYPE_SHIFT                16
 305#define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 306#define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 307#define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 308#define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 309#define ERIAR_MASK_SHIFT                12
 310#define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 311#define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 312#define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 313#define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 314#define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 315        EPHY_RXER_NUM           = 0x7c,
 316        OCPDR                   = 0xb0, /* OCP GPHY access */
 317#define OCPDR_WRITE_CMD                 0x80000000
 318#define OCPDR_READ_CMD                  0x00000000
 319#define OCPDR_REG_MASK                  0x7f
 320#define OCPDR_GPHY_REG_SHIFT            16
 321#define OCPDR_DATA_MASK                 0xffff
 322        OCPAR                   = 0xb4,
 323#define OCPAR_FLAG                      0x80000000
 324#define OCPAR_GPHY_WRITE_CMD            0x8000f060
 325#define OCPAR_GPHY_READ_CMD             0x0000f060
 326        GPHY_OCP                = 0xb8,
 327        RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 328        MISC                    = 0xf0, /* 8168e only. */
 329#define TXPLA_RST                       (1 << 29)
 330#define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 331#define PWM_EN                          (1 << 22)
 332#define RXDV_GATED_EN                   (1 << 19)
 333#define EARLY_TALLY_EN                  (1 << 16)
 334};
 335
 336enum rtl8125_registers {
 337        IntrMask_8125           = 0x38,
 338        IntrStatus_8125         = 0x3c,
 339        TxPoll_8125             = 0x90,
 340        MAC0_BKP                = 0x19e0,
 341        EEE_TXIDLE_TIMER_8125   = 0x6048,
 342};
 343
 344#define RX_VLAN_INNER_8125      BIT(22)
 345#define RX_VLAN_OUTER_8125      BIT(23)
 346#define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 347
 348#define RX_FETCH_DFLT_8125      (8 << 27)
 349
 350enum rtl_register_content {
 351        /* InterruptStatusBits */
 352        SYSErr          = 0x8000,
 353        PCSTimeout      = 0x4000,
 354        SWInt           = 0x0100,
 355        TxDescUnavail   = 0x0080,
 356        RxFIFOOver      = 0x0040,
 357        LinkChg         = 0x0020,
 358        RxOverflow      = 0x0010,
 359        TxErr           = 0x0008,
 360        TxOK            = 0x0004,
 361        RxErr           = 0x0002,
 362        RxOK            = 0x0001,
 363
 364        /* RxStatusDesc */
 365        RxRWT   = (1 << 22),
 366        RxRES   = (1 << 21),
 367        RxRUNT  = (1 << 20),
 368        RxCRC   = (1 << 19),
 369
 370        /* ChipCmdBits */
 371        StopReq         = 0x80,
 372        CmdReset        = 0x10,
 373        CmdRxEnb        = 0x08,
 374        CmdTxEnb        = 0x04,
 375        RxBufEmpty      = 0x01,
 376
 377        /* TXPoll register p.5 */
 378        HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 379        NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 380        FSWInt          = 0x01,         /* Forced software interrupt */
 381
 382        /* Cfg9346Bits */
 383        Cfg9346_Lock    = 0x00,
 384        Cfg9346_Unlock  = 0xc0,
 385
 386        /* rx_mode_bits */
 387        AcceptErr       = 0x20,
 388        AcceptRunt      = 0x10,
 389#define RX_CONFIG_ACCEPT_ERR_MASK       0x30
 390        AcceptBroadcast = 0x08,
 391        AcceptMulticast = 0x04,
 392        AcceptMyPhys    = 0x02,
 393        AcceptAllPhys   = 0x01,
 394#define RX_CONFIG_ACCEPT_OK_MASK        0x0f
 395#define RX_CONFIG_ACCEPT_MASK           0x3f
 396
 397        /* TxConfigBits */
 398        TxInterFrameGapShift = 24,
 399        TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 400
 401        /* Config1 register p.24 */
 402        LEDS1           = (1 << 7),
 403        LEDS0           = (1 << 6),
 404        Speed_down      = (1 << 4),
 405        MEMMAP          = (1 << 3),
 406        IOMAP           = (1 << 2),
 407        VPD             = (1 << 1),
 408        PMEnable        = (1 << 0),     /* Power Management Enable */
 409
 410        /* Config2 register p. 25 */
 411        ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 412        MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 413        PCI_Clock_66MHz = 0x01,
 414        PCI_Clock_33MHz = 0x00,
 415
 416        /* Config3 register p.25 */
 417        MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 418        LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 419        Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 420        Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 421        Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 422
 423        /* Config4 register */
 424        Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 425
 426        /* Config5 register p.27 */
 427        BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 428        MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 429        UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 430        Spi_en          = (1 << 3),
 431        LanWake         = (1 << 1),     /* LanWake enable/disable */
 432        PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 433        ASPM_en         = (1 << 0),     /* ASPM enable */
 434
 435        /* CPlusCmd p.31 */
 436        EnableBist      = (1 << 15),    // 8168 8101
 437        Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 438        EnAnaPLL        = (1 << 14),    // 8169
 439        Normal_mode     = (1 << 13),    // unused
 440        Force_half_dup  = (1 << 12),    // 8168 8101
 441        Force_rxflow_en = (1 << 11),    // 8168 8101
 442        Force_txflow_en = (1 << 10),    // 8168 8101
 443        Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 444        ASF             = (1 << 8),     // 8168 8101
 445        PktCntrDisable  = (1 << 7),     // 8168 8101
 446        Mac_dbgo_sel    = 0x001c,       // 8168
 447        RxVlan          = (1 << 6),
 448        RxChkSum        = (1 << 5),
 449        PCIDAC          = (1 << 4),
 450        PCIMulRW        = (1 << 3),
 451#define INTT_MASK       GENMASK(1, 0)
 452#define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 453
 454        /* rtl8169_PHYstatus */
 455        TBI_Enable      = 0x80,
 456        TxFlowCtrl      = 0x40,
 457        RxFlowCtrl      = 0x20,
 458        _1000bpsF       = 0x10,
 459        _100bps         = 0x08,
 460        _10bps          = 0x04,
 461        LinkStatus      = 0x02,
 462        FullDup         = 0x01,
 463
 464        /* ResetCounterCommand */
 465        CounterReset    = 0x1,
 466
 467        /* DumpCounterCommand */
 468        CounterDump     = 0x8,
 469
 470        /* magic enable v2 */
 471        MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 472};
 473
 474enum rtl_desc_bit {
 475        /* First doubleword. */
 476        DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 477        RingEnd         = (1 << 30), /* End of descriptor ring */
 478        FirstFrag       = (1 << 29), /* First segment of a packet */
 479        LastFrag        = (1 << 28), /* Final segment of a packet */
 480};
 481
 482/* Generic case. */
 483enum rtl_tx_desc_bit {
 484        /* First doubleword. */
 485        TD_LSO          = (1 << 27),            /* Large Send Offload */
 486#define TD_MSS_MAX                      0x07ffu /* MSS value */
 487
 488        /* Second doubleword. */
 489        TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 490};
 491
 492/* 8169, 8168b and 810x except 8102e. */
 493enum rtl_tx_desc_bit_0 {
 494        /* First doubleword. */
 495#define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 496        TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 497        TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 498        TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 499};
 500
 501/* 8102e, 8168c and beyond. */
 502enum rtl_tx_desc_bit_1 {
 503        /* First doubleword. */
 504        TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 505        TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 506#define GTTCPHO_SHIFT                   18
 507#define GTTCPHO_MAX                     0x7f
 508
 509        /* Second doubleword. */
 510#define TCPHO_SHIFT                     18
 511#define TCPHO_MAX                       0x3ff
 512#define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 513        TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 514        TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 515        TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 516        TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 517};
 518
 519enum rtl_rx_desc_bit {
 520        /* Rx private */
 521        PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 522        PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 523
 524#define RxProtoUDP      (PID1)
 525#define RxProtoTCP      (PID0)
 526#define RxProtoIP       (PID1 | PID0)
 527#define RxProtoMask     RxProtoIP
 528
 529        IPFail          = (1 << 16), /* IP checksum failed */
 530        UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 531        TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 532        RxVlanTag       = (1 << 16), /* VLAN tag available */
 533};
 534
 535#define RTL_GSO_MAX_SIZE_V1     32000
 536#define RTL_GSO_MAX_SEGS_V1     24
 537#define RTL_GSO_MAX_SIZE_V2     64000
 538#define RTL_GSO_MAX_SEGS_V2     64
 539
 540struct TxDesc {
 541        __le32 opts1;
 542        __le32 opts2;
 543        __le64 addr;
 544};
 545
 546struct RxDesc {
 547        __le32 opts1;
 548        __le32 opts2;
 549        __le64 addr;
 550};
 551
 552struct ring_info {
 553        struct sk_buff  *skb;
 554        u32             len;
 555};
 556
 557struct rtl8169_counters {
 558        __le64  tx_packets;
 559        __le64  rx_packets;
 560        __le64  tx_errors;
 561        __le32  rx_errors;
 562        __le16  rx_missed;
 563        __le16  align_errors;
 564        __le32  tx_one_collision;
 565        __le32  tx_multi_collision;
 566        __le64  rx_unicast;
 567        __le64  rx_broadcast;
 568        __le32  rx_multicast;
 569        __le16  tx_aborted;
 570        __le16  tx_underun;
 571};
 572
 573struct rtl8169_tc_offsets {
 574        bool    inited;
 575        __le64  tx_errors;
 576        __le32  tx_multi_collision;
 577        __le16  tx_aborted;
 578        __le16  rx_missed;
 579};
 580
 581enum rtl_flag {
 582        RTL_FLAG_TASK_ENABLED = 0,
 583        RTL_FLAG_TASK_RESET_PENDING,
 584        RTL_FLAG_MAX
 585};
 586
 587struct rtl8169_stats {
 588        u64                     packets;
 589        u64                     bytes;
 590        struct u64_stats_sync   syncp;
 591};
 592
 593struct rtl8169_private {
 594        void __iomem *mmio_addr;        /* memory map physical address */
 595        struct pci_dev *pci_dev;
 596        struct net_device *dev;
 597        struct phy_device *phydev;
 598        struct napi_struct napi;
 599        enum mac_version mac_version;
 600        u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 601        u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 602        u32 dirty_tx;
 603        struct rtl8169_stats rx_stats;
 604        struct rtl8169_stats tx_stats;
 605        struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 606        struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 607        dma_addr_t TxPhyAddr;
 608        dma_addr_t RxPhyAddr;
 609        struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 610        struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 611        u16 cp_cmd;
 612        u32 irq_mask;
 613        struct clk *clk;
 614
 615        struct {
 616                DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 617                struct work_struct work;
 618        } wk;
 619
 620        unsigned irq_enabled:1;
 621        unsigned supports_gmii:1;
 622        unsigned aspm_manageable:1;
 623        dma_addr_t counters_phys_addr;
 624        struct rtl8169_counters *counters;
 625        struct rtl8169_tc_offsets tc_offset;
 626        u32 saved_wolopts;
 627        int eee_adv;
 628
 629        const char *fw_name;
 630        struct rtl_fw *rtl_fw;
 631
 632        u32 ocp_base;
 633};
 634
 635typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 636
 637MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 638MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 639MODULE_SOFTDEP("pre: realtek");
 640MODULE_LICENSE("GPL");
 641MODULE_FIRMWARE(FIRMWARE_8168D_1);
 642MODULE_FIRMWARE(FIRMWARE_8168D_2);
 643MODULE_FIRMWARE(FIRMWARE_8168E_1);
 644MODULE_FIRMWARE(FIRMWARE_8168E_2);
 645MODULE_FIRMWARE(FIRMWARE_8168E_3);
 646MODULE_FIRMWARE(FIRMWARE_8105E_1);
 647MODULE_FIRMWARE(FIRMWARE_8168F_1);
 648MODULE_FIRMWARE(FIRMWARE_8168F_2);
 649MODULE_FIRMWARE(FIRMWARE_8402_1);
 650MODULE_FIRMWARE(FIRMWARE_8411_1);
 651MODULE_FIRMWARE(FIRMWARE_8411_2);
 652MODULE_FIRMWARE(FIRMWARE_8106E_1);
 653MODULE_FIRMWARE(FIRMWARE_8106E_2);
 654MODULE_FIRMWARE(FIRMWARE_8168G_2);
 655MODULE_FIRMWARE(FIRMWARE_8168G_3);
 656MODULE_FIRMWARE(FIRMWARE_8168H_1);
 657MODULE_FIRMWARE(FIRMWARE_8168H_2);
 658MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 659MODULE_FIRMWARE(FIRMWARE_8107E_1);
 660MODULE_FIRMWARE(FIRMWARE_8107E_2);
 661MODULE_FIRMWARE(FIRMWARE_8125A_3);
 662MODULE_FIRMWARE(FIRMWARE_8125B_2);
 663
 664static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 665{
 666        return &tp->pci_dev->dev;
 667}
 668
 669static void rtl_lock_config_regs(struct rtl8169_private *tp)
 670{
 671        RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 672}
 673
 674static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 675{
 676        RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 677}
 678
 679static void rtl_pci_commit(struct rtl8169_private *tp)
 680{
 681        /* Read an arbitrary register to commit a preceding PCI write */
 682        RTL_R8(tp, ChipCmd);
 683}
 684
 685static bool rtl_is_8125(struct rtl8169_private *tp)
 686{
 687        return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 688}
 689
 690static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 691{
 692        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 693               tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 694               tp->mac_version <= RTL_GIGA_MAC_VER_52;
 695}
 696
 697static bool rtl_supports_eee(struct rtl8169_private *tp)
 698{
 699        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 700               tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 701               tp->mac_version != RTL_GIGA_MAC_VER_39;
 702}
 703
 704static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 705{
 706        int i;
 707
 708        for (i = 0; i < ETH_ALEN; i++)
 709                mac[i] = RTL_R8(tp, reg + i);
 710}
 711
 712struct rtl_cond {
 713        bool (*check)(struct rtl8169_private *);
 714        const char *msg;
 715};
 716
 717static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 718                          unsigned long usecs, int n, bool high)
 719{
 720        int i;
 721
 722        for (i = 0; i < n; i++) {
 723                if (c->check(tp) == high)
 724                        return true;
 725                fsleep(usecs);
 726        }
 727
 728        if (net_ratelimit())
 729                netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
 730                           c->msg, !high, n, usecs);
 731        return false;
 732}
 733
 734static bool rtl_loop_wait_high(struct rtl8169_private *tp,
 735                               const struct rtl_cond *c,
 736                               unsigned long d, int n)
 737{
 738        return rtl_loop_wait(tp, c, d, n, true);
 739}
 740
 741static bool rtl_loop_wait_low(struct rtl8169_private *tp,
 742                              const struct rtl_cond *c,
 743                              unsigned long d, int n)
 744{
 745        return rtl_loop_wait(tp, c, d, n, false);
 746}
 747
 748#define DECLARE_RTL_COND(name)                          \
 749static bool name ## _check(struct rtl8169_private *);   \
 750                                                        \
 751static const struct rtl_cond name = {                   \
 752        .check  = name ## _check,                       \
 753        .msg    = #name                                 \
 754};                                                      \
 755                                                        \
 756static bool name ## _check(struct rtl8169_private *tp)
 757
 758static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 759{
 760        if (reg & 0xffff0001) {
 761                if (net_ratelimit())
 762                        netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
 763                return true;
 764        }
 765        return false;
 766}
 767
 768DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 769{
 770        return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 771}
 772
 773static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 774{
 775        if (rtl_ocp_reg_failure(tp, reg))
 776                return;
 777
 778        RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 779
 780        rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 781}
 782
 783static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 784{
 785        if (rtl_ocp_reg_failure(tp, reg))
 786                return 0;
 787
 788        RTL_W32(tp, GPHY_OCP, reg << 15);
 789
 790        return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 791                (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 792}
 793
 794static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 795{
 796        if (rtl_ocp_reg_failure(tp, reg))
 797                return;
 798
 799        RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 800}
 801
 802static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 803{
 804        if (rtl_ocp_reg_failure(tp, reg))
 805                return 0;
 806
 807        RTL_W32(tp, OCPDR, reg << 15);
 808
 809        return RTL_R32(tp, OCPDR);
 810}
 811
 812static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 813                                 u16 set)
 814{
 815        u16 data = r8168_mac_ocp_read(tp, reg);
 816
 817        r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 818}
 819
 820static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 821{
 822        if (reg == 0x1f) {
 823                tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 824                return;
 825        }
 826
 827        if (tp->ocp_base != OCP_STD_PHY_BASE)
 828                reg -= 0x10;
 829
 830        r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 831}
 832
 833static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 834{
 835        if (reg == 0x1f)
 836                return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 837
 838        if (tp->ocp_base != OCP_STD_PHY_BASE)
 839                reg -= 0x10;
 840
 841        return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 842}
 843
 844static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 845{
 846        if (reg == 0x1f) {
 847                tp->ocp_base = value << 4;
 848                return;
 849        }
 850
 851        r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 852}
 853
 854static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 855{
 856        return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 857}
 858
 859DECLARE_RTL_COND(rtl_phyar_cond)
 860{
 861        return RTL_R32(tp, PHYAR) & 0x80000000;
 862}
 863
 864static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 865{
 866        RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 867
 868        rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 869        /*
 870         * According to hardware specs a 20us delay is required after write
 871         * complete indication, but before sending next command.
 872         */
 873        udelay(20);
 874}
 875
 876static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 877{
 878        int value;
 879
 880        RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 881
 882        value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 883                RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 884
 885        /*
 886         * According to hardware specs a 20us delay is required after read
 887         * complete indication, but before sending next command.
 888         */
 889        udelay(20);
 890
 891        return value;
 892}
 893
 894DECLARE_RTL_COND(rtl_ocpar_cond)
 895{
 896        return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 897}
 898
 899static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 900{
 901        RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 902        RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 903        RTL_W32(tp, EPHY_RXER_NUM, 0);
 904
 905        rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 906}
 907
 908static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 909{
 910        r8168dp_1_mdio_access(tp, reg,
 911                              OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 912}
 913
 914static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 915{
 916        r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 917
 918        mdelay(1);
 919        RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 920        RTL_W32(tp, EPHY_RXER_NUM, 0);
 921
 922        return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 923                RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
 924}
 925
 926#define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 927
 928static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 929{
 930        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 931}
 932
 933static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 934{
 935        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 936}
 937
 938static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 939{
 940        r8168dp_2_mdio_start(tp);
 941
 942        r8169_mdio_write(tp, reg, value);
 943
 944        r8168dp_2_mdio_stop(tp);
 945}
 946
 947static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
 948{
 949        int value;
 950
 951        /* Work around issue with chip reporting wrong PHY ID */
 952        if (reg == MII_PHYSID2)
 953                return 0xc912;
 954
 955        r8168dp_2_mdio_start(tp);
 956
 957        value = r8169_mdio_read(tp, reg);
 958
 959        r8168dp_2_mdio_stop(tp);
 960
 961        return value;
 962}
 963
 964static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
 965{
 966        switch (tp->mac_version) {
 967        case RTL_GIGA_MAC_VER_27:
 968                r8168dp_1_mdio_write(tp, location, val);
 969                break;
 970        case RTL_GIGA_MAC_VER_28:
 971        case RTL_GIGA_MAC_VER_31:
 972                r8168dp_2_mdio_write(tp, location, val);
 973                break;
 974        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 975                r8168g_mdio_write(tp, location, val);
 976                break;
 977        default:
 978                r8169_mdio_write(tp, location, val);
 979                break;
 980        }
 981}
 982
 983static int rtl_readphy(struct rtl8169_private *tp, int location)
 984{
 985        switch (tp->mac_version) {
 986        case RTL_GIGA_MAC_VER_27:
 987                return r8168dp_1_mdio_read(tp, location);
 988        case RTL_GIGA_MAC_VER_28:
 989        case RTL_GIGA_MAC_VER_31:
 990                return r8168dp_2_mdio_read(tp, location);
 991        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
 992                return r8168g_mdio_read(tp, location);
 993        default:
 994                return r8169_mdio_read(tp, location);
 995        }
 996}
 997
 998DECLARE_RTL_COND(rtl_ephyar_cond)
 999{
1000        return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;

1001}
1002
1003static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1004{
1005        RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1006                (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1007
1008        rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1009
1010        udelay(10);
1011}
1012
1013static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1014{
1015        RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1016
1017        return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1018                RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1019}
1020
1021static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1022{
1023        /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
1024        if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1025                *cmd |= 0x7f0 << 18;
1026}
1027
1028DECLARE_RTL_COND(rtl_eriar_cond)
1029{
1030        return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1031}
1032
1033static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1034                           u32 val, int type)
1035{
1036        u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
1037
1038        BUG_ON((addr & 3) || (mask == 0));
1039        RTL_W32(tp, ERIDR, val);
1040        r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1041        RTL_W32(tp, ERIAR, cmd);
1042
1043        rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1044}
1045
1046static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1047                          u32 val)
1048{
1049        _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1050}
1051
1052static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1053{
1054        u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
1055
1056        r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1057        RTL_W32(tp, ERIAR, cmd);
1058
1059        return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1060                RTL_R32(tp, ERIDR) : ~0;
1061}
1062
1063static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1064{
1065        return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1066}
1067
1068static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1069{
1070        u32 val = rtl_eri_read(tp, addr);
1071
1072        rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1073}
1074
1075static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1076{
1077        rtl_w0w1_eri(tp, addr, p, 0);
1078}
1079
1080static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1081{
1082        rtl_w0w1_eri(tp, addr, 0, m);
1083}
1084
1085static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1086{
1087        RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1088        return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1089                RTL_R32(tp, OCPDR) : ~0;
1090}
1091
1092static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1093{
1094        return _rtl_eri_read(tp, reg, ERIAR_OOB);
1095}
1096
1097static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1098                              u32 data)
1099{
1100        RTL_W32(tp, OCPDR, data);
1101        RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1102        rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1103}
1104
1105static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1106                              u32 data)
1107{
1108        _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1109                       data, ERIAR_OOB);
1110}
1111
1112static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1113{
1114        rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1115
1116        r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1117}
1118
1119#define OOB_CMD_RESET           0x00
1120#define OOB_CMD_DRIVER_START    0x05
1121#define OOB_CMD_DRIVER_STOP     0x06
1122
1123static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1124{
1125        return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1126}
1127
1128DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1129{
1130        u16 reg;
1131
1132        reg = rtl8168_get_ocp_reg(tp);
1133
1134        return r8168dp_ocp_read(tp, reg) & 0x00000800;
1135}
1136
1137DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1138{
1139        return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1140}
1141
1142DECLARE_RTL_COND(rtl_ocp_tx_cond)
1143{
1144        return RTL_R8(tp, IBISR0) & 0x20;
1145}
1146
1147static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1148{
1149        RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1150        rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1151        RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1152        RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1153}
1154
1155static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1156{
1157        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1158        rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1159}
1160
1161static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1162{
1163        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1164        r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1165        rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1166}
1167
1168static void rtl8168_driver_start(struct rtl8169_private *tp)
1169{
1170        switch (tp->mac_version) {
1171        case RTL_GIGA_MAC_VER_27:
1172        case RTL_GIGA_MAC_VER_28:
1173        case RTL_GIGA_MAC_VER_31:
1174                rtl8168dp_driver_start(tp);
1175                break;
1176        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1177                rtl8168ep_driver_start(tp);
1178                break;
1179        default:
1180                BUG();
1181                break;
1182        }
1183}
1184
1185static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1186{
1187        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1188        rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1189}
1190
1191static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1192{
1193        rtl8168ep_stop_cmac(tp);
1194        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1195        r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1196        rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1197}
1198
1199static void rtl8168_driver_stop(struct rtl8169_private *tp)
1200{
1201        switch (tp->mac_version) {
1202        case RTL_GIGA_MAC_VER_27:
1203        case RTL_GIGA_MAC_VER_28:
1204        case RTL_GIGA_MAC_VER_31:
1205                rtl8168dp_driver_stop(tp);
1206                break;
1207        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1208                rtl8168ep_driver_stop(tp);
1209                break;
1210        default:
1211                BUG();
1212                break;
1213        }
1214}
1215
1216static bool r8168dp_check_dash(struct rtl8169_private *tp)
1217{
1218        u16 reg = rtl8168_get_ocp_reg(tp);
1219
1220        return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1221}
1222
1223static bool r8168ep_check_dash(struct rtl8169_private *tp)
1224{
1225        return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1226}
1227
1228static bool r8168_check_dash(struct rtl8169_private *tp)
1229{
1230        switch (tp->mac_version) {
1231        case RTL_GIGA_MAC_VER_27:
1232        case RTL_GIGA_MAC_VER_28:
1233        case RTL_GIGA_MAC_VER_31:
1234                return r8168dp_check_dash(tp);
1235        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1236                return r8168ep_check_dash(tp);
1237        default:
1238                return false;
1239        }
1240}
1241
1242static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1243{
1244        rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1245        rtl_eri_set_bits(tp, 0xdc, BIT(0));
1246}
1247
1248DECLARE_RTL_COND(rtl_efusear_cond)
1249{
1250        return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1251}
1252
1253u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1254{
1255        RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1256
1257        return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1258                RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1259}
1260
1261static u32 rtl_get_events(struct rtl8169_private *tp)
1262{
1263        if (rtl_is_8125(tp))
1264                return RTL_R32(tp, IntrStatus_8125);
1265        else
1266                return RTL_R16(tp, IntrStatus);
1267}
1268
1269static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1270{
1271        if (rtl_is_8125(tp))
1272                RTL_W32(tp, IntrStatus_8125, bits);
1273        else
1274                RTL_W16(tp, IntrStatus, bits);
1275}
1276
1277static void rtl_irq_disable(struct rtl8169_private *tp)
1278{
1279        if (rtl_is_8125(tp))
1280                RTL_W32(tp, IntrMask_8125, 0);
1281        else
1282                RTL_W16(tp, IntrMask, 0);
1283        tp->irq_enabled = 0;
1284}
1285
1286static void rtl_irq_enable(struct rtl8169_private *tp)
1287{
1288        tp->irq_enabled = 1;
1289        if (rtl_is_8125(tp))
1290                RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1291        else
1292                RTL_W16(tp, IntrMask, tp->irq_mask);
1293}
1294
1295static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1296{
1297        rtl_irq_disable(tp);
1298        rtl_ack_events(tp, 0xffffffff);
1299        rtl_pci_commit(tp);
1300}
1301
1302static void rtl_link_chg_patch(struct rtl8169_private *tp)
1303{
1304        struct phy_device *phydev = tp->phydev;
1305
1306        if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1307            tp->mac_version == RTL_GIGA_MAC_VER_38) {
1308                if (phydev->speed == SPEED_1000) {
1309                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1310                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1311                } else if (phydev->speed == SPEED_100) {
1312                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1313                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1314                } else {
1315                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1316                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1317                }
1318                rtl_reset_packet_filter(tp);
1319        } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1320                   tp->mac_version == RTL_GIGA_MAC_VER_36) {
1321                if (phydev->speed == SPEED_1000) {
1322                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1323                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1324                } else {
1325                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1326                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1327                }
1328        } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1329                if (phydev->speed == SPEED_10) {
1330                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1331                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1332                } else {
1333                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1334                }
1335        }
1336}
1337
1338#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1339
1340static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1341{
1342        struct rtl8169_private *tp = netdev_priv(dev);
1343
1344        wol->supported = WAKE_ANY;
1345        wol->wolopts = tp->saved_wolopts;
1346}
1347
1348static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1349{
1350        static const struct {
1351                u32 opt;
1352                u16 reg;
1353                u8  mask;
1354        } cfg[] = {
1355                { WAKE_PHY,   Config3, LinkUp },
1356                { WAKE_UCAST, Config5, UWF },
1357                { WAKE_BCAST, Config5, BWF },
1358                { WAKE_MCAST, Config5, MWF },
1359                { WAKE_ANY,   Config5, LanWake },
1360                { WAKE_MAGIC, Config3, MagicPacket }
1361        };
1362        unsigned int i, tmp = ARRAY_SIZE(cfg);
1363        u8 options;
1364
1365        rtl_unlock_config_regs(tp);
1366
1367        if (rtl_is_8168evl_up(tp)) {
1368                tmp--;
1369                if (wolopts & WAKE_MAGIC)
1370                        rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1371                else
1372                        rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1373        } else if (rtl_is_8125(tp)) {
1374                tmp--;
1375                if (wolopts & WAKE_MAGIC)
1376                        r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1377                else
1378                        r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1379        }
1380
1381        for (i = 0; i < tmp; i++) {
1382                options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1383                if (wolopts & cfg[i].opt)
1384                        options |= cfg[i].mask;
1385                RTL_W8(tp, cfg[i].reg, options);
1386        }
1387
1388        switch (tp->mac_version) {
1389        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1390                options = RTL_R8(tp, Config1) & ~PMEnable;
1391                if (wolopts)
1392                        options |= PMEnable;
1393                RTL_W8(tp, Config1, options);
1394                break;
1395        case RTL_GIGA_MAC_VER_34:
1396        case RTL_GIGA_MAC_VER_37:
1397        case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1398                options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1399                if (wolopts)
1400                        options |= PME_SIGNAL;
1401                RTL_W8(tp, Config2, options);
1402                break;
1403        default:
1404                break;
1405        }
1406
1407        rtl_lock_config_regs(tp);
1408
1409        device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1410        tp->dev->wol_enabled = wolopts ? 1 : 0;
1411}
1412
1413static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1414{
1415        struct rtl8169_private *tp = netdev_priv(dev);
1416
1417        if (wol->wolopts & ~WAKE_ANY)
1418                return -EINVAL;
1419
1420        tp->saved_wolopts = wol->wolopts;
1421        __rtl8169_set_wol(tp, tp->saved_wolopts);
1422
1423        return 0;
1424}
1425
1426static void rtl8169_get_drvinfo(struct net_device *dev,
1427                                struct ethtool_drvinfo *info)
1428{
1429        struct rtl8169_private *tp = netdev_priv(dev);
1430        struct rtl_fw *rtl_fw = tp->rtl_fw;
1431
1432        strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1433        strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1434        BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1435        if (rtl_fw)
1436                strlcpy(info->fw_version, rtl_fw->version,
1437                        sizeof(info->fw_version));
1438}
1439
1440static int rtl8169_get_regs_len(struct net_device *dev)
1441{
1442        return R8169_REGS_SIZE;
1443}
1444
1445static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1446        netdev_features_t features)
1447{
1448        struct rtl8169_private *tp = netdev_priv(dev);
1449
1450        if (dev->mtu > TD_MSS_MAX)
1451                features &= ~NETIF_F_ALL_TSO;
1452
1453        if (dev->mtu > ETH_DATA_LEN &&
1454            tp->mac_version > RTL_GIGA_MAC_VER_06)
1455                features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1456
1457        return features;
1458}
1459
1460static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1461                                       netdev_features_t features)
1462{
1463        u32 rx_config = RTL_R32(tp, RxConfig);
1464
1465        if (features & NETIF_F_RXALL)
1466                rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1467        else
1468                rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1469
1470        if (rtl_is_8125(tp)) {
1471                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1472                        rx_config |= RX_VLAN_8125;
1473                else
1474                        rx_config &= ~RX_VLAN_8125;
1475        }
1476
1477        RTL_W32(tp, RxConfig, rx_config);
1478}
1479
1480static int rtl8169_set_features(struct net_device *dev,
1481                                netdev_features_t features)
1482{
1483        struct rtl8169_private *tp = netdev_priv(dev);
1484
1485        rtl_set_rx_config_features(tp, features);
1486
1487        if (features & NETIF_F_RXCSUM)
1488                tp->cp_cmd |= RxChkSum;
1489        else
1490                tp->cp_cmd &= ~RxChkSum;
1491
1492        if (!rtl_is_8125(tp)) {
1493                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1494                        tp->cp_cmd |= RxVlan;
1495                else
1496                        tp->cp_cmd &= ~RxVlan;
1497        }
1498
1499        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1500        rtl_pci_commit(tp);
1501
1502        return 0;
1503}
1504
1505static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1506{
1507        return (skb_vlan_tag_present(skb)) ?
1508                TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1509}
1510
1511static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1512{
1513        u32 opts2 = le32_to_cpu(desc->opts2);
1514
1515        if (opts2 & RxVlanTag)
1516                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1517}
1518
1519static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1520                             void *p)
1521{
1522        struct rtl8169_private *tp = netdev_priv(dev);
1523        u32 __iomem *data = tp->mmio_addr;
1524        u32 *dw = p;
1525        int i;
1526
1527        for (i = 0; i < R8169_REGS_SIZE; i += 4)
1528                memcpy_fromio(dw++, data++, 4);
1529}
1530
1531static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1532        "tx_packets",
1533        "rx_packets",
1534        "tx_errors",
1535        "rx_errors",
1536        "rx_missed",
1537        "align_errors",
1538        "tx_single_collisions",
1539        "tx_multi_collisions",
1540        "unicast",
1541        "broadcast",
1542        "multicast",
1543        "tx_aborted",
1544        "tx_underrun",
1545};
1546
1547static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1548{
1549        switch (sset) {
1550        case ETH_SS_STATS:
1551                return ARRAY_SIZE(rtl8169_gstrings);
1552        default:
1553                return -EOPNOTSUPP;
1554        }
1555}
1556
1557DECLARE_RTL_COND(rtl_counters_cond)
1558{
1559        return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1560}
1561
1562static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1563{
1564        dma_addr_t paddr = tp->counters_phys_addr;
1565        u32 cmd;
1566
1567        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1568        rtl_pci_commit(tp);
1569        cmd = (u64)paddr & DMA_BIT_MASK(32);
1570        RTL_W32(tp, CounterAddrLow, cmd);
1571        RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1572
1573        rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1574}
1575
1576static void rtl8169_reset_counters(struct rtl8169_private *tp)
1577{
1578        /*
1579         * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1580         * tally counters.
1581         */
1582        if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1583                rtl8169_do_counters(tp, CounterReset);
1584}
1585
1586static void rtl8169_update_counters(struct rtl8169_private *tp)
1587{
1588        u8 val = RTL_R8(tp, ChipCmd);
1589
1590        /*
1591         * Some chips are unable to dump tally counters when the receiver
1592         * is disabled. If 0xff chip may be in a PCI power-save state.
1593         */
1594        if (val & CmdRxEnb && val != 0xff)
1595                rtl8169_do_counters(tp, CounterDump);
1596}
1597
1598static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1599{
1600        struct rtl8169_counters *counters = tp->counters;
1601
1602        /*
1603         * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1604         * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1605         * reset by a power cycle, while the counter values collected by the
1606         * driver are reset at every driver unload/load cycle.
1607         *
1608         * To make sure the HW values returned by @get_stats64 match the SW
1609         * values, we collect the initial values at first open(*) and use them
1610         * as offsets to normalize the values returned by @get_stats64.
1611         *
1612         * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1613         * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1614         * set at open time by rtl_hw_start.
1615         */
1616
1617        if (tp->tc_offset.inited)
1618                return;
1619
1620        rtl8169_reset_counters(tp);
1621        rtl8169_update_counters(tp);
1622
1623        tp->tc_offset.tx_errors = counters->tx_errors;
1624        tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1625        tp->tc_offset.tx_aborted = counters->tx_aborted;
1626        tp->tc_offset.rx_missed = counters->rx_missed;
1627        tp->tc_offset.inited = true;
1628}
1629
1630static void rtl8169_get_ethtool_stats(struct net_device *dev,
1631                                      struct ethtool_stats *stats, u64 *data)
1632{
1633        struct rtl8169_private *tp = netdev_priv(dev);
1634        struct rtl8169_counters *counters;
1635
1636        counters = tp->counters;
1637        rtl8169_update_counters(tp);
1638
1639        data[0] = le64_to_cpu(counters->tx_packets);
1640        data[1] = le64_to_cpu(counters->rx_packets);
1641        data[2] = le64_to_cpu(counters->tx_errors);
1642        data[3] = le32_to_cpu(counters->rx_errors);
1643        data[4] = le16_to_cpu(counters->rx_missed);
1644        data[5] = le16_to_cpu(counters->align_errors);
1645        data[6] = le32_to_cpu(counters->tx_one_collision);
1646        data[7] = le32_to_cpu(counters->tx_multi_collision);
1647        data[8] = le64_to_cpu(counters->rx_unicast);
1648        data[9] = le64_to_cpu(counters->rx_broadcast);
1649        data[10] = le32_to_cpu(counters->rx_multicast);
1650        data[11] = le16_to_cpu(counters->tx_aborted);
1651        data[12] = le16_to_cpu(counters->tx_underun);
1652}
1653
1654static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1655{
1656        switch(stringset) {
1657        case ETH_SS_STATS:
1658                memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1659                break;
1660        }
1661}
1662
1663/*
1664 * Interrupt coalescing
1665 *
1666 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1667 * >     8169, 8168 and 810x line of chipsets
1668 *
1669 * 8169, 8168, and 8136(810x) serial chipsets support it.
1670 *
1671 * > 2 - the Tx timer unit at gigabit speed
1672 *
1673 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1674 * (0xe0) bit 1 and bit 0.
1675 *
1676 * For 8169
1677 * bit[1:0] \ speed        1000M           100M            10M
1678 * 0 0                     320ns           2.56us          40.96us
1679 * 0 1                     2.56us          20.48us         327.7us
1680 * 1 0                     5.12us          40.96us         655.4us
1681 * 1 1                     10.24us         81.92us         1.31ms
1682 *
1683 * For the other
1684 * bit[1:0] \ speed        1000M           100M            10M
1685 * 0 0                     5us             2.56us          40.96us
1686 * 0 1                     40us            20.48us         327.7us
1687 * 1 0                     80us            40.96us         655.4us
1688 * 1 1                     160us           81.92us         1.31ms
1689 */
1690
1691/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1692struct rtl_coalesce_info {
1693        u32 speed;
1694        u32 scale_nsecs[4];
1695};
1696
1697/* produce array with base delay *1, *8, *8*2, *8*2*2 */
1698#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1699
1700static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1701        { SPEED_1000,   COALESCE_DELAY(320) },
1702        { SPEED_100,    COALESCE_DELAY(2560) },
1703        { SPEED_10,     COALESCE_DELAY(40960) },
1704        { 0 },
1705};
1706
1707static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1708        { SPEED_1000,   COALESCE_DELAY(5000) },
1709        { SPEED_100,    COALESCE_DELAY(2560) },
1710        { SPEED_10,     COALESCE_DELAY(40960) },
1711        { 0 },
1712};
1713#undef COALESCE_DELAY
1714
1715/* get rx/tx scale vector corresponding to current speed */
1716static const struct rtl_coalesce_info *
1717rtl_coalesce_info(struct rtl8169_private *tp)
1718{
1719        const struct rtl_coalesce_info *ci;
1720
1721        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1722                ci = rtl_coalesce_info_8169;
1723        else
1724                ci = rtl_coalesce_info_8168_8136;
1725
1726        /* if speed is unknown assume highest one */
1727        if (tp->phydev->speed == SPEED_UNKNOWN)
1728                return ci;
1729
1730        for (; ci->speed; ci++) {
1731                if (tp->phydev->speed == ci->speed)
1732                        return ci;
1733        }
1734
1735        return ERR_PTR(-ELNRNG);
1736}
1737
1738static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1739{
1740        struct rtl8169_private *tp = netdev_priv(dev);
1741        const struct rtl_coalesce_info *ci;
1742        u32 scale, c_us, c_fr;
1743        u16 intrmit;
1744
1745        if (rtl_is_8125(tp))
1746                return -EOPNOTSUPP;
1747
1748        memset(ec, 0, sizeof(*ec));
1749
1750        /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1751        ci = rtl_coalesce_info(tp);
1752        if (IS_ERR(ci))
1753                return PTR_ERR(ci);
1754
1755        scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1756
1757        intrmit = RTL_R16(tp, IntrMitigate);
1758
1759        c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1760        ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1761
1762        c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1763        /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1764        ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1765
1766        c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1767        ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1768
1769        c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1770        ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1771
1772        return 0;
1773}
1774
1775/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1776static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1777                                     u16 *cp01)
1778{
1779        const struct rtl_coalesce_info *ci;
1780        u16 i;
1781
1782        ci = rtl_coalesce_info(tp);
1783        if (IS_ERR(ci))
1784                return PTR_ERR(ci);
1785
1786        for (i = 0; i < 4; i++) {
1787                if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1788                        *cp01 = i;
1789                        return ci->scale_nsecs[i];
1790                }
1791        }
1792
1793        return -ERANGE;
1794}
1795
1796static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1797{
1798        struct rtl8169_private *tp = netdev_priv(dev);
1799        u32 tx_fr = ec->tx_max_coalesced_frames;
1800        u32 rx_fr = ec->rx_max_coalesced_frames;
1801        u32 coal_usec_max, units;
1802        u16 w = 0, cp01 = 0;
1803        int scale;
1804
1805        if (rtl_is_8125(tp))
1806                return -EOPNOTSUPP;
1807
1808        if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1809                return -ERANGE;
1810
1811        coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1812        scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1813        if (scale < 0)
1814                return scale;
1815
1816        /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1817         * not only when usecs=0 because of e.g. the following scenario:
1818         *
1819         * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1820         * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1821         * - then user does `ethtool -C eth0 rx-usecs 100`
1822         *
1823         * Since ethtool sends to kernel whole ethtool_coalesce settings,
1824         * if we want to ignore rx_frames then it has to be set to 0.
1825         */
1826        if (rx_fr == 1)
1827                rx_fr = 0;
1828        if (tx_fr == 1)
1829                tx_fr = 0;
1830
1831        /* HW requires time limit to be set if frame limit is set */
1832        if ((tx_fr && !ec->tx_coalesce_usecs) ||
1833            (rx_fr && !ec->rx_coalesce_usecs))
1834                return -EINVAL;
1835
1836        w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1837        w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1838
1839        units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1840        w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1841        units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1842        w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1843
1844        RTL_W16(tp, IntrMitigate, w);
1845
1846        /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1847        if (rtl_is_8168evl_up(tp)) {
1848                if (!rx_fr && !tx_fr)
1849                        /* disable packet counter */
1850                        tp->cp_cmd |= PktCntrDisable;
1851                else
1852                        tp->cp_cmd &= ~PktCntrDisable;
1853        }
1854
1855        tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1856        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1857        rtl_pci_commit(tp);
1858
1859        return 0;
1860}
1861
1862static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1863{
1864        struct rtl8169_private *tp = netdev_priv(dev);
1865
1866        if (!rtl_supports_eee(tp))
1867                return -EOPNOTSUPP;
1868
1869        return phy_ethtool_get_eee(tp->phydev, data);
1870}
1871
1872static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1873{
1874        struct rtl8169_private *tp = netdev_priv(dev);
1875        int ret;
1876
1877        if (!rtl_supports_eee(tp))
1878                return -EOPNOTSUPP;
1879
1880        ret = phy_ethtool_set_eee(tp->phydev, data);
1881
1882        if (!ret)
1883                tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1884                                           MDIO_AN_EEE_ADV);
1885        return ret;
1886}
1887
1888static const struct ethtool_ops rtl8169_ethtool_ops = {
1889        .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1890                                     ETHTOOL_COALESCE_MAX_FRAMES,
1891        .get_drvinfo            = rtl8169_get_drvinfo,
1892        .get_regs_len           = rtl8169_get_regs_len,
1893        .get_link               = ethtool_op_get_link,
1894        .get_coalesce           = rtl_get_coalesce,
1895        .set_coalesce           = rtl_set_coalesce,
1896        .get_regs               = rtl8169_get_regs,
1897        .get_wol                = rtl8169_get_wol,
1898        .set_wol                = rtl8169_set_wol,
1899        .get_strings            = rtl8169_get_strings,
1900        .get_sset_count         = rtl8169_get_sset_count,
1901        .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1902        .get_ts_info            = ethtool_op_get_ts_info,
1903        .nway_reset             = phy_ethtool_nway_reset,
1904        .get_eee                = rtl8169_get_eee,
1905        .set_eee                = rtl8169_set_eee,
1906        .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1907        .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1908};
1909
1910static void rtl_enable_eee(struct rtl8169_private *tp)
1911{
1912        struct phy_device *phydev = tp->phydev;
1913        int adv;
1914
1915        /* respect EEE advertisement the user may have set */
1916        if (tp->eee_adv >= 0)
1917                adv = tp->eee_adv;
1918        else
1919                adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1920
1921        if (adv >= 0)
1922                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1923}
1924
1925static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1926{
1927        /*
1928         * The driver currently handles the 8168Bf and the 8168Be identically
1929         * but they can be identified more specifically through the test below
1930         * if needed:
1931         *
1932         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1933         *
1934         * Same thing for the 8101Eb and the 8101Ec:
1935         *
1936         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1937         */
1938        static const struct rtl_mac_info {
1939                u16 mask;
1940                u16 val;
1941                enum mac_version ver;
1942        } mac_info[] = {
1943                /* 8125B family. */
1944                { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
1945
1946                /* 8125A family. */
1947                { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
1948                { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
1949
1950                /* RTL8117 */
1951                { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
1952
1953                /* 8168EP family. */
1954                { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
1955                { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
1956                { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
1957
1958                /* 8168H family. */
1959                { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
1960                { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
1961
1962                /* 8168G family. */
1963                { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
1964                { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
1965                { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
1966                { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
1967
1968                /* 8168F family. */
1969                { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
1970                { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
1971                { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
1972
1973                /* 8168E family. */
1974                { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
1975                { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
1976                { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
1977
1978                /* 8168D family. */
1979                { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
1980                { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
1981
1982                /* 8168DP family. */
1983                { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
1984                { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
1985                { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
1986
1987                /* 8168C family. */
1988                { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
1989                { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
1990                { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
1991                { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
1992                { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
1993                { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
1994                { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
1995
1996                /* 8168B family. */
1997                { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
1998                { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
1999                { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2000

2001                /* 8101 family. */
2002                { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2003                { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2004                { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2005                { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2006                { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2007                { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2008                { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2009                { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2010                { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2011                { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2012                { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2013                { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2014                { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2015                { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2016                { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2017                /* FIXME: where did these entries come from ? -- FR */
2018                { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2019                { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2020
2021                /* 8110 family. */
2022                { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2023                { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2024                { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2025                { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2026                { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2027
2028                /* Catch-all */
2029                { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2030        };
2031        const struct rtl_mac_info *p = mac_info;
2032        enum mac_version ver;
2033
2034        while ((xid & p->mask) != p->val)
2035                p++;
2036        ver = p->ver;
2037
2038        if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2039                if (ver == RTL_GIGA_MAC_VER_42)
2040                        ver = RTL_GIGA_MAC_VER_43;
2041                else if (ver == RTL_GIGA_MAC_VER_45)
2042                        ver = RTL_GIGA_MAC_VER_47;
2043                else if (ver == RTL_GIGA_MAC_VER_46)
2044                        ver = RTL_GIGA_MAC_VER_48;
2045        }
2046
2047        return ver;
2048}
2049
2050static void rtl_release_firmware(struct rtl8169_private *tp)
2051{
2052        if (tp->rtl_fw) {
2053                rtl_fw_release_firmware(tp->rtl_fw);
2054                kfree(tp->rtl_fw);
2055                tp->rtl_fw = NULL;
2056        }
2057}
2058
2059void r8169_apply_firmware(struct rtl8169_private *tp)
2060{
2061        int val;
2062
2063        /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2064        if (tp->rtl_fw) {
2065                rtl_fw_write_firmware(tp, tp->rtl_fw);
2066                /* At least one firmware doesn't reset tp->ocp_base. */
2067                tp->ocp_base = OCP_STD_PHY_BASE;
2068
2069                /* PHY soft reset may still be in progress */
2070                phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2071                                      !(val & BMCR_RESET),
2072                                      50000, 600000, true);
2073        }
2074}
2075
2076static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2077{
2078        /* Adjust EEE LED frequency */
2079        if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2080                RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2081
2082        rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2083}
2084
2085static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2086{
2087        r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2088        r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2089}
2090
2091static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2092{
2093        RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2094}
2095
2096static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2097{
2098        rtl8125_set_eee_txidle_timer(tp);
2099        r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2100}
2101
2102static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2103{
2104        const u16 w[] = {
2105                addr[0] | (addr[1] << 8),
2106                addr[2] | (addr[3] << 8),
2107                addr[4] | (addr[5] << 8)
2108        };
2109
2110        rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2111        rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2112        rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2113        rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2114}
2115
2116u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2117{
2118        u16 data1, data2, ioffset;
2119
2120        r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2121        data1 = r8168_mac_ocp_read(tp, 0xdd02);
2122        data2 = r8168_mac_ocp_read(tp, 0xdd00);
2123
2124        ioffset = (data2 >> 1) & 0x7ff8;
2125        ioffset |= data2 & 0x0007;
2126        if (data1 & BIT(7))
2127                ioffset |= BIT(15);
2128
2129        return ioffset;
2130}
2131
2132static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2133{
2134        set_bit(flag, tp->wk.flags);
2135        schedule_work(&tp->wk.work);
2136}
2137
2138static void rtl8169_init_phy(struct rtl8169_private *tp)
2139{
2140        r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2141
2142        if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2143                pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2144                pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2145                /* set undocumented MAC Reg C+CR Offset 0x82h */
2146                RTL_W8(tp, 0x82, 0x01);
2147        }
2148
2149        if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2150            tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2151            tp->pci_dev->subsystem_device == 0xe000)
2152                phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2153
2154        /* We may have called phy_speed_down before */
2155        phy_speed_up(tp->phydev);
2156
2157        if (rtl_supports_eee(tp))
2158                rtl_enable_eee(tp);
2159
2160        genphy_soft_reset(tp->phydev);
2161}
2162
2163static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2164{
2165        rtl_unlock_config_regs(tp);
2166
2167        RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2168        rtl_pci_commit(tp);
2169
2170        RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2171        rtl_pci_commit(tp);
2172
2173        if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2174                rtl_rar_exgmac_set(tp, addr);
2175
2176        rtl_lock_config_regs(tp);
2177}
2178
2179static int rtl_set_mac_address(struct net_device *dev, void *p)
2180{
2181        struct rtl8169_private *tp = netdev_priv(dev);
2182        int ret;
2183
2184        ret = eth_mac_addr(dev, p);
2185        if (ret)
2186                return ret;
2187
2188        rtl_rar_set(tp, dev->dev_addr);
2189
2190        return 0;
2191}
2192
2193static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2194{
2195        switch (tp->mac_version) {
2196        case RTL_GIGA_MAC_VER_25:
2197        case RTL_GIGA_MAC_VER_26:
2198        case RTL_GIGA_MAC_VER_29:
2199        case RTL_GIGA_MAC_VER_30:
2200        case RTL_GIGA_MAC_VER_32:
2201        case RTL_GIGA_MAC_VER_33:
2202        case RTL_GIGA_MAC_VER_34:
2203        case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_63:
2204                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2205                        AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2206                break;
2207        default:
2208                break;
2209        }
2210}
2211
2212static void rtl_pll_power_down(struct rtl8169_private *tp)
2213{
2214        if (r8168_check_dash(tp))
2215                return;
2216
2217        if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2218            tp->mac_version == RTL_GIGA_MAC_VER_33)
2219                rtl_ephy_write(tp, 0x19, 0xff64);
2220
2221        if (device_may_wakeup(tp_to_dev(tp))) {
2222                phy_speed_down(tp->phydev, false);
2223                rtl_wol_suspend_quirk(tp);
2224                return;
2225        }
2226
2227        switch (tp->mac_version) {
2228        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2229        case RTL_GIGA_MAC_VER_37:
2230        case RTL_GIGA_MAC_VER_39:
2231        case RTL_GIGA_MAC_VER_43:
2232        case RTL_GIGA_MAC_VER_44:
2233        case RTL_GIGA_MAC_VER_45:
2234        case RTL_GIGA_MAC_VER_46:
2235        case RTL_GIGA_MAC_VER_47:
2236        case RTL_GIGA_MAC_VER_48:
2237        case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2238                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2239                break;
2240        case RTL_GIGA_MAC_VER_40:
2241        case RTL_GIGA_MAC_VER_41:
2242        case RTL_GIGA_MAC_VER_49:
2243                rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2244                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2245                break;
2246        default:
2247                break;
2248        }
2249}
2250
2251static void rtl_pll_power_up(struct rtl8169_private *tp)
2252{
2253        switch (tp->mac_version) {
2254        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2255        case RTL_GIGA_MAC_VER_37:
2256        case RTL_GIGA_MAC_VER_39:
2257        case RTL_GIGA_MAC_VER_43:
2258                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2259                break;
2260        case RTL_GIGA_MAC_VER_44:
2261        case RTL_GIGA_MAC_VER_45:
2262        case RTL_GIGA_MAC_VER_46:
2263        case RTL_GIGA_MAC_VER_47:
2264        case RTL_GIGA_MAC_VER_48:
2265        case RTL_GIGA_MAC_VER_50 ... RTL_GIGA_MAC_VER_63:
2266                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2267                break;
2268        case RTL_GIGA_MAC_VER_40:
2269        case RTL_GIGA_MAC_VER_41:
2270        case RTL_GIGA_MAC_VER_49:
2271                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2272                rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2273                break;
2274        default:
2275                break;
2276        }
2277
2278        phy_resume(tp->phydev);
2279}
2280
2281static void rtl_init_rxcfg(struct rtl8169_private *tp)
2282{
2283        switch (tp->mac_version) {
2284        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2285        case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2286                RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2287                break;
2288        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2289        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2290        case RTL_GIGA_MAC_VER_38:
2291                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2292                break;
2293        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2294                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2295                break;
2296        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2297                RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2298                break;
2299        default:
2300                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2301                break;
2302        }
2303}
2304
2305static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2306{
2307        tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2308}
2309
2310static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2311{
2312        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2313        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2314}
2315
2316static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2317{
2318        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2319        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2320}
2321
2322static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2323{
2324        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2325}
2326
2327static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2328{
2329        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2330}
2331
2332static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2333{
2334        RTL_W8(tp, MaxTxPacketSize, 0x3f);
2335        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2336        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2337}
2338
2339static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2340{
2341        RTL_W8(tp, MaxTxPacketSize, 0x0c);
2342        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2343        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2344}
2345
2346static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2347{
2348        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2349}
2350
2351static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2352{
2353        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2354}
2355
2356static void rtl_jumbo_config(struct rtl8169_private *tp)
2357{
2358        bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2359
2360        rtl_unlock_config_regs(tp);
2361        switch (tp->mac_version) {
2362        case RTL_GIGA_MAC_VER_12:
2363        case RTL_GIGA_MAC_VER_17:
2364                if (jumbo) {
2365                        pcie_set_readrq(tp->pci_dev, 512);
2366                        r8168b_1_hw_jumbo_enable(tp);
2367                } else {
2368                        r8168b_1_hw_jumbo_disable(tp);
2369                }
2370                break;
2371        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2372                if (jumbo) {
2373                        pcie_set_readrq(tp->pci_dev, 512);
2374                        r8168c_hw_jumbo_enable(tp);
2375                } else {
2376                        r8168c_hw_jumbo_disable(tp);
2377                }
2378                break;
2379        case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2380                if (jumbo)
2381                        r8168dp_hw_jumbo_enable(tp);
2382                else
2383                        r8168dp_hw_jumbo_disable(tp);
2384                break;
2385        case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2386                if (jumbo) {
2387                        pcie_set_readrq(tp->pci_dev, 512);
2388                        r8168e_hw_jumbo_enable(tp);
2389                } else {
2390                        r8168e_hw_jumbo_disable(tp);
2391                }
2392                break;
2393        default:
2394                break;
2395        }
2396        rtl_lock_config_regs(tp);
2397
2398        if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2399                pcie_set_readrq(tp->pci_dev, 4096);
2400}
2401
2402DECLARE_RTL_COND(rtl_chipcmd_cond)
2403{
2404        return RTL_R8(tp, ChipCmd) & CmdReset;
2405}
2406
2407static void rtl_hw_reset(struct rtl8169_private *tp)
2408{
2409        RTL_W8(tp, ChipCmd, CmdReset);
2410
2411        rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2412}
2413
2414static void rtl_request_firmware(struct rtl8169_private *tp)
2415{
2416        struct rtl_fw *rtl_fw;
2417
2418        /* firmware loaded already or no firmware available */
2419        if (tp->rtl_fw || !tp->fw_name)
2420                return;
2421
2422        rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2423        if (!rtl_fw)
2424                return;
2425
2426        rtl_fw->phy_write = rtl_writephy;
2427        rtl_fw->phy_read = rtl_readphy;
2428        rtl_fw->mac_mcu_write = mac_mcu_write;
2429        rtl_fw->mac_mcu_read = mac_mcu_read;
2430        rtl_fw->fw_name = tp->fw_name;
2431        rtl_fw->dev = tp_to_dev(tp);
2432
2433        if (rtl_fw_request_firmware(rtl_fw))
2434                kfree(rtl_fw);
2435        else
2436                tp->rtl_fw = rtl_fw;
2437}
2438
2439static void rtl_rx_close(struct rtl8169_private *tp)
2440{
2441        RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2442}
2443
2444DECLARE_RTL_COND(rtl_npq_cond)
2445{
2446        return RTL_R8(tp, TxPoll) & NPQ;
2447}
2448
2449DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2450{
2451        return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2452}
2453
2454DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2455{
2456        return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2457}
2458
2459DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2460{
2461        /* IntrMitigate has new functionality on RTL8125 */
2462        return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2463}
2464
2465static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2466{
2467        switch (tp->mac_version) {
2468        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2469                rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2470                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2471                break;
2472        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2473                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2474                break;
2475        case RTL_GIGA_MAC_VER_63:
2476                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2477                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2478                rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2479                break;
2480        default:
2481                break;
2482        }
2483}
2484
2485static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2486{
2487        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2488        fsleep(2000);
2489        rtl_wait_txrx_fifo_empty(tp);
2490}
2491
2492static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2493{
2494        u32 val = TX_DMA_BURST << TxDMAShift |
2495                  InterFrameGap << TxInterFrameGapShift;
2496
2497        if (rtl_is_8168evl_up(tp))
2498                val |= TXCFG_AUTO_FIFO;
2499
2500        RTL_W32(tp, TxConfig, val);
2501}
2502
2503static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2504{
2505        /* Low hurts. Let's disable the filtering. */
2506        RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2507}
2508
2509static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2510{
2511        /*
2512         * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2513         * register to be written before TxDescAddrLow to work.
2514         * Switching from MMIO to I/O access fixes the issue as well.
2515         */
2516        RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2517        RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2518        RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2519        RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2520}
2521
2522static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2523{
2524        u32 val;
2525
2526        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2527                val = 0x000fff00;
2528        else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2529                val = 0x00ffff00;
2530        else
2531                return;
2532
2533        if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2534                val |= 0xff;
2535
2536        RTL_W32(tp, 0x7c, val);
2537}
2538
2539static void rtl_set_rx_mode(struct net_device *dev)
2540{
2541        u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2542        /* Multicast hash filter */
2543        u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2544        struct rtl8169_private *tp = netdev_priv(dev);
2545        u32 tmp;
2546
2547        if (dev->flags & IFF_PROMISC) {
2548                rx_mode |= AcceptAllPhys;
2549        } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2550                   dev->flags & IFF_ALLMULTI ||
2551                   tp->mac_version == RTL_GIGA_MAC_VER_35) {
2552                /* accept all multicasts */
2553        } else if (netdev_mc_empty(dev)) {
2554                rx_mode &= ~AcceptMulticast;
2555        } else {
2556                struct netdev_hw_addr *ha;
2557
2558                mc_filter[1] = mc_filter[0] = 0;
2559                netdev_for_each_mc_addr(ha, dev) {
2560                        u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2561                        mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2562                }
2563
2564                if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2565                        tmp = mc_filter[0];
2566                        mc_filter[0] = swab32(mc_filter[1]);
2567                        mc_filter[1] = swab32(tmp);
2568                }
2569        }
2570
2571        RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2572        RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2573
2574        tmp = RTL_R32(tp, RxConfig);
2575        RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2576}
2577
2578DECLARE_RTL_COND(rtl_csiar_cond)
2579{
2580        return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2581}
2582
2583static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2584{
2585        u32 func = PCI_FUNC(tp->pci_dev->devfn);
2586
2587        RTL_W32(tp, CSIDR, value);
2588        RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2589                CSIAR_BYTE_ENABLE | func << 16);
2590
2591        rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2592}
2593
2594static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2595{
2596        u32 func = PCI_FUNC(tp->pci_dev->devfn);
2597
2598        RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2599                CSIAR_BYTE_ENABLE);
2600
2601        return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2602                RTL_R32(tp, CSIDR) : ~0;
2603}
2604
2605static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2606{
2607        struct pci_dev *pdev = tp->pci_dev;
2608        u32 csi;
2609
2610        /* According to Realtek the value at config space address 0x070f
2611         * controls the L0s/L1 entrance latency. We try standard ECAM access
2612         * first and if it fails fall back to CSI.
2613         */
2614        if (pdev->cfg_size > 0x070f &&
2615            pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2616                return;
2617
2618        netdev_notice_once(tp->dev,
2619                "No native access to PCI extended config space, falling back to CSI\n");
2620        csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2621        rtl_csi_write(tp, 0x070c, csi | val << 24);
2622}
2623
2624static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2625{
2626        rtl_csi_access_enable(tp, 0x27);
2627}
2628
2629struct ephy_info {
2630        unsigned int offset;
2631        u16 mask;
2632        u16 bits;
2633};
2634
2635static void __rtl_ephy_init(struct rtl8169_private *tp,
2636                            const struct ephy_info *e, int len)
2637{
2638        u16 w;
2639
2640        while (len-- > 0) {
2641                w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2642                rtl_ephy_write(tp, e->offset, w);
2643                e++;
2644        }
2645}
2646
2647#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2648
2649static void rtl_disable_clock_request(struct rtl8169_private *tp)
2650{
2651        pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2652                                   PCI_EXP_LNKCTL_CLKREQ_EN);
2653}
2654
2655static void rtl_enable_clock_request(struct rtl8169_private *tp)
2656{
2657        pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2658                                 PCI_EXP_LNKCTL_CLKREQ_EN);
2659}
2660
2661static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2662{
2663        /* work around an issue when PCI reset occurs during L2/L3 state */
2664        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2665}
2666
2667static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2668{
2669        /* Don't enable ASPM in the chip if OS can't control ASPM */
2670        if (enable && tp->aspm_manageable) {
2671                RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2672                RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2673        } else {
2674                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2675                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2676        }
2677
2678        udelay(10);
2679}
2680
2681static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2682                              u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2683{
2684        /* Usage of dynamic vs. static FIFO is controlled by bit
2685         * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2686         */
2687        rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2688        rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2689}
2690
2691static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2692                                          u8 low, u8 high)
2693{
2694        /* FIFO thresholds for pause flow control */
2695        rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2696        rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2697}
2698
2699static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2700{
2701        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2702}
2703
2704static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2705{
2706        RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2707
2708        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2709
2710        rtl_disable_clock_request(tp);
2711}
2712
2713static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2714{
2715        static const struct ephy_info e_info_8168cp[] = {
2716                { 0x01, 0,      0x0001 },
2717                { 0x02, 0x0800, 0x1000 },
2718                { 0x03, 0,      0x0042 },
2719                { 0x06, 0x0080, 0x0000 },
2720                { 0x07, 0,      0x2000 }
2721        };
2722
2723        rtl_set_def_aspm_entry_latency(tp);
2724
2725        rtl_ephy_init(tp, e_info_8168cp);
2726
2727        __rtl_hw_start_8168cp(tp);
2728}
2729
2730static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2731{
2732        rtl_set_def_aspm_entry_latency(tp);
2733
2734        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2735}
2736
2737static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2738{
2739        rtl_set_def_aspm_entry_latency(tp);
2740
2741        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2742
2743        /* Magic. */
2744        RTL_W8(tp, DBG_REG, 0x20);
2745}
2746
2747static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2748{
2749        static const struct ephy_info e_info_8168c_1[] = {
2750                { 0x02, 0x0800, 0x1000 },
2751                { 0x03, 0,      0x0002 },
2752                { 0x06, 0x0080, 0x0000 }
2753        };
2754
2755        rtl_set_def_aspm_entry_latency(tp);
2756
2757        RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2758
2759        rtl_ephy_init(tp, e_info_8168c_1);
2760
2761        __rtl_hw_start_8168cp(tp);
2762}
2763
2764static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2765{
2766        static const struct ephy_info e_info_8168c_2[] = {
2767                { 0x01, 0,      0x0001 },
2768                { 0x03, 0x0400, 0x0020 }
2769        };
2770
2771        rtl_set_def_aspm_entry_latency(tp);
2772
2773        rtl_ephy_init(tp, e_info_8168c_2);
2774
2775        __rtl_hw_start_8168cp(tp);
2776}
2777
2778static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2779{
2780        rtl_hw_start_8168c_2(tp);
2781}
2782
2783static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2784{
2785        rtl_set_def_aspm_entry_latency(tp);
2786
2787        __rtl_hw_start_8168cp(tp);
2788}
2789
2790static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2791{
2792        rtl_set_def_aspm_entry_latency(tp);
2793
2794        rtl_disable_clock_request(tp);
2795}
2796
2797static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2798{
2799        static const struct ephy_info e_info_8168d_4[] = {
2800                { 0x0b, 0x0000, 0x0048 },
2801                { 0x19, 0x0020, 0x0050 },
2802                { 0x0c, 0x0100, 0x0020 },
2803                { 0x10, 0x0004, 0x0000 },
2804        };
2805
2806        rtl_set_def_aspm_entry_latency(tp);
2807
2808        rtl_ephy_init(tp, e_info_8168d_4);
2809
2810        rtl_enable_clock_request(tp);
2811}
2812
2813static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2814{
2815        static const struct ephy_info e_info_8168e_1[] = {
2816                { 0x00, 0x0200, 0x0100 },
2817                { 0x00, 0x0000, 0x0004 },
2818                { 0x06, 0x0002, 0x0001 },
2819                { 0x06, 0x0000, 0x0030 },
2820                { 0x07, 0x0000, 0x2000 },
2821                { 0x00, 0x0000, 0x0020 },
2822                { 0x03, 0x5800, 0x2000 },
2823                { 0x03, 0x0000, 0x0001 },
2824                { 0x01, 0x0800, 0x1000 },
2825                { 0x07, 0x0000, 0x4000 },
2826                { 0x1e, 0x0000, 0x2000 },
2827                { 0x19, 0xffff, 0xfe6c },
2828                { 0x0a, 0x0000, 0x0040 }
2829        };
2830
2831        rtl_set_def_aspm_entry_latency(tp);
2832
2833        rtl_ephy_init(tp, e_info_8168e_1);
2834
2835        rtl_disable_clock_request(tp);
2836
2837        /* Reset tx FIFO pointer */
2838        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2839        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2840
2841        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2842}
2843
2844static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2845{
2846        static const struct ephy_info e_info_8168e_2[] = {
2847                { 0x09, 0x0000, 0x0080 },
2848                { 0x19, 0x0000, 0x0224 },
2849                { 0x00, 0x0000, 0x0004 },
2850                { 0x0c, 0x3df0, 0x0200 },
2851        };
2852
2853        rtl_set_def_aspm_entry_latency(tp);
2854
2855        rtl_ephy_init(tp, e_info_8168e_2);
2856
2857        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2858        rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2859        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2860        rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2861        rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2862        rtl_reset_packet_filter(tp);
2863        rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2864        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2865        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2866
2867        rtl_disable_clock_request(tp);
2868
2869        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2870
2871        rtl8168_config_eee_mac(tp);
2872
2873        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2874        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2875        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2876
2877        rtl_hw_aspm_clkreq_enable(tp, true);
2878}
2879
2880static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2881{
2882        rtl_set_def_aspm_entry_latency(tp);
2883
2884        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2885        rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2886        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2887        rtl_reset_packet_filter(tp);
2888        rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2889        rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2890        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2891        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2892
2893        rtl_disable_clock_request(tp);
2894
2895        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2896        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2897        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2898        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2899
2900        rtl8168_config_eee_mac(tp);
2901}
2902
2903static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2904{
2905        static const struct ephy_info e_info_8168f_1[] = {
2906                { 0x06, 0x00c0, 0x0020 },
2907                { 0x08, 0x0001, 0x0002 },
2908                { 0x09, 0x0000, 0x0080 },
2909                { 0x19, 0x0000, 0x0224 },
2910                { 0x00, 0x0000, 0x0008 },
2911                { 0x0c, 0x3df0, 0x0200 },
2912        };
2913
2914        rtl_hw_start_8168f(tp);
2915
2916        rtl_ephy_init(tp, e_info_8168f_1);
2917
2918        rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2919}
2920
2921static void rtl_hw_start_8411(struct rtl8169_private *tp)
2922{
2923        static const struct ephy_info e_info_8168f_1[] = {
2924                { 0x06, 0x00c0, 0x0020 },
2925                { 0x0f, 0xffff, 0x5200 },
2926                { 0x19, 0x0000, 0x0224 },
2927                { 0x00, 0x0000, 0x0008 },
2928                { 0x0c, 0x3df0, 0x0200 },
2929        };
2930
2931        rtl_hw_start_8168f(tp);
2932        rtl_pcie_state_l2l3_disable(tp);
2933
2934        rtl_ephy_init(tp, e_info_8168f_1);
2935
2936        rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2937}
2938
2939static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2940{
2941        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2942        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2943
2944        rtl_set_def_aspm_entry_latency(tp);
2945
2946        rtl_reset_packet_filter(tp);
2947        rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2948
2949        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2950
2951        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2952        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2953        rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2954
2955        rtl8168_config_eee_mac(tp);
2956
2957        rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2958        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2959
2960        rtl_pcie_state_l2l3_disable(tp);
2961}
2962
2963static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2964{
2965        static const struct ephy_info e_info_8168g_1[] = {
2966                { 0x00, 0x0008, 0x0000 },
2967                { 0x0c, 0x3ff0, 0x0820 },
2968                { 0x1e, 0x0000, 0x0001 },
2969                { 0x19, 0x8000, 0x0000 }
2970        };
2971
2972        rtl_hw_start_8168g(tp);
2973
2974        /* disable aspm and clock request before access ephy */
2975        rtl_hw_aspm_clkreq_enable(tp, false);
2976        rtl_ephy_init(tp, e_info_8168g_1);
2977        rtl_hw_aspm_clkreq_enable(tp, true);
2978}
2979
2980static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
2981{
2982        static const struct ephy_info e_info_8168g_2[] = {
2983                { 0x00, 0x0008, 0x0000 },
2984                { 0x0c, 0x3ff0, 0x0820 },
2985                { 0x19, 0xffff, 0x7c00 },
2986                { 0x1e, 0xffff, 0x20eb },
2987                { 0x0d, 0xffff, 0x1666 },
2988                { 0x00, 0xffff, 0x10a3 },
2989                { 0x06, 0xffff, 0xf050 },
2990                { 0x04, 0x0000, 0x0010 },
2991                { 0x1d, 0x4000, 0x0000 },
2992        };
2993
2994        rtl_hw_start_8168g(tp);
2995
2996        /* disable aspm and clock request before access ephy */
2997        rtl_hw_aspm_clkreq_enable(tp, false);
2998        rtl_ephy_init(tp, e_info_8168g_2);
2999}
3000

3001static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3002{
3003        static const struct ephy_info e_info_8411_2[] = {
3004                { 0x00, 0x0008, 0x0000 },
3005                { 0x0c, 0x37d0, 0x0820 },
3006                { 0x1e, 0x0000, 0x0001 },
3007                { 0x19, 0x8021, 0x0000 },
3008                { 0x1e, 0x0000, 0x2000 },
3009                { 0x0d, 0x0100, 0x0200 },
3010                { 0x00, 0x0000, 0x0080 },
3011                { 0x06, 0x0000, 0x0010 },
3012                { 0x04, 0x0000, 0x0010 },
3013                { 0x1d, 0x0000, 0x4000 },
3014        };
3015
3016        rtl_hw_start_8168g(tp);
3017
3018        /* disable aspm and clock request before access ephy */
3019        rtl_hw_aspm_clkreq_enable(tp, false);
3020        rtl_ephy_init(tp, e_info_8411_2);
3021
3022        /* The following Realtek-provided magic fixes an issue with the RX unit
3023         * getting confused after the PHY having been powered-down.
3024         */
3025        r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3026        r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3027        r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3028        r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3029        r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3030        r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3031        r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3032        r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3033        mdelay(3);
3034        r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3035
3036        r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3037        r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3038        r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3039        r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3040        r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3041        r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3042        r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3043        r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3044        r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3045        r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3046        r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3047        r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3048        r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3049        r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3050        r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3051        r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3052        r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3053        r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3054        r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3055        r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3056        r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3057        r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3058        r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3059        r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3060        r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3061        r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3062        r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3063        r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3064        r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3065        r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3066        r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3067        r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3068        r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3069        r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3070        r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3071        r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3072        r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3073        r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3074        r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3075        r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3076        r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3077        r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3078        r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3079        r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3080        r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3081        r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3082        r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3083        r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3084        r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3085        r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3086        r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3087        r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3088        r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3089        r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3090        r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3091        r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3092        r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3093        r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3094        r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3095        r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3096        r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3097        r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3098        r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3099        r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3100        r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3101        r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3102        r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3103        r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3104        r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3105        r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3106        r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3107        r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3108        r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3109        r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3110        r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3111        r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3112        r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3113        r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3114        r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3115        r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3116        r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3117        r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3118        r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3119        r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3120        r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3121        r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3122        r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3123        r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3124        r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3125        r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3126        r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3127        r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3128        r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3129        r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3130        r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3131        r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3132        r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3133        r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3134        r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3135        r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3136        r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3137        r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3138        r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3139        r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3140        r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3141        r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3142        r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3143        r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3144        r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3145        r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3146        r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3147
3148        r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3149
3150        r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3151        r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3152        r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3153        r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3154        r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3155        r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3156        r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3157
3158        rtl_hw_aspm_clkreq_enable(tp, true);
3159}
3160
3161static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3162{
3163        static const struct ephy_info e_info_8168h_1[] = {
3164                { 0x1e, 0x0800, 0x0001 },
3165                { 0x1d, 0x0000, 0x0800 },
3166                { 0x05, 0xffff, 0x2089 },
3167                { 0x06, 0xffff, 0x5881 },
3168                { 0x04, 0xffff, 0x854a },
3169                { 0x01, 0xffff, 0x068b }
3170        };
3171        int rg_saw_cnt;
3172
3173        /* disable aspm and clock request before access ephy */
3174        rtl_hw_aspm_clkreq_enable(tp, false);
3175        rtl_ephy_init(tp, e_info_8168h_1);
3176
3177        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3178        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3179
3180        rtl_set_def_aspm_entry_latency(tp);
3181
3182        rtl_reset_packet_filter(tp);
3183
3184        rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3185        rtl_eri_set_bits(tp, 0xdc, 0x001c);
3186
3187        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3188
3189        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3190
3191        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3192        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3193
3194        rtl8168_config_eee_mac(tp);
3195
3196        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3197        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3198
3199        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3200
3201        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3202
3203        rtl_pcie_state_l2l3_disable(tp);
3204
3205        rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3206        if (rg_saw_cnt > 0) {
3207                u16 sw_cnt_1ms_ini;
3208
3209                sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3210                sw_cnt_1ms_ini &= 0x0fff;
3211                r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3212        }
3213
3214        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3215        r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3216        r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3217        r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3218
3219        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3220        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3221        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3222        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3223
3224        rtl_hw_aspm_clkreq_enable(tp, true);
3225}
3226
3227static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3228{
3229        rtl8168ep_stop_cmac(tp);
3230
3231        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3232        rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3233
3234        rtl_set_def_aspm_entry_latency(tp);
3235
3236        rtl_reset_packet_filter(tp);
3237
3238        rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3239
3240        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3241
3242        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3243
3244        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3245        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3246
3247        rtl8168_config_eee_mac(tp);
3248
3249        rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3250
3251        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3252
3253        rtl_pcie_state_l2l3_disable(tp);
3254}
3255
3256static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3257{
3258        static const struct ephy_info e_info_8168ep_1[] = {
3259                { 0x00, 0xffff, 0x10ab },
3260                { 0x06, 0xffff, 0xf030 },
3261                { 0x08, 0xffff, 0x2006 },
3262                { 0x0d, 0xffff, 0x1666 },
3263                { 0x0c, 0x3ff0, 0x0000 }
3264        };
3265
3266        /* disable aspm and clock request before access ephy */
3267        rtl_hw_aspm_clkreq_enable(tp, false);
3268        rtl_ephy_init(tp, e_info_8168ep_1);
3269
3270        rtl_hw_start_8168ep(tp);
3271
3272        rtl_hw_aspm_clkreq_enable(tp, true);
3273}
3274
3275static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3276{
3277        static const struct ephy_info e_info_8168ep_2[] = {
3278                { 0x00, 0xffff, 0x10a3 },
3279                { 0x19, 0xffff, 0xfc00 },
3280                { 0x1e, 0xffff, 0x20ea }
3281        };
3282
3283        /* disable aspm and clock request before access ephy */
3284        rtl_hw_aspm_clkreq_enable(tp, false);
3285        rtl_ephy_init(tp, e_info_8168ep_2);
3286
3287        rtl_hw_start_8168ep(tp);
3288
3289        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3290        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3291
3292        rtl_hw_aspm_clkreq_enable(tp, true);
3293}
3294
3295static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3296{
3297        static const struct ephy_info e_info_8168ep_3[] = {
3298                { 0x00, 0x0000, 0x0080 },
3299                { 0x0d, 0x0100, 0x0200 },
3300                { 0x19, 0x8021, 0x0000 },
3301                { 0x1e, 0x0000, 0x2000 },
3302        };
3303
3304        /* disable aspm and clock request before access ephy */
3305        rtl_hw_aspm_clkreq_enable(tp, false);
3306        rtl_ephy_init(tp, e_info_8168ep_3);
3307
3308        rtl_hw_start_8168ep(tp);
3309
3310        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3311        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3312
3313        r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3314        r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3315        r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3316
3317        rtl_hw_aspm_clkreq_enable(tp, true);
3318}
3319
3320static void rtl_hw_start_8117(struct rtl8169_private *tp)
3321{
3322        static const struct ephy_info e_info_8117[] = {
3323                { 0x19, 0x0040, 0x1100 },
3324                { 0x59, 0x0040, 0x1100 },
3325        };
3326        int rg_saw_cnt;
3327
3328        rtl8168ep_stop_cmac(tp);
3329
3330        /* disable aspm and clock request before access ephy */
3331        rtl_hw_aspm_clkreq_enable(tp, false);
3332        rtl_ephy_init(tp, e_info_8117);
3333
3334        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3335        rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3336
3337        rtl_set_def_aspm_entry_latency(tp);
3338
3339        rtl_reset_packet_filter(tp);
3340
3341        rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3342
3343        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3344
3345        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3346
3347        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3348        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3349
3350        rtl8168_config_eee_mac(tp);
3351
3352        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3353        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3354
3355        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3356
3357        rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3358
3359        rtl_pcie_state_l2l3_disable(tp);
3360
3361        rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3362        if (rg_saw_cnt > 0) {
3363                u16 sw_cnt_1ms_ini;
3364
3365                sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3366                r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3367        }
3368
3369        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3370        r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3371        r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3372        r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3373
3374        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3375        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3376        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3377        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3378
3379        /* firmware is for MAC only */
3380        r8169_apply_firmware(tp);
3381
3382        rtl_hw_aspm_clkreq_enable(tp, true);
3383}
3384
3385static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3386{
3387        static const struct ephy_info e_info_8102e_1[] = {
3388                { 0x01, 0, 0x6e65 },
3389                { 0x02, 0, 0x091f },
3390                { 0x03, 0, 0xc2f9 },
3391                { 0x06, 0, 0xafb5 },
3392                { 0x07, 0, 0x0e00 },
3393                { 0x19, 0, 0xec80 },
3394                { 0x01, 0, 0x2e65 },
3395                { 0x01, 0, 0x6e65 }
3396        };
3397        u8 cfg1;
3398
3399        rtl_set_def_aspm_entry_latency(tp);
3400
3401        RTL_W8(tp, DBG_REG, FIX_NAK_1);
3402
3403        RTL_W8(tp, Config1,
3404               LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3405        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3406
3407        cfg1 = RTL_R8(tp, Config1);
3408        if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3409                RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3410
3411        rtl_ephy_init(tp, e_info_8102e_1);
3412}
3413
3414static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3415{
3416        rtl_set_def_aspm_entry_latency(tp);
3417
3418        RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3419        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3420}
3421
3422static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3423{
3424        rtl_hw_start_8102e_2(tp);
3425
3426        rtl_ephy_write(tp, 0x03, 0xc2f9);
3427}
3428
3429static void rtl_hw_start_8401(struct rtl8169_private *tp)
3430{
3431        static const struct ephy_info e_info_8401[] = {
3432                { 0x01, 0xffff, 0x6fe5 },
3433                { 0x03, 0xffff, 0x0599 },
3434                { 0x06, 0xffff, 0xaf25 },
3435                { 0x07, 0xffff, 0x8e68 },
3436        };
3437
3438        rtl_ephy_init(tp, e_info_8401);
3439        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3440}
3441
3442static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3443{
3444        static const struct ephy_info e_info_8105e_1[] = {
3445                { 0x07, 0, 0x4000 },
3446                { 0x19, 0, 0x0200 },
3447                { 0x19, 0, 0x0020 },
3448                { 0x1e, 0, 0x2000 },
3449                { 0x03, 0, 0x0001 },
3450                { 0x19, 0, 0x0100 },
3451                { 0x19, 0, 0x0004 },
3452                { 0x0a, 0, 0x0020 }
3453        };
3454
3455        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3456        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3457
3458        /* Disable Early Tally Counter */
3459        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3460
3461        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3462        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3463
3464        rtl_ephy_init(tp, e_info_8105e_1);
3465
3466        rtl_pcie_state_l2l3_disable(tp);
3467}
3468
3469static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3470{
3471        rtl_hw_start_8105e_1(tp);
3472        rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3473}
3474
3475static void rtl_hw_start_8402(struct rtl8169_private *tp)
3476{
3477        static const struct ephy_info e_info_8402[] = {
3478                { 0x19, 0xffff, 0xff64 },
3479                { 0x1e, 0, 0x4000 }
3480        };
3481
3482        rtl_set_def_aspm_entry_latency(tp);
3483
3484        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3485        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3486
3487        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3488
3489        rtl_ephy_init(tp, e_info_8402);
3490
3491        rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3492        rtl_reset_packet_filter(tp);
3493        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3494        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3495        rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3496
3497        /* disable EEE */
3498        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3499
3500        rtl_pcie_state_l2l3_disable(tp);
3501}
3502
3503static void rtl_hw_start_8106(struct rtl8169_private *tp)
3504{
3505        rtl_hw_aspm_clkreq_enable(tp, false);
3506
3507        /* Force LAN exit from ASPM if Rx/Tx are not idle */
3508        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3509
3510        RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3511        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3512        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3513
3514        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3515
3516        /* disable EEE */
3517        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3518
3519        rtl_pcie_state_l2l3_disable(tp);
3520        rtl_hw_aspm_clkreq_enable(tp, true);
3521}
3522
3523DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3524{
3525        return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3526}
3527
3528static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3529{
3530        rtl_pcie_state_l2l3_disable(tp);
3531
3532        RTL_W16(tp, 0x382, 0x221b);
3533        RTL_W8(tp, 0x4500, 0);
3534        RTL_W16(tp, 0x4800, 0);
3535
3536        /* disable UPS */
3537        r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3538
3539        RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3540
3541        r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3542        r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3543
3544        r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3545        r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3546        r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3547
3548        /* disable new tx descriptor format */
3549        r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3550
3551        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3552                r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3553        else
3554                r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3555
3556        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3557                r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3558        else
3559                r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3560
3561        r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3562        r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3563        r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3564        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3565        r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3566        r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3567        r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3568        r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3569        r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3570        r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3571
3572        r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3573        r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3574        udelay(1);
3575        r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3576        RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3577
3578        r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3579
3580        rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3581
3582        if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3583                rtl8125b_config_eee_mac(tp);
3584        else
3585                rtl8125a_config_eee_mac(tp);
3586
3587        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3588        udelay(10);
3589}
3590
3591static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3592{
3593        static const struct ephy_info e_info_8125a_1[] = {
3594                { 0x01, 0xffff, 0xa812 },
3595                { 0x09, 0xffff, 0x520c },
3596                { 0x04, 0xffff, 0xd000 },
3597                { 0x0d, 0xffff, 0xf702 },
3598                { 0x0a, 0xffff, 0x8653 },
3599                { 0x06, 0xffff, 0x001e },
3600                { 0x08, 0xffff, 0x3595 },
3601                { 0x20, 0xffff, 0x9455 },
3602                { 0x21, 0xffff, 0x99ff },
3603                { 0x02, 0xffff, 0x6046 },
3604                { 0x29, 0xffff, 0xfe00 },
3605                { 0x23, 0xffff, 0xab62 },
3606
3607                { 0x41, 0xffff, 0xa80c },
3608                { 0x49, 0xffff, 0x520c },
3609                { 0x44, 0xffff, 0xd000 },
3610                { 0x4d, 0xffff, 0xf702 },
3611                { 0x4a, 0xffff, 0x8653 },
3612                { 0x46, 0xffff, 0x001e },
3613                { 0x48, 0xffff, 0x3595 },
3614                { 0x60, 0xffff, 0x9455 },
3615                { 0x61, 0xffff, 0x99ff },
3616                { 0x42, 0xffff, 0x6046 },
3617                { 0x69, 0xffff, 0xfe00 },
3618                { 0x63, 0xffff, 0xab62 },
3619        };
3620
3621        rtl_set_def_aspm_entry_latency(tp);
3622
3623        /* disable aspm and clock request before access ephy */
3624        rtl_hw_aspm_clkreq_enable(tp, false);
3625        rtl_ephy_init(tp, e_info_8125a_1);
3626
3627        rtl_hw_start_8125_common(tp);
3628        rtl_hw_aspm_clkreq_enable(tp, true);
3629}
3630
3631static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3632{
3633        static const struct ephy_info e_info_8125a_2[] = {
3634                { 0x04, 0xffff, 0xd000 },
3635                { 0x0a, 0xffff, 0x8653 },
3636                { 0x23, 0xffff, 0xab66 },
3637                { 0x20, 0xffff, 0x9455 },
3638                { 0x21, 0xffff, 0x99ff },
3639                { 0x29, 0xffff, 0xfe04 },
3640
3641                { 0x44, 0xffff, 0xd000 },
3642                { 0x4a, 0xffff, 0x8653 },
3643                { 0x63, 0xffff, 0xab66 },
3644                { 0x60, 0xffff, 0x9455 },
3645                { 0x61, 0xffff, 0x99ff },
3646                { 0x69, 0xffff, 0xfe04 },
3647        };
3648
3649        rtl_set_def_aspm_entry_latency(tp);
3650
3651        /* disable aspm and clock request before access ephy */
3652        rtl_hw_aspm_clkreq_enable(tp, false);
3653        rtl_ephy_init(tp, e_info_8125a_2);
3654
3655        rtl_hw_start_8125_common(tp);
3656        rtl_hw_aspm_clkreq_enable(tp, true);
3657}
3658
3659static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3660{
3661        static const struct ephy_info e_info_8125b[] = {
3662                { 0x0b, 0xffff, 0xa908 },
3663                { 0x1e, 0xffff, 0x20eb },
3664                { 0x4b, 0xffff, 0xa908 },
3665                { 0x5e, 0xffff, 0x20eb },
3666                { 0x22, 0x0030, 0x0020 },
3667                { 0x62, 0x0030, 0x0020 },
3668        };
3669
3670        rtl_set_def_aspm_entry_latency(tp);
3671        rtl_hw_aspm_clkreq_enable(tp, false);
3672
3673        rtl_ephy_init(tp, e_info_8125b);
3674        rtl_hw_start_8125_common(tp);
3675
3676        rtl_hw_aspm_clkreq_enable(tp, true);
3677}
3678
3679static void rtl_hw_config(struct rtl8169_private *tp)
3680{
3681        static const rtl_generic_fct hw_configs[] = {
3682                [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3683                [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3684                [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3685                [RTL_GIGA_MAC_VER_10] = NULL,
3686                [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3687                [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3688                [RTL_GIGA_MAC_VER_13] = NULL,
3689                [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3690                [RTL_GIGA_MAC_VER_16] = NULL,
3691                [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3692                [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3693                [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3694                [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3695                [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3696                [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3697                [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3698                [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3699                [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3700                [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3701                [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3702                [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3703                [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3704                [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3705                [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3706                [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3707                [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3708                [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3709                [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3710                [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3711                [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3712                [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3713                [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3714                [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3715                [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3716                [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3717                [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3718                [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3719                [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3720                [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3721                [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3722                [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3723                [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3724                [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3725                [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3726                [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3727                [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3728                [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3729                [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3730        };
3731
3732        if (hw_configs[tp->mac_version])
3733                hw_configs[tp->mac_version](tp);
3734}
3735
3736static void rtl_hw_start_8125(struct rtl8169_private *tp)
3737{
3738        int i;
3739
3740        /* disable interrupt coalescing */
3741        for (i = 0xa00; i < 0xb00; i += 4)
3742                RTL_W32(tp, i, 0);
3743
3744        rtl_hw_config(tp);
3745}
3746
3747static void rtl_hw_start_8168(struct rtl8169_private *tp)
3748{
3749        if (rtl_is_8168evl_up(tp))
3750                RTL_W8(tp, MaxTxPacketSize, EarlySize);
3751        else
3752                RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3753
3754        rtl_hw_config(tp);
3755
3756        /* disable interrupt coalescing */
3757        RTL_W16(tp, IntrMitigate, 0x0000);
3758}
3759
3760static void rtl_hw_start_8169(struct rtl8169_private *tp)
3761{
3762        RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3763
3764        tp->cp_cmd |= PCIMulRW;
3765
3766        if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3767            tp->mac_version == RTL_GIGA_MAC_VER_03)
3768                tp->cp_cmd |= EnAnaPLL;
3769
3770        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3771
3772        rtl8169_set_magic_reg(tp);
3773
3774        /* disable interrupt coalescing */
3775        RTL_W16(tp, IntrMitigate, 0x0000);
3776}
3777
3778static void rtl_hw_start(struct  rtl8169_private *tp)
3779{
3780        rtl_unlock_config_regs(tp);
3781
3782        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3783
3784        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3785                rtl_hw_start_8169(tp);
3786        else if (rtl_is_8125(tp))
3787                rtl_hw_start_8125(tp);
3788        else
3789                rtl_hw_start_8168(tp);
3790
3791        rtl_set_rx_max_size(tp);
3792        rtl_set_rx_tx_desc_registers(tp);
3793        rtl_lock_config_regs(tp);
3794
3795        rtl_jumbo_config(tp);
3796
3797        /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3798        rtl_pci_commit(tp);
3799
3800        RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3801        rtl_init_rxcfg(tp);
3802        rtl_set_tx_config_registers(tp);
3803        rtl_set_rx_config_features(tp, tp->dev->features);
3804        rtl_set_rx_mode(tp->dev);
3805        rtl_irq_enable(tp);
3806}
3807
3808static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3809{
3810        struct rtl8169_private *tp = netdev_priv(dev);
3811
3812        dev->mtu = new_mtu;
3813        netdev_update_features(dev);
3814        rtl_jumbo_config(tp);
3815
3816        switch (tp->mac_version) {
3817        case RTL_GIGA_MAC_VER_61:
3818        case RTL_GIGA_MAC_VER_63:
3819                rtl8125_set_eee_txidle_timer(tp);
3820                break;
3821        default:
3822                break;
3823        }
3824
3825        return 0;
3826}
3827
3828static void rtl8169_mark_to_asic(struct RxDesc *desc)
3829{
3830        u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3831
3832        desc->opts2 = 0;
3833        /* Force memory writes to complete before releasing descriptor */
3834        dma_wmb();
3835        WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3836}
3837
3838static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3839                                          struct RxDesc *desc)
3840{
3841        struct device *d = tp_to_dev(tp);
3842        int node = dev_to_node(d);
3843        dma_addr_t mapping;
3844        struct page *data;
3845
3846        data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3847        if (!data)
3848                return NULL;
3849
3850        mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3851        if (unlikely(dma_mapping_error(d, mapping))) {
3852                netdev_err(tp->dev, "Failed to map RX DMA!\n");
3853                __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3854                return NULL;
3855        }
3856
3857        desc->addr = cpu_to_le64(mapping);
3858        rtl8169_mark_to_asic(desc);
3859
3860        return data;
3861}
3862
3863static void rtl8169_rx_clear(struct rtl8169_private *tp)
3864{
3865        unsigned int i;
3866
3867        for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3868                dma_unmap_page(tp_to_dev(tp),
3869                               le64_to_cpu(tp->RxDescArray[i].addr),
3870                               R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3871                __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3872                tp->Rx_databuff[i] = NULL;
3873                tp->RxDescArray[i].addr = 0;
3874                tp->RxDescArray[i].opts1 = 0;
3875        }
3876}
3877
3878static int rtl8169_rx_fill(struct rtl8169_private *tp)
3879{
3880        unsigned int i;
3881
3882        for (i = 0; i < NUM_RX_DESC; i++) {
3883                struct page *data;
3884
3885                data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3886                if (!data) {
3887                        rtl8169_rx_clear(tp);
3888                        return -ENOMEM;
3889                }
3890                tp->Rx_databuff[i] = data;
3891        }
3892
3893        /* mark as last descriptor in the ring */
3894        tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3895
3896        return 0;
3897}
3898
3899static int rtl8169_init_ring(struct rtl8169_private *tp)
3900{
3901        rtl8169_init_ring_indexes(tp);
3902
3903        memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3904        memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3905
3906        return rtl8169_rx_fill(tp);
3907}
3908
3909static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3910{
3911        struct ring_info *tx_skb = tp->tx_skb + entry;
3912        struct TxDesc *desc = tp->TxDescArray + entry;
3913
3914        dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3915                         DMA_TO_DEVICE);
3916        memset(desc, 0, sizeof(*desc));
3917        memset(tx_skb, 0, sizeof(*tx_skb));
3918}
3919
3920static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3921                                   unsigned int n)
3922{
3923        unsigned int i;
3924
3925        for (i = 0; i < n; i++) {
3926                unsigned int entry = (start + i) % NUM_TX_DESC;
3927                struct ring_info *tx_skb = tp->tx_skb + entry;
3928                unsigned int len = tx_skb->len;
3929
3930                if (len) {
3931                        struct sk_buff *skb = tx_skb->skb;
3932
3933                        rtl8169_unmap_tx_skb(tp, entry);
3934                        if (skb)
3935                                dev_consume_skb_any(skb);
3936                }
3937        }
3938}
3939
3940static void rtl8169_tx_clear(struct rtl8169_private *tp)
3941{
3942        rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3943        netdev_reset_queue(tp->dev);
3944}
3945
3946static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3947{
3948        napi_disable(&tp->napi);
3949
3950        /* Give a racing hard_start_xmit a few cycles to complete. */
3951        synchronize_net();
3952
3953        /* Disable interrupts */
3954        rtl8169_irq_mask_and_ack(tp);
3955
3956        rtl_rx_close(tp);
3957
3958        if (going_down && tp->dev->wol_enabled)
3959                goto no_reset;
3960
3961        switch (tp->mac_version) {
3962        case RTL_GIGA_MAC_VER_27:
3963        case RTL_GIGA_MAC_VER_28:
3964        case RTL_GIGA_MAC_VER_31:
3965                rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3966                break;
3967        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3968                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3969                rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3970                break;
3971        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3972                rtl_enable_rxdvgate(tp);
3973                fsleep(2000);
3974                break;
3975        default:
3976                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3977                fsleep(100);
3978                break;
3979        }
3980
3981        rtl_hw_reset(tp);
3982no_reset:
3983        rtl8169_tx_clear(tp);
3984        rtl8169_init_ring_indexes(tp);
3985}
3986
3987static void rtl_reset_work(struct rtl8169_private *tp)
3988{
3989        int i;
3990
3991        netif_stop_queue(tp->dev);
3992
3993        rtl8169_cleanup(tp, false);
3994
3995        for (i = 0; i < NUM_RX_DESC; i++)
3996                rtl8169_mark_to_asic(tp->RxDescArray + i);
3997
3998        napi_enable(&tp->napi);
3999        rtl_hw_start(tp);
4000}

4001
4002static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4003{
4004        struct rtl8169_private *tp = netdev_priv(dev);
4005
4006        rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4007}
4008
4009static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4010                          void *addr, unsigned int entry, bool desc_own)
4011{
4012        struct TxDesc *txd = tp->TxDescArray + entry;
4013        struct device *d = tp_to_dev(tp);
4014        dma_addr_t mapping;
4015        u32 opts1;
4016        int ret;
4017
4018        mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4019        ret = dma_mapping_error(d, mapping);
4020        if (unlikely(ret)) {
4021                if (net_ratelimit())
4022                        netdev_err(tp->dev, "Failed to map TX data!\n");
4023                return ret;
4024        }
4025
4026        txd->addr = cpu_to_le64(mapping);
4027        txd->opts2 = cpu_to_le32(opts[1]);
4028
4029        opts1 = opts[0] | len;
4030        if (entry == NUM_TX_DESC - 1)
4031                opts1 |= RingEnd;
4032        if (desc_own)
4033                opts1 |= DescOwn;
4034        txd->opts1 = cpu_to_le32(opts1);
4035
4036        tp->tx_skb[entry].len = len;
4037
4038        return 0;
4039}
4040
4041static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4042                              const u32 *opts, unsigned int entry)
4043{
4044        struct skb_shared_info *info = skb_shinfo(skb);
4045        unsigned int cur_frag;
4046
4047        for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4048                const skb_frag_t *frag = info->frags + cur_frag;
4049                void *addr = skb_frag_address(frag);
4050                u32 len = skb_frag_size(frag);
4051
4052                entry = (entry + 1) % NUM_TX_DESC;
4053
4054                if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4055                        goto err_out;
4056        }
4057
4058        return 0;
4059
4060err_out:
4061        rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4062        return -EIO;
4063}
4064
4065static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4066{
4067        return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4068}
4069
4070static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4071{
4072        u32 mss = skb_shinfo(skb)->gso_size;
4073
4074        if (mss) {
4075                opts[0] |= TD_LSO;
4076                opts[0] |= mss << TD0_MSS_SHIFT;
4077        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4078                const struct iphdr *ip = ip_hdr(skb);
4079
4080                if (ip->protocol == IPPROTO_TCP)
4081                        opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4082                else if (ip->protocol == IPPROTO_UDP)
4083                        opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4084                else
4085                        WARN_ON_ONCE(1);
4086        }
4087}
4088
4089static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4090                                struct sk_buff *skb, u32 *opts)
4091{
4092        u32 transport_offset = (u32)skb_transport_offset(skb);
4093        struct skb_shared_info *shinfo = skb_shinfo(skb);
4094        u32 mss = shinfo->gso_size;
4095
4096        if (mss) {
4097                if (shinfo->gso_type & SKB_GSO_TCPV4) {
4098                        opts[0] |= TD1_GTSENV4;
4099                } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4100                        if (skb_cow_head(skb, 0))
4101                                return false;
4102
4103                        tcp_v6_gso_csum_prep(skb);
4104                        opts[0] |= TD1_GTSENV6;
4105                } else {
4106                        WARN_ON_ONCE(1);
4107                }
4108
4109                opts[0] |= transport_offset << GTTCPHO_SHIFT;
4110                opts[1] |= mss << TD1_MSS_SHIFT;
4111        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4112                u8 ip_protocol;
4113
4114                switch (vlan_get_protocol(skb)) {
4115                case htons(ETH_P_IP):
4116                        opts[1] |= TD1_IPv4_CS;
4117                        ip_protocol = ip_hdr(skb)->protocol;
4118                        break;
4119
4120                case htons(ETH_P_IPV6):
4121                        opts[1] |= TD1_IPv6_CS;
4122                        ip_protocol = ipv6_hdr(skb)->nexthdr;
4123                        break;
4124
4125                default:
4126                        ip_protocol = IPPROTO_RAW;
4127                        break;
4128                }
4129
4130                if (ip_protocol == IPPROTO_TCP)
4131                        opts[1] |= TD1_TCP_CS;
4132                else if (ip_protocol == IPPROTO_UDP)
4133                        opts[1] |= TD1_UDP_CS;
4134                else
4135                        WARN_ON_ONCE(1);
4136
4137                opts[1] |= transport_offset << TCPHO_SHIFT;
4138        } else {
4139                if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4140                        return !eth_skb_pad(skb);
4141        }
4142
4143        return true;
4144}
4145
4146static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4147                               unsigned int nr_frags)
4148{
4149        unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4150
4151        /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4152        return slots_avail > nr_frags;
4153}
4154
4155/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4156static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4157{
4158        switch (tp->mac_version) {
4159        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4160        case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4161                return false;
4162        default:
4163                return true;
4164        }
4165}
4166
4167static void rtl8169_doorbell(struct rtl8169_private *tp)
4168{
4169        if (rtl_is_8125(tp))
4170                RTL_W16(tp, TxPoll_8125, BIT(0));
4171        else
4172                RTL_W8(tp, TxPoll, NPQ);
4173}
4174
4175static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4176                                      struct net_device *dev)
4177{
4178        unsigned int frags = skb_shinfo(skb)->nr_frags;
4179        struct rtl8169_private *tp = netdev_priv(dev);
4180        unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4181        struct TxDesc *txd_first, *txd_last;
4182        bool stop_queue, door_bell;
4183        u32 opts[2];
4184
4185        txd_first = tp->TxDescArray + entry;
4186
4187        if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4188                if (net_ratelimit())
4189                        netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4190                goto err_stop_0;
4191        }
4192
4193        if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn))
4194                goto err_stop_0;
4195
4196        opts[1] = rtl8169_tx_vlan_tag(skb);
4197        opts[0] = 0;
4198
4199        if (!rtl_chip_supports_csum_v2(tp))
4200                rtl8169_tso_csum_v1(skb, opts);
4201        else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4202                goto err_dma_0;
4203
4204        if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4205                                    entry, false)))
4206                goto err_dma_0;
4207
4208        if (frags) {
4209                if (rtl8169_xmit_frags(tp, skb, opts, entry))
4210                        goto err_dma_1;
4211                entry = (entry + frags) % NUM_TX_DESC;
4212        }
4213
4214        txd_last = tp->TxDescArray + entry;
4215        txd_last->opts1 |= cpu_to_le32(LastFrag);
4216        tp->tx_skb[entry].skb = skb;
4217
4218        skb_tx_timestamp(skb);
4219
4220        /* Force memory writes to complete before releasing descriptor */
4221        dma_wmb();
4222
4223        door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4224
4225        txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4226
4227        /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4228        smp_wmb();
4229
4230        tp->cur_tx += frags + 1;
4231
4232        stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4233        if (unlikely(stop_queue)) {
4234                /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4235                 * not miss a ring update when it notices a stopped queue.
4236                 */
4237                smp_wmb();
4238                netif_stop_queue(dev);
4239                door_bell = true;
4240        }
4241
4242        if (door_bell)
4243                rtl8169_doorbell(tp);
4244
4245        if (unlikely(stop_queue)) {
4246                /* Sync with rtl_tx:
4247                 * - publish queue status and cur_tx ring index (write barrier)
4248                 * - refresh dirty_tx ring index (read barrier).
4249                 * May the current thread have a pessimistic view of the ring
4250                 * status and forget to wake up queue, a racing rtl_tx thread
4251                 * can't.
4252                 */
4253                smp_mb();
4254                if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4255                        netif_start_queue(dev);
4256        }
4257
4258        return NETDEV_TX_OK;
4259
4260err_dma_1:
4261        rtl8169_unmap_tx_skb(tp, entry);
4262err_dma_0:
4263        dev_kfree_skb_any(skb);
4264        dev->stats.tx_dropped++;
4265        return NETDEV_TX_OK;
4266
4267err_stop_0:
4268        netif_stop_queue(dev);
4269        dev->stats.tx_dropped++;
4270        return NETDEV_TX_BUSY;
4271}
4272
4273static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4274{
4275        struct skb_shared_info *info = skb_shinfo(skb);
4276        unsigned int nr_frags = info->nr_frags;
4277
4278        if (!nr_frags)
4279                return UINT_MAX;
4280
4281        return skb_frag_size(info->frags + nr_frags - 1);
4282}
4283
4284/* Workaround for hw issues with TSO on RTL8168evl */
4285static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4286                                            netdev_features_t features)
4287{
4288        /* IPv4 header has options field */
4289        if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4290            ip_hdrlen(skb) > sizeof(struct iphdr))
4291                features &= ~NETIF_F_ALL_TSO;
4292
4293        /* IPv4 TCP header has options field */
4294        else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4295                 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4296                features &= ~NETIF_F_ALL_TSO;
4297
4298        else if (rtl_last_frag_len(skb) <= 6)
4299                features &= ~NETIF_F_ALL_TSO;
4300
4301        return features;
4302}
4303
4304static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4305                                                struct net_device *dev,
4306                                                netdev_features_t features)
4307{
4308        int transport_offset = skb_transport_offset(skb);
4309        struct rtl8169_private *tp = netdev_priv(dev);
4310
4311        if (skb_is_gso(skb)) {
4312                if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4313                        features = rtl8168evl_fix_tso(skb, features);
4314
4315                if (transport_offset > GTTCPHO_MAX &&
4316                    rtl_chip_supports_csum_v2(tp))
4317                        features &= ~NETIF_F_ALL_TSO;
4318        } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4319                if (skb->len < ETH_ZLEN) {
4320                        switch (tp->mac_version) {
4321                        case RTL_GIGA_MAC_VER_11:
4322                        case RTL_GIGA_MAC_VER_12:
4323                        case RTL_GIGA_MAC_VER_17:
4324                        case RTL_GIGA_MAC_VER_34:
4325                                features &= ~NETIF_F_CSUM_MASK;
4326                                break;
4327                        default:
4328                                break;
4329                        }
4330                }
4331
4332                if (transport_offset > TCPHO_MAX &&
4333                    rtl_chip_supports_csum_v2(tp))
4334                        features &= ~NETIF_F_CSUM_MASK;
4335        }
4336
4337        return vlan_features_check(skb, features);
4338}
4339
4340static void rtl8169_pcierr_interrupt(struct net_device *dev)
4341{
4342        struct rtl8169_private *tp = netdev_priv(dev);
4343        struct pci_dev *pdev = tp->pci_dev;
4344        int pci_status_errs;
4345        u16 pci_cmd;
4346
4347        pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4348
4349        pci_status_errs = pci_status_get_and_clear_errors(pdev);
4350
4351        if (net_ratelimit())
4352                netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4353                           pci_cmd, pci_status_errs);
4354        /*
4355         * The recovery sequence below admits a very elaborated explanation:
4356         * - it seems to work;
4357         * - I did not see what else could be done;
4358         * - it makes iop3xx happy.
4359         *
4360         * Feel free to adjust to your needs.
4361         */
4362        if (pdev->broken_parity_status)
4363                pci_cmd &= ~PCI_COMMAND_PARITY;
4364        else
4365                pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4366
4367        pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4368
4369        rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4370}
4371
4372static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4373                   int budget)
4374{
4375        unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4376
4377        dirty_tx = tp->dirty_tx;
4378        smp_rmb();
4379
4380        for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4381                unsigned int entry = dirty_tx % NUM_TX_DESC;
4382                struct sk_buff *skb = tp->tx_skb[entry].skb;
4383                u32 status;
4384
4385                status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4386                if (status & DescOwn)
4387                        break;
4388
4389                rtl8169_unmap_tx_skb(tp, entry);
4390
4391                if (skb) {
4392                        pkts_compl++;
4393                        bytes_compl += skb->len;
4394                        napi_consume_skb(skb, budget);
4395                }
4396                dirty_tx++;
4397        }
4398
4399        if (tp->dirty_tx != dirty_tx) {
4400                netdev_completed_queue(dev, pkts_compl, bytes_compl);
4401
4402                u64_stats_update_begin(&tp->tx_stats.syncp);
4403                tp->tx_stats.packets += pkts_compl;
4404                tp->tx_stats.bytes += bytes_compl;
4405                u64_stats_update_end(&tp->tx_stats.syncp);
4406
4407                tp->dirty_tx = dirty_tx;
4408                /* Sync with rtl8169_start_xmit:
4409                 * - publish dirty_tx ring index (write barrier)
4410                 * - refresh cur_tx ring index and queue status (read barrier)
4411                 * May the current thread miss the stopped queue condition,
4412                 * a racing xmit thread can only have a right view of the
4413                 * ring status.
4414                 */
4415                smp_mb();
4416                if (netif_queue_stopped(dev) &&
4417                    rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4418                        netif_wake_queue(dev);
4419                }
4420                /*
4421                 * 8168 hack: TxPoll requests are lost when the Tx packets are
4422                 * too close. Let's kick an extra TxPoll request when a burst
4423                 * of start_xmit activity is detected (if it is not detected,
4424                 * it is slow enough). -- FR
4425                 */
4426                if (tp->cur_tx != dirty_tx)
4427                        rtl8169_doorbell(tp);
4428        }
4429}
4430
4431static inline int rtl8169_fragmented_frame(u32 status)
4432{
4433        return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4434}
4435
4436static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4437{
4438        u32 status = opts1 & RxProtoMask;
4439
4440        if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4441            ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4442                skb->ip_summed = CHECKSUM_UNNECESSARY;
4443        else
4444                skb_checksum_none_assert(skb);
4445}
4446
4447static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4448{
4449        unsigned int cur_rx, rx_left, count;
4450        struct device *d = tp_to_dev(tp);
4451
4452        cur_rx = tp->cur_rx;
4453
4454        for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4455                unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC;
4456                struct RxDesc *desc = tp->RxDescArray + entry;
4457                struct sk_buff *skb;
4458                const void *rx_buf;
4459                dma_addr_t addr;
4460                u32 status;
4461
4462                status = le32_to_cpu(desc->opts1);
4463                if (status & DescOwn)
4464                        break;
4465
4466                /* This barrier is needed to keep us from reading
4467                 * any other fields out of the Rx descriptor until
4468                 * we know the status of DescOwn
4469                 */
4470                dma_rmb();
4471
4472                if (unlikely(status & RxRES)) {
4473                        if (net_ratelimit())
4474                                netdev_warn(dev, "Rx ERROR. status = %08x\n",
4475                                            status);
4476                        dev->stats.rx_errors++;
4477                        if (status & (RxRWT | RxRUNT))
4478                                dev->stats.rx_length_errors++;
4479                        if (status & RxCRC)
4480                                dev->stats.rx_crc_errors++;
4481
4482                        if (!(dev->features & NETIF_F_RXALL))
4483                                goto release_descriptor;
4484                        else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4485                                goto release_descriptor;
4486                }
4487
4488                pkt_size = status & GENMASK(13, 0);
4489                if (likely(!(dev->features & NETIF_F_RXFCS)))
4490                        pkt_size -= ETH_FCS_LEN;
4491
4492                /* The driver does not support incoming fragmented frames.
4493                 * They are seen as a symptom of over-mtu sized frames.
4494                 */
4495                if (unlikely(rtl8169_fragmented_frame(status))) {
4496                        dev->stats.rx_dropped++;
4497                        dev->stats.rx_length_errors++;
4498                        goto release_descriptor;
4499                }
4500
4501                skb = napi_alloc_skb(&tp->napi, pkt_size);
4502                if (unlikely(!skb)) {
4503                        dev->stats.rx_dropped++;
4504                        goto release_descriptor;
4505                }
4506
4507                addr = le64_to_cpu(desc->addr);
4508                rx_buf = page_address(tp->Rx_databuff[entry]);
4509
4510                dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4511                prefetch(rx_buf);
4512                skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4513                skb->tail += pkt_size;
4514                skb->len = pkt_size;
4515                dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4516
4517                rtl8169_rx_csum(skb, status);
4518                skb->protocol = eth_type_trans(skb, dev);
4519
4520                rtl8169_rx_vlan_tag(desc, skb);
4521
4522                if (skb->pkt_type == PACKET_MULTICAST)
4523                        dev->stats.multicast++;
4524
4525                napi_gro_receive(&tp->napi, skb);
4526
4527                u64_stats_update_begin(&tp->rx_stats.syncp);
4528                tp->rx_stats.packets++;
4529                tp->rx_stats.bytes += pkt_size;
4530                u64_stats_update_end(&tp->rx_stats.syncp);
4531
4532release_descriptor:
4533                rtl8169_mark_to_asic(desc);
4534        }
4535
4536        count = cur_rx - tp->cur_rx;
4537        tp->cur_rx = cur_rx;
4538
4539        return count;
4540}
4541
4542static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4543{
4544        struct rtl8169_private *tp = dev_instance;
4545        u32 status = rtl_get_events(tp);
4546
4547        if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
4548            !(status & tp->irq_mask))
4549                return IRQ_NONE;
4550
4551        if (unlikely(status & SYSErr)) {
4552                rtl8169_pcierr_interrupt(tp->dev);
4553                goto out;
4554        }
4555
4556        if (status & LinkChg)
4557                phy_mac_interrupt(tp->phydev);
4558
4559        if (unlikely(status & RxFIFOOver &&
4560            tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4561                netif_stop_queue(tp->dev);
4562                rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4563        }
4564
4565        rtl_irq_disable(tp);
4566        napi_schedule_irqoff(&tp->napi);
4567out:
4568        rtl_ack_events(tp, status);
4569
4570        return IRQ_HANDLED;
4571}
4572
4573static void rtl_task(struct work_struct *work)
4574{
4575        struct rtl8169_private *tp =
4576                container_of(work, struct rtl8169_private, wk.work);
4577
4578        rtnl_lock();
4579
4580        if (!netif_running(tp->dev) ||
4581            !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4582                goto out_unlock;
4583
4584        if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4585                rtl_reset_work(tp);
4586                netif_wake_queue(tp->dev);
4587        }
4588out_unlock:
4589        rtnl_unlock();
4590}
4591
4592static int rtl8169_poll(struct napi_struct *napi, int budget)
4593{
4594        struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4595        struct net_device *dev = tp->dev;
4596        int work_done;
4597
4598        work_done = rtl_rx(dev, tp, (u32) budget);
4599
4600        rtl_tx(dev, tp, budget);
4601
4602        if (work_done < budget) {
4603                napi_complete_done(napi, work_done);
4604                rtl_irq_enable(tp);
4605        }
4606
4607        return work_done;
4608}
4609
4610static void r8169_phylink_handler(struct net_device *ndev)
4611{
4612        struct rtl8169_private *tp = netdev_priv(ndev);
4613
4614        if (netif_carrier_ok(ndev)) {
4615                rtl_link_chg_patch(tp);
4616                pm_request_resume(&tp->pci_dev->dev);
4617        } else {
4618                pm_runtime_idle(&tp->pci_dev->dev);
4619        }
4620
4621        if (net_ratelimit())
4622                phy_print_status(tp->phydev);
4623}
4624
4625static int r8169_phy_connect(struct rtl8169_private *tp)
4626{
4627        struct phy_device *phydev = tp->phydev;
4628        phy_interface_t phy_mode;
4629        int ret;
4630
4631        phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4632                   PHY_INTERFACE_MODE_MII;
4633
4634        ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4635                                 phy_mode);
4636        if (ret)
4637                return ret;
4638
4639        if (!tp->supports_gmii)
4640                phy_set_max_speed(phydev, SPEED_100);
4641
4642        phy_support_asym_pause(phydev);
4643
4644        phy_attached_info(phydev);
4645
4646        return 0;
4647}
4648
4649static void rtl8169_down(struct rtl8169_private *tp)
4650{
4651        /* Clear all task flags */
4652        bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4653
4654        phy_stop(tp->phydev);
4655
4656        rtl8169_update_counters(tp);
4657
4658        rtl8169_cleanup(tp, true);
4659
4660        rtl_pll_power_down(tp);
4661}
4662
4663static void rtl8169_up(struct rtl8169_private *tp)
4664{
4665        rtl_pll_power_up(tp);
4666        rtl8169_init_phy(tp);
4667        napi_enable(&tp->napi);
4668        set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4669        rtl_reset_work(tp);
4670
4671        phy_start(tp->phydev);
4672}
4673
4674static int rtl8169_close(struct net_device *dev)
4675{
4676        struct rtl8169_private *tp = netdev_priv(dev);
4677        struct pci_dev *pdev = tp->pci_dev;
4678
4679        pm_runtime_get_sync(&pdev->dev);
4680
4681        netif_stop_queue(dev);
4682        rtl8169_down(tp);
4683        rtl8169_rx_clear(tp);
4684
4685        cancel_work_sync(&tp->wk.work);
4686
4687        phy_disconnect(tp->phydev);
4688
4689        pci_free_irq(pdev, 0, tp);
4690
4691        dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4692                          tp->RxPhyAddr);
4693        dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4694                          tp->TxPhyAddr);
4695        tp->TxDescArray = NULL;
4696        tp->RxDescArray = NULL;
4697
4698        pm_runtime_put_sync(&pdev->dev);
4699
4700        return 0;
4701}
4702
4703#ifdef CONFIG_NET_POLL_CONTROLLER
4704static void rtl8169_netpoll(struct net_device *dev)
4705{
4706        struct rtl8169_private *tp = netdev_priv(dev);
4707
4708        rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4709}
4710#endif
4711
4712static int rtl_open(struct net_device *dev)
4713{
4714        struct rtl8169_private *tp = netdev_priv(dev);
4715        struct pci_dev *pdev = tp->pci_dev;
4716        int retval = -ENOMEM;
4717
4718        pm_runtime_get_sync(&pdev->dev);
4719
4720        /*
4721         * Rx and Tx descriptors needs 256 bytes alignment.
4722         * dma_alloc_coherent provides more.
4723         */
4724        tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4725                                             &tp->TxPhyAddr, GFP_KERNEL);
4726        if (!tp->TxDescArray)
4727                goto err_pm_runtime_put;
4728
4729        tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4730                                             &tp->RxPhyAddr, GFP_KERNEL);
4731        if (!tp->RxDescArray)
4732                goto err_free_tx_0;
4733
4734        retval = rtl8169_init_ring(tp);
4735        if (retval < 0)
4736                goto err_free_rx_1;
4737
4738        rtl_request_firmware(tp);
4739
4740        retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
4741                                 dev->name);
4742        if (retval < 0)
4743                goto err_release_fw_2;
4744
4745        retval = r8169_phy_connect(tp);
4746        if (retval)
4747                goto err_free_irq;
4748
4749        rtl8169_up(tp);
4750        rtl8169_init_counter_offsets(tp);
4751        netif_start_queue(dev);
4752
4753        pm_runtime_put_sync(&pdev->dev);
4754out:
4755        return retval;
4756
4757err_free_irq:
4758        pci_free_irq(pdev, 0, tp);
4759err_release_fw_2:
4760        rtl_release_firmware(tp);
4761        rtl8169_rx_clear(tp);
4762err_free_rx_1:
4763        dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4764                          tp->RxPhyAddr);
4765        tp->RxDescArray = NULL;
4766err_free_tx_0:
4767        dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4768                          tp->TxPhyAddr);
4769        tp->TxDescArray = NULL;
4770err_pm_runtime_put:
4771        pm_runtime_put_noidle(&pdev->dev);
4772        goto out;
4773}
4774
4775static void
4776rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4777{
4778        struct rtl8169_private *tp = netdev_priv(dev);
4779        struct pci_dev *pdev = tp->pci_dev;
4780        struct rtl8169_counters *counters = tp->counters;
4781        unsigned int start;
4782
4783        pm_runtime_get_noresume(&pdev->dev);
4784
4785        netdev_stats_to_stats64(stats, &dev->stats);
4786
4787        do {
4788                start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
4789                stats->rx_packets = tp->rx_stats.packets;
4790                stats->rx_bytes = tp->rx_stats.bytes;
4791        } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
4792
4793        do {
4794                start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
4795                stats->tx_packets = tp->tx_stats.packets;
4796                stats->tx_bytes = tp->tx_stats.bytes;
4797        } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
4798
4799        /*
4800         * Fetch additional counter values missing in stats collected by driver
4801         * from tally counters.
4802         */
4803        if (pm_runtime_active(&pdev->dev))
4804                rtl8169_update_counters(tp);
4805
4806        /*
4807         * Subtract values fetched during initalization.
4808         * See rtl8169_init_counter_offsets for a description why we do that.
4809         */
4810        stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4811                le64_to_cpu(tp->tc_offset.tx_errors);
4812        stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4813                le32_to_cpu(tp->tc_offset.tx_multi_collision);
4814        stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4815                le16_to_cpu(tp->tc_offset.tx_aborted);
4816        stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4817                le16_to_cpu(tp->tc_offset.rx_missed);
4818
4819        pm_runtime_put_noidle(&pdev->dev);
4820}
4821
4822static void rtl8169_net_suspend(struct rtl8169_private *tp)
4823{
4824        netif_device_detach(tp->dev);
4825
4826        if (netif_running(tp->dev))
4827                rtl8169_down(tp);
4828}
4829
4830#ifdef CONFIG_PM
4831
4832static int rtl8169_net_resume(struct rtl8169_private *tp)
4833{
4834        rtl_rar_set(tp, tp->dev->dev_addr);
4835
4836        if (tp->TxDescArray)
4837                rtl8169_up(tp);
4838
4839        netif_device_attach(tp->dev);
4840
4841        return 0;
4842}
4843
4844static int __maybe_unused rtl8169_suspend(struct device *device)
4845{
4846        struct rtl8169_private *tp = dev_get_drvdata(device);
4847
4848        rtnl_lock();
4849        rtl8169_net_suspend(tp);
4850        if (!device_may_wakeup(tp_to_dev(tp)))
4851                clk_disable_unprepare(tp->clk);
4852        rtnl_unlock();
4853
4854        return 0;
4855}
4856
4857static int __maybe_unused rtl8169_resume(struct device *device)
4858{
4859        struct rtl8169_private *tp = dev_get_drvdata(device);
4860
4861        if (!device_may_wakeup(tp_to_dev(tp)))
4862                clk_prepare_enable(tp->clk);
4863
4864        /* Reportedly at least Asus X453MA truncates packets otherwise */
4865        if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4866                rtl_init_rxcfg(tp);
4867
4868        return rtl8169_net_resume(tp);
4869}
4870
4871static int rtl8169_runtime_suspend(struct device *device)
4872{
4873        struct rtl8169_private *tp = dev_get_drvdata(device);
4874
4875        if (!tp->TxDescArray) {
4876                netif_device_detach(tp->dev);
4877                return 0;
4878        }
4879
4880        rtnl_lock();
4881        __rtl8169_set_wol(tp, WAKE_PHY);
4882        rtl8169_net_suspend(tp);
4883        rtnl_unlock();
4884
4885        return 0;
4886}
4887
4888static int rtl8169_runtime_resume(struct device *device)
4889{
4890        struct rtl8169_private *tp = dev_get_drvdata(device);
4891
4892        __rtl8169_set_wol(tp, tp->saved_wolopts);
4893
4894        return rtl8169_net_resume(tp);
4895}
4896
4897static int rtl8169_runtime_idle(struct device *device)
4898{
4899        struct rtl8169_private *tp = dev_get_drvdata(device);
4900
4901        if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4902                pm_schedule_suspend(device, 10000);
4903
4904        return -EBUSY;
4905}
4906
4907static const struct dev_pm_ops rtl8169_pm_ops = {
4908        SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4909        SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4910                           rtl8169_runtime_idle)
4911};
4912
4913#endif /* CONFIG_PM */
4914
4915static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4916{
4917        /* WoL fails with 8168b when the receiver is disabled. */
4918        switch (tp->mac_version) {
4919        case RTL_GIGA_MAC_VER_11:
4920        case RTL_GIGA_MAC_VER_12:
4921        case RTL_GIGA_MAC_VER_17:
4922                pci_clear_master(tp->pci_dev);
4923
4924                RTL_W8(tp, ChipCmd, CmdRxEnb);
4925                rtl_pci_commit(tp);
4926                break;
4927        default:
4928                break;
4929        }
4930}
4931
4932static void rtl_shutdown(struct pci_dev *pdev)
4933{
4934        struct rtl8169_private *tp = pci_get_drvdata(pdev);
4935
4936        rtnl_lock();
4937        rtl8169_net_suspend(tp);
4938        rtnl_unlock();
4939
4940        /* Restore original MAC address */
4941        rtl_rar_set(tp, tp->dev->perm_addr);
4942
4943        if (system_state == SYSTEM_POWER_OFF) {
4944                if (tp->saved_wolopts) {
4945                        rtl_wol_suspend_quirk(tp);
4946                        rtl_wol_shutdown_quirk(tp);
4947                }
4948
4949                pci_wake_from_d3(pdev, true);
4950                pci_set_power_state(pdev, PCI_D3hot);
4951        }
4952}
4953
4954static void rtl_remove_one(struct pci_dev *pdev)
4955{
4956        struct rtl8169_private *tp = pci_get_drvdata(pdev);
4957
4958        if (pci_dev_run_wake(pdev))
4959                pm_runtime_get_noresume(&pdev->dev);
4960
4961        unregister_netdev(tp->dev);
4962
4963        if (r8168_check_dash(tp))
4964                rtl8168_driver_stop(tp);
4965
4966        rtl_release_firmware(tp);
4967
4968        /* restore original MAC address */
4969        rtl_rar_set(tp, tp->dev->perm_addr);
4970}
4971
4972static const struct net_device_ops rtl_netdev_ops = {
4973        .ndo_open               = rtl_open,
4974        .ndo_stop               = rtl8169_close,
4975        .ndo_get_stats64        = rtl8169_get_stats64,
4976        .ndo_start_xmit         = rtl8169_start_xmit,
4977        .ndo_features_check     = rtl8169_features_check,
4978        .ndo_tx_timeout         = rtl8169_tx_timeout,
4979        .ndo_validate_addr      = eth_validate_addr,
4980        .ndo_change_mtu         = rtl8169_change_mtu,
4981        .ndo_fix_features       = rtl8169_fix_features,
4982        .ndo_set_features       = rtl8169_set_features,
4983        .ndo_set_mac_address    = rtl_set_mac_address,
4984        .ndo_do_ioctl           = phy_do_ioctl_running,
4985        .ndo_set_rx_mode        = rtl_set_rx_mode,
4986#ifdef CONFIG_NET_POLL_CONTROLLER
4987        .ndo_poll_controller    = rtl8169_netpoll,
4988#endif
4989
4990};
4991
4992static void rtl_set_irq_mask(struct rtl8169_private *tp)
4993{
4994        tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
4995
4996        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4997                tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
4998        else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
4999                /* special workaround needed */
5000                tp->irq_mask |= RxFIFOOver;

5001        else
5002                tp->irq_mask |= RxOverflow;
5003}
5004
5005static int rtl_alloc_irq(struct rtl8169_private *tp)
5006{
5007        unsigned int flags;
5008
5009        switch (tp->mac_version) {
5010        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5011                rtl_unlock_config_regs(tp);
5012                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5013                rtl_lock_config_regs(tp);
5014                fallthrough;
5015        case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5016                flags = PCI_IRQ_LEGACY;
5017                break;
5018        default:
5019                flags = PCI_IRQ_ALL_TYPES;
5020                break;
5021        }
5022
5023        return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5024}
5025
5026static void rtl_read_mac_address(struct rtl8169_private *tp,
5027                                 u8 mac_addr[ETH_ALEN])
5028{
5029        /* Get MAC address */
5030        if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5031                u32 value = rtl_eri_read(tp, 0xe0);
5032
5033                mac_addr[0] = (value >>  0) & 0xff;
5034                mac_addr[1] = (value >>  8) & 0xff;
5035                mac_addr[2] = (value >> 16) & 0xff;
5036                mac_addr[3] = (value >> 24) & 0xff;
5037
5038                value = rtl_eri_read(tp, 0xe4);
5039                mac_addr[4] = (value >>  0) & 0xff;
5040                mac_addr[5] = (value >>  8) & 0xff;
5041        } else if (rtl_is_8125(tp)) {
5042                rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5043        }
5044}
5045
5046DECLARE_RTL_COND(rtl_link_list_ready_cond)
5047{
5048        return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5049}
5050
5051static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5052{
5053        rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5054}
5055
5056static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5057{
5058        struct rtl8169_private *tp = mii_bus->priv;
5059
5060        if (phyaddr > 0)
5061                return -ENODEV;
5062
5063        return rtl_readphy(tp, phyreg);
5064}
5065
5066static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5067                                int phyreg, u16 val)
5068{
5069        struct rtl8169_private *tp = mii_bus->priv;
5070
5071        if (phyaddr > 0)
5072                return -ENODEV;
5073
5074        rtl_writephy(tp, phyreg, val);
5075
5076        return 0;
5077}
5078
5079static int r8169_mdio_register(struct rtl8169_private *tp)
5080{
5081        struct pci_dev *pdev = tp->pci_dev;
5082        struct mii_bus *new_bus;
5083        int ret;
5084
5085        new_bus = devm_mdiobus_alloc(&pdev->dev);
5086        if (!new_bus)
5087                return -ENOMEM;
5088
5089        new_bus->name = "r8169";
5090        new_bus->priv = tp;
5091        new_bus->parent = &pdev->dev;
5092        new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5093        snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5094
5095        new_bus->read = r8169_mdio_read_reg;
5096        new_bus->write = r8169_mdio_write_reg;
5097
5098        ret = devm_mdiobus_register(&pdev->dev, new_bus);
5099        if (ret)
5100                return ret;
5101
5102        tp->phydev = mdiobus_get_phy(new_bus, 0);
5103        if (!tp->phydev) {
5104                return -ENODEV;
5105        } else if (!tp->phydev->drv) {
5106                /* Most chip versions fail with the genphy driver.
5107                 * Therefore ensure that the dedicated PHY driver is loaded.
5108                 */
5109                dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5110                        tp->phydev->phy_id);
5111                return -EUNATCH;
5112        }
5113
5114        /* PHY will be woken up in rtl_open() */
5115        phy_suspend(tp->phydev);
5116
5117        return 0;
5118}
5119
5120static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5121{
5122        rtl_enable_rxdvgate(tp);
5123
5124        RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5125        msleep(1);
5126        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5127
5128        r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5129        r8168g_wait_ll_share_fifo_ready(tp);
5130
5131        r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5132        r8168g_wait_ll_share_fifo_ready(tp);
5133}
5134
5135static void rtl_hw_init_8125(struct rtl8169_private *tp)
5136{
5137        rtl_enable_rxdvgate(tp);
5138
5139        RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5140        msleep(1);
5141        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5142
5143        r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5144        r8168g_wait_ll_share_fifo_ready(tp);
5145
5146        r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5147        r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5148        r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5149        r8168g_wait_ll_share_fifo_ready(tp);
5150}
5151
5152static void rtl_hw_initialize(struct rtl8169_private *tp)
5153{
5154        switch (tp->mac_version) {
5155        case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5156                rtl8168ep_stop_cmac(tp);
5157                fallthrough;
5158        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5159                rtl_hw_init_8168g(tp);
5160                break;
5161        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5162                rtl_hw_init_8125(tp);
5163                break;
5164        default:
5165                break;
5166        }
5167}
5168
5169static int rtl_jumbo_max(struct rtl8169_private *tp)
5170{
5171        /* Non-GBit versions don't support jumbo frames */
5172        if (!tp->supports_gmii)
5173                return 0;
5174
5175        switch (tp->mac_version) {
5176        /* RTL8169 */
5177        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5178                return JUMBO_7K;
5179        /* RTL8168b */
5180        case RTL_GIGA_MAC_VER_11:
5181        case RTL_GIGA_MAC_VER_12:
5182        case RTL_GIGA_MAC_VER_17:
5183                return JUMBO_4K;
5184        /* RTL8168c */
5185        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5186                return JUMBO_6K;
5187        default:
5188                return JUMBO_9K;
5189        }
5190}
5191
5192static void rtl_disable_clk(void *data)
5193{
5194        clk_disable_unprepare(data);
5195}
5196
5197static int rtl_get_ether_clk(struct rtl8169_private *tp)
5198{
5199        struct device *d = tp_to_dev(tp);
5200        struct clk *clk;
5201        int rc;
5202
5203        clk = devm_clk_get(d, "ether_clk");
5204        if (IS_ERR(clk)) {
5205                rc = PTR_ERR(clk);
5206                if (rc == -ENOENT)
5207                        /* clk-core allows NULL (for suspend / resume) */
5208                        rc = 0;
5209                else if (rc != -EPROBE_DEFER)
5210                        dev_err(d, "failed to get clk: %d\n", rc);
5211        } else {
5212                tp->clk = clk;
5213                rc = clk_prepare_enable(clk);
5214                if (rc)
5215                        dev_err(d, "failed to enable clk: %d\n", rc);
5216                else
5217                        rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5218        }
5219
5220        return rc;
5221}
5222
5223static void rtl_init_mac_address(struct rtl8169_private *tp)
5224{
5225        struct net_device *dev = tp->dev;
5226        u8 *mac_addr = dev->dev_addr;
5227        int rc;
5228
5229        rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5230        if (!rc)
5231                goto done;
5232
5233        rtl_read_mac_address(tp, mac_addr);
5234        if (is_valid_ether_addr(mac_addr))
5235                goto done;
5236
5237        rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5238        if (is_valid_ether_addr(mac_addr))
5239                goto done;
5240
5241        eth_hw_addr_random(dev);
5242        dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5243done:
5244        rtl_rar_set(tp, mac_addr);
5245}
5246
5247static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5248{
5249        struct rtl8169_private *tp;
5250        int jumbo_max, region, rc;
5251        enum mac_version chipset;
5252        struct net_device *dev;
5253        u16 xid;
5254
5255        dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5256        if (!dev)
5257                return -ENOMEM;
5258
5259        SET_NETDEV_DEV(dev, &pdev->dev);
5260        dev->netdev_ops = &rtl_netdev_ops;
5261        tp = netdev_priv(dev);
5262        tp->dev = dev;
5263        tp->pci_dev = pdev;
5264        tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5265        tp->eee_adv = -1;
5266        tp->ocp_base = OCP_STD_PHY_BASE;
5267
5268        /* Get the *optional* external "ether_clk" used on some boards */
5269        rc = rtl_get_ether_clk(tp);
5270        if (rc)
5271                return rc;
5272
5273        /* Disable ASPM completely as that cause random device stop working
5274         * problems as well as full system hangs for some PCIe devices users.
5275         */
5276        rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5277                                          PCIE_LINK_STATE_L1);
5278        tp->aspm_manageable = !rc;
5279
5280        /* enable device (incl. PCI PM wakeup and hotplug setup) */
5281        rc = pcim_enable_device(pdev);
5282        if (rc < 0) {
5283                dev_err(&pdev->dev, "enable failure\n");
5284                return rc;
5285        }
5286
5287        if (pcim_set_mwi(pdev) < 0)
5288                dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5289
5290        /* use first MMIO region */
5291        region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5292        if (region < 0) {
5293                dev_err(&pdev->dev, "no MMIO resource found\n");
5294                return -ENODEV;
5295        }
5296
5297        /* check for weird/broken PCI region reporting */
5298        if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5299                dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5300                return -ENODEV;
5301        }
5302
5303        rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5304        if (rc < 0) {
5305                dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5306                return rc;
5307        }
5308
5309        tp->mmio_addr = pcim_iomap_table(pdev)[region];
5310
5311        xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5312
5313        /* Identify chip attached to board */
5314        chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5315        if (chipset == RTL_GIGA_MAC_NONE) {
5316                dev_err(&pdev->dev, "unknown chip XID %03x\n", xid);
5317                return -ENODEV;
5318        }
5319
5320        tp->mac_version = chipset;
5321
5322        tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5323
5324        if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5325            !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5326                dev->features |= NETIF_F_HIGHDMA;
5327
5328        rtl_init_rxcfg(tp);
5329
5330        rtl8169_irq_mask_and_ack(tp);
5331
5332        rtl_hw_initialize(tp);
5333
5334        rtl_hw_reset(tp);
5335
5336        pci_set_master(pdev);
5337
5338        rc = rtl_alloc_irq(tp);
5339        if (rc < 0) {
5340                dev_err(&pdev->dev, "Can't allocate interrupt\n");
5341                return rc;
5342        }
5343
5344        INIT_WORK(&tp->wk.work, rtl_task);
5345        u64_stats_init(&tp->rx_stats.syncp);
5346        u64_stats_init(&tp->tx_stats.syncp);
5347
5348        rtl_init_mac_address(tp);
5349
5350        dev->ethtool_ops = &rtl8169_ethtool_ops;
5351
5352        netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5353
5354        dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5355                           NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5356        dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5357        dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5358
5359        /*
5360         * Pretend we are using VLANs; This bypasses a nasty bug where
5361         * Interrupts stop flowing on high load on 8110SCd controllers.
5362         */
5363        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5364                /* Disallow toggling */
5365                dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5366
5367        if (rtl_chip_supports_csum_v2(tp))
5368                dev->hw_features |= NETIF_F_IPV6_CSUM;
5369
5370        dev->features |= dev->hw_features;
5371
5372        /* There has been a number of reports that using SG/TSO results in
5373         * tx timeouts. However for a lot of people SG/TSO works fine.
5374         * Therefore disable both features by default, but allow users to
5375         * enable them. Use at own risk!
5376         */
5377        if (rtl_chip_supports_csum_v2(tp)) {
5378                dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5379                dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5380                dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5381        } else {
5382                dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5383                dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5384                dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5385        }
5386
5387        dev->hw_features |= NETIF_F_RXALL;
5388        dev->hw_features |= NETIF_F_RXFCS;
5389
5390        /* configure chip for default features */
5391        rtl8169_set_features(dev, dev->features);
5392
5393        jumbo_max = rtl_jumbo_max(tp);
5394        if (jumbo_max)
5395                dev->max_mtu = jumbo_max;
5396
5397        rtl_set_irq_mask(tp);
5398
5399        tp->fw_name = rtl_chip_infos[chipset].fw_name;
5400
5401        tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5402                                            &tp->counters_phys_addr,
5403                                            GFP_KERNEL);
5404        if (!tp->counters)
5405                return -ENOMEM;
5406
5407        pci_set_drvdata(pdev, tp);
5408
5409        rc = r8169_mdio_register(tp);
5410        if (rc)
5411                return rc;
5412
5413        /* chip gets powered up in rtl_open() */
5414        rtl_pll_power_down(tp);
5415
5416        rc = register_netdev(dev);
5417        if (rc)
5418                return rc;
5419
5420        netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5421                    rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5422                    pci_irq_vector(pdev, 0));
5423
5424        if (jumbo_max)
5425                netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5426                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5427                            "ok" : "ko");
5428
5429        if (r8168_check_dash(tp)) {
5430                netdev_info(dev, "DASH enabled\n");
5431                rtl8168_driver_start(tp);
5432        }
5433
5434        if (pci_dev_run_wake(pdev))
5435                pm_runtime_put_sync(&pdev->dev);
5436
5437        return 0;
5438}
5439
5440static struct pci_driver rtl8169_pci_driver = {
5441        .name           = MODULENAME,
5442        .id_table       = rtl8169_pci_tbl,
5443        .probe          = rtl_init_one,
5444        .remove         = rtl_remove_one,
5445        .shutdown       = rtl_shutdown,
5446#ifdef CONFIG_PM
5447        .driver.pm      = &rtl8169_pm_ops,
5448#endif
5449};
5450
5451module_pci_driver(rtl8169_pci_driver);
5452