1
2#ifndef __HD64570_H
3#define __HD64570_H
4
5
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8
9
10
11
12
13
14#define LPR 0x00
15
16
17#define PABR0 0x02
18#define PABR1 0x03
19#define WCRL 0x04
20#define WCRM 0x05
21#define WCRH 0x06
22
23#define PCR 0x08
24#define DMER 0x09
25
26
27
28#define ISR0 0x10
29#define ISR1 0x11
30#define ISR2 0x12
31
32#define IER0 0x14
33#define IER1 0x15
34#define IER2 0x16
35
36#define ITCR 0x18
37#define IVR 0x1A
38#define IMVR 0x1C
39
40
41
42
43
44
45#define MSCI0_OFFSET 0x20
46#define MSCI1_OFFSET 0x40
47
48#define TRBL 0x00
49#define TRBH 0x01
50#define ST0 0x02
51#define ST1 0x03
52#define ST2 0x04
53#define ST3 0x05
54#define FST 0x06
55#define IE0 0x08
56#define IE1 0x09
57#define IE2 0x0A
58#define FIE 0x0B
59#define CMD 0x0C
60#define MD0 0x0E
61#define MD1 0x0F
62#define MD2 0x10
63#define CTL 0x11
64#define SA0 0x12
65#define SA1 0x13
66#define IDL 0x14
67#define TMC 0x15
68#define RXS 0x16
69#define TXS 0x17
70#define TRC0 0x18
71#define TRC1 0x19
72#define RRC 0x1A
73#define CST0 0x1C
74#define CST1 0x1D
75
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81
82
83#define TIMER0RX_OFFSET 0x60
84#define TIMER0TX_OFFSET 0x68
85#define TIMER1RX_OFFSET 0x70
86#define TIMER1TX_OFFSET 0x78
87
88#define TCNTL 0x00
89#define TCNTH 0x01
90#define TCONRL 0x02
91#define TCONRH 0x03
92#define TCSR 0x04
93#define TEPR 0x05
94
95
96
97
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100
101
102
103#define DMAC0RX_OFFSET 0x80
104#define DMAC0TX_OFFSET 0xA0
105#define DMAC1RX_OFFSET 0xC0
106#define DMAC1TX_OFFSET 0xE0
107
108#define BARL 0x00
109#define BARH 0x01
110#define BARB 0x02
111
112#define DARL 0x00
113#define DARH 0x01
114#define DARB 0x02
115
116#define SARL 0x04
117#define SARH 0x05
118#define SARB 0x06
119
120#define CPB 0x06
121
122#define CDAL 0x08
123#define CDAH 0x09
124#define EDAL 0x0A
125#define EDAH 0x0B
126#define BFLL 0x0C
127#define BFLH 0x0D
128#define BCRL 0x0E
129#define BCRH 0x0F
130#define DSR 0x10
131#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
132#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
133#define DMR 0x11
134#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
135#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
136#define FCT 0x13
137#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
138#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
139#define DIR 0x14
140#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
141#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
142#define DCR 0x15
143#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
144#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
145
146
147
148
149
150
151typedef struct {
152 u16 cp;
153 u32 bp;
154 u16 len;
155 u8 stat;
156 u8 unused;
157}__packed pkt_desc;
158
159
160
161
162#define ST_TX_EOM 0x80
163#define ST_TX_EOT 0x01
164
165#define ST_RX_EOM 0x80
166#define ST_RX_SHORT 0x40
167#define ST_RX_ABORT 0x20
168#define ST_RX_RESBIT 0x10
169#define ST_RX_OVERRUN 0x08
170#define ST_RX_CRC 0x04
171
172#define ST_ERROR_MASK 0x7C
173
174#define DIR_EOTE 0x80
175#define DIR_EOME 0x40
176#define DIR_BOFE 0x20
177#define DIR_COFE 0x10
178
179
180#define DSR_EOT 0x80
181#define DSR_EOM 0x40
182#define DSR_BOF 0x20
183#define DSR_COF 0x10
184#define DSR_DE 0x02
185#define DSR_DWE 0x01
186
187
188#define DMER_DME 0x80
189
190
191#define CMD_RESET 0x21
192#define CMD_TX_ENABLE 0x02
193#define CMD_RX_ENABLE 0x12
194
195#define MD0_HDLC 0x80
196#define MD0_CRC_ENA 0x04
197#define MD0_CRC_CCITT 0x02
198#define MD0_CRC_PR1 0x01
199
200#define MD0_CRC_NONE 0x00
201#define MD0_CRC_16_0 0x04
202#define MD0_CRC_16 0x05
203#define MD0_CRC_ITU_0 0x06
204#define MD0_CRC_ITU 0x07
205
206#define MD2_NRZ 0x00
207#define MD2_NRZI 0x20
208#define MD2_MANCHESTER 0x80
209#define MD2_FM_MARK 0xA0
210#define MD2_FM_SPACE 0xC0
211#define MD2_LOOPBACK 0x03
212
213#define CTL_NORTS 0x01
214#define CTL_IDLE 0x10
215#define CTL_UDRNC 0x20
216
217#define ST0_TXRDY 0x02
218#define ST0_RXRDY 0x01
219
220#define ST1_UDRN 0x80
221#define ST1_CDCD 0x04
222
223#define ST3_CTS 0x08
224#define ST3_DCD 0x04
225
226#define IE0_TXINT 0x80
227#define IE0_RXINTA 0x40
228#define IE1_UDRN 0x80
229#define IE1_CDCD 0x04
230
231#define DCR_ABORT 0x01
232#define DCR_CLEAR_EOF 0x02
233
234
235#define CLK_BRG_MASK 0x0F
236#define CLK_LINE_RX 0x00
237#define CLK_LINE_TX 0x00
238#define CLK_BRG_RX 0x40
239#define CLK_BRG_TX 0x40
240#define CLK_RXCLK_TX 0x60
241
242#endif
243