1
2
3#include <linux/etherdevice.h>
4#include "mt7603.h"
5#include "mac.h"
6#include "eeprom.h"
7
8const struct mt76_driver_ops mt7603_drv_ops = {
9 .txwi_size = MT_TXD_SIZE,
10 .drv_flags = MT_DRV_SW_RX_AIRTIME,
11 .survey_flags = SURVEY_INFO_TIME_TX,
12 .tx_prepare_skb = mt7603_tx_prepare_skb,
13 .tx_complete_skb = mt7603_tx_complete_skb,
14 .rx_skb = mt7603_queue_rx_skb,
15 .rx_poll_complete = mt7603_rx_poll_complete,
16 .sta_ps = mt7603_sta_ps,
17 .sta_add = mt7603_sta_add,
18 .sta_assoc = mt7603_sta_assoc,
19 .sta_remove = mt7603_sta_remove,
20 .update_survey = mt7603_update_channel,
21};
22
23static void
24mt7603_set_tmac_template(struct mt7603_dev *dev)
25{
26 u32 desc[5] = {
27 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),
28 [3] = MT_TXD5_SW_POWER_MGMT
29 };
30 u32 addr;
31 int i;
32
33 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
34 addr += MT_CLIENT_TMAC_INFO_TEMPLATE;
35 for (i = 0; i < ARRAY_SIZE(desc); i++)
36 mt76_wr(dev, addr + 4 * i, desc[i]);
37}
38
39static void
40mt7603_dma_sched_init(struct mt7603_dev *dev)
41{
42 int page_size = 128;
43 int page_count;
44 int max_len = 1792;
45 int max_amsdu_pages = 4096 / page_size;
46 int max_mcu_len = 4096;
47 int max_beacon_len = 512 * 4 + max_len;
48 int max_mcast_pages = 4 * max_len / page_size;
49 int reserved_count = 0;
50 int beacon_pages;
51 int mcu_pages;
52 int i;
53
54 page_count = mt76_get_field(dev, MT_PSE_FC_P0,
55 MT_PSE_FC_P0_MAX_QUOTA);
56 beacon_pages = 4 * (max_beacon_len / page_size);
57 mcu_pages = max_mcu_len / page_size;
58
59 mt76_wr(dev, MT_PSE_FRP,
60 FIELD_PREP(MT_PSE_FRP_P0, 7) |
61 FIELD_PREP(MT_PSE_FRP_P1, 6) |
62 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4));
63
64 mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);
65 mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);
66
67 mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);
68 mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);
69
70 mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);
71
72 mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));
73 mt76_wr(dev, MT_SCH_2, max_amsdu_pages);
74
75 for (i = 0; i <= 4; i++)
76 mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages);
77 reserved_count += 5 * max_amsdu_pages;
78
79 mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);
80 reserved_count += mcu_pages;
81
82 mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);
83 reserved_count += beacon_pages;
84
85 mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages);
86 reserved_count += max_mcast_pages;
87
88 if (is_mt7603(dev))
89 reserved_count = 0;
90
91 mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count);
92
93 if (is_mt7603(dev) && mt76xx_rev(dev) >= MT7603_REV_E2) {
94 mt76_wr(dev, MT_GROUP_THRESH(0),
95 page_count - beacon_pages - mcu_pages);
96 mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);
97 mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);
98 mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);
99 mt76_wr(dev, MT_BMAP_1, 0x00000020);
100 } else {
101 mt76_wr(dev, MT_GROUP_THRESH(0), page_count);
102 mt76_wr(dev, MT_BMAP_0, 0xffff);
103 }
104
105 mt76_wr(dev, MT_SCH_4, 0);
106
107 for (i = 0; i <= 15; i++)
108 mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);
109
110 mt76_set(dev, MT_SCH_4, BIT(6));
111}
112
113static void
114mt7603_phy_init(struct mt7603_dev *dev)
115{
116 int rx_chains = dev->mphy.antenna_mask;
117 int tx_chains = hweight8(rx_chains) - 1;
118
119 mt76_rmw(dev, MT_WF_RMAC_RMCR,
120 (MT_WF_RMAC_RMCR_SMPS_MODE |
121 MT_WF_RMAC_RMCR_RX_STREAMS),
122 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) |
123 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains)));
124
125 mt76_rmw_field(dev, MT_TMAC_TCR, MT_TMAC_TCR_TX_STREAMS,
126 tx_chains);
127
128 dev->agc0 = mt76_rr(dev, MT_AGC(0));
129 dev->agc3 = mt76_rr(dev, MT_AGC(3));
130}
131
132static void
133mt7603_mac_init(struct mt7603_dev *dev)
134{
135 u8 bc_addr[ETH_ALEN];
136 u32 addr;
137 int i;
138
139 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0,
140 (MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
141 (MT_AGG_SIZE_LIMIT(1) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
142 (MT_AGG_SIZE_LIMIT(2) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
143 (MT_AGG_SIZE_LIMIT(3) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
144
145 mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1,
146 (MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
147 (MT_AGG_SIZE_LIMIT(5) << 1 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
148 (MT_AGG_SIZE_LIMIT(6) << 2 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |
149 (MT_AGG_SIZE_LIMIT(7) << 3 * MT_AGG_BA_SIZE_LIMIT_SHIFT));
150
151 mt76_wr(dev, MT_AGG_LIMIT,
152 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
153 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
154 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
155 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
156
157 mt76_wr(dev, MT_AGG_LIMIT_1,
158 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |
159 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) |
160 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) |
161 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24));
162
163 mt76_wr(dev, MT_AGG_CONTROL,
164 FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |
165 FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |
166 MT_AGG_CONTROL_NO_BA_AR_RULE);
167
168 mt76_wr(dev, MT_AGG_RETRY_CONTROL,
169 FIELD_PREP(MT_AGG_RETRY_CONTROL_BAR_LIMIT, 1) |
170 FIELD_PREP(MT_AGG_RETRY_CONTROL_RTS_LIMIT, 15));
171
172 mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |
173 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 4096));
174
175 mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));
176 mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));
177
178 mt76_clear(dev, MT_WF_RMAC_TMR_PA, BIT(31));
179
180 mt76_set(dev, MT_WF_RMACDR, MT_WF_RMACDR_MAXLEN_20BIT);
181 mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);
182
183 mt76_wr(dev, MT_WF_RFCR1, 0);
184
185 mt76_set(dev, MT_TMAC_TCR, MT_TMAC_TCR_RX_RIFS_MODE);
186
187 mt7603_set_tmac_template(dev);
188
189
190 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR);
191 mt76_set(dev, addr + MT_CLIENT_RXINF, MT_CLIENT_RXINF_RXSH_GROUPS);
192
193
194 mt76_set(dev, MT_DMA_DCR1, GENMASK(13, 11));
195
196 mt76_rmw_field(dev, MT_AGG_PCR_RTS, MT_AGG_PCR_RTS_PKT_THR, 3);
197 mt76_set(dev, MT_TMAC_PCR, MT_TMAC_PCR_SPE_EN);
198
199
200 mt76_rmw_field(dev, MT_TXREQ, MT_TXREQ_CCA_SRC_SEL, 2);
201
202 mt76_wr(dev, MT_RXREQ, 4);
203
204
205 mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);
206
207
208 mt76_wr(dev, MT_DMA_TCFR0,
209 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) |
210 MT_DMA_TCFR_TXS_AGGR_COUNT);
211
212
213 mt76_wr(dev, MT_DMA_TCFR1,
214 FIELD_PREP(MT_DMA_TCFR_TXS_AGGR_TIMEOUT, 1) |
215 MT_DMA_TCFR_TXS_AGGR_COUNT |
216 MT_DMA_TCFR_TXS_BIT_MAP);
217
218 mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);
219
220 for (i = 0; i < MT7603_WTBL_SIZE; i++)
221 mt7603_wtbl_clear(dev, i);
222
223 eth_broadcast_addr(bc_addr);
224 mt7603_wtbl_init(dev, MT7603_WTBL_RESERVED, -1, bc_addr);
225 dev->global_sta.wcid.idx = MT7603_WTBL_RESERVED;
226 rcu_assign_pointer(dev->mt76.wcid[MT7603_WTBL_RESERVED],
227 &dev->global_sta.wcid);
228
229 mt76_rmw_field(dev, MT_LPON_BTEIR, MT_LPON_BTEIR_MBSS_MODE, 2);
230 mt76_rmw_field(dev, MT_WF_RMACDR, MT_WF_RMACDR_MBSSID_MASK, 2);
231
232 mt76_wr(dev, MT_AGG_ARUCR,
233 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |
234 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) |
235 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) |
236 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) |
237 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) |
238 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), 1) |
239 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), 1) |
240 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), 1));
241
242 mt76_wr(dev, MT_AGG_ARDCR,
243 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |
244 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), MT7603_RATE_RETRY - 1) |
245 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), MT7603_RATE_RETRY - 1) |
246 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), MT7603_RATE_RETRY - 1) |
247 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), MT7603_RATE_RETRY - 1) |
248 FIELD_PREP(MT_AGG_ARxCR_LIMIT(5), MT7603_RATE_RETRY - 1) |
249 FIELD_PREP(MT_AGG_ARxCR_LIMIT(6), MT7603_RATE_RETRY - 1) |
250 FIELD_PREP(MT_AGG_ARxCR_LIMIT(7), MT7603_RATE_RETRY - 1));
251
252 mt76_wr(dev, MT_AGG_ARCR,
253 (FIELD_PREP(MT_AGG_ARCR_RTS_RATE_THR, 2) |
254 MT_AGG_ARCR_RATE_DOWN_RATIO_EN |
255 FIELD_PREP(MT_AGG_ARCR_RATE_DOWN_RATIO, 1) |
256 FIELD_PREP(MT_AGG_ARCR_RATE_UP_EXTRA_TH, 4)));
257
258 mt76_set(dev, MT_WTBL_RMVTCR, MT_WTBL_RMVTCR_RX_MV_MODE);
259
260 mt76_clear(dev, MT_SEC_SCR, MT_SEC_SCR_MASK_ORDER);
261 mt76_clear(dev, MT_SEC_SCR, BIT(18));
262
263
264 for (i = 0; i <= 4; i++)
265 mt76_rmw_field(dev, MT_LPON_SBTOR(i), MT_LPON_SBTOR_TIME_OFFSET,
266 (i + 1) * (20 + 4096));
267}
268
269static int
270mt7603_init_hardware(struct mt7603_dev *dev)
271{
272 int i, ret;
273
274 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
275
276 ret = mt7603_eeprom_init(dev);
277 if (ret < 0)
278 return ret;
279
280 ret = mt7603_dma_init(dev);
281 if (ret)
282 return ret;
283
284 mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);
285 mt7603_mac_dma_start(dev);
286 dev->rxfilter = mt76_rr(dev, MT_WF_RFCR);
287 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
288
289 for (i = 0; i < MT7603_WTBL_SIZE; i++) {
290 mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE |
291 FIELD_PREP(MT_PSE_RTA_TAG_ID, i));
292 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
293 }
294
295 ret = mt7603_mcu_init(dev);
296 if (ret)
297 return ret;
298
299 mt7603_dma_sched_init(dev);
300 mt7603_mcu_set_eeprom(dev);
301 mt7603_phy_init(dev);
302 mt7603_mac_init(dev);
303
304 return 0;
305}
306
307#define CCK_RATE(_idx, _rate) { \
308 .bitrate = _rate, \
309 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
310 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
311 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
312}
313
314#define OFDM_RATE(_idx, _rate) { \
315 .bitrate = _rate, \
316 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
317 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
318}
319
320static struct ieee80211_rate mt7603_rates[] = {
321 CCK_RATE(0, 10),
322 CCK_RATE(1, 20),
323 CCK_RATE(2, 55),
324 CCK_RATE(3, 110),
325 OFDM_RATE(11, 60),
326 OFDM_RATE(15, 90),
327 OFDM_RATE(10, 120),
328 OFDM_RATE(14, 180),
329 OFDM_RATE(9, 240),
330 OFDM_RATE(13, 360),
331 OFDM_RATE(8, 480),
332 OFDM_RATE(12, 540),
333};
334
335static const struct ieee80211_iface_limit if_limits[] = {
336 {
337 .max = 1,
338 .types = BIT(NL80211_IFTYPE_ADHOC)
339 }, {
340 .max = MT7603_MAX_INTERFACES,
341 .types = BIT(NL80211_IFTYPE_STATION) |
342#ifdef CONFIG_MAC80211_MESH
343 BIT(NL80211_IFTYPE_MESH_POINT) |
344#endif
345 BIT(NL80211_IFTYPE_P2P_CLIENT) |
346 BIT(NL80211_IFTYPE_P2P_GO) |
347 BIT(NL80211_IFTYPE_AP)
348 },
349};
350
351static const struct ieee80211_iface_combination if_comb[] = {
352 {
353 .limits = if_limits,
354 .n_limits = ARRAY_SIZE(if_limits),
355 .max_interfaces = 4,
356 .num_different_channels = 1,
357 .beacon_int_infra_match = true,
358 }
359};
360
361static void mt7603_led_set_config(struct mt76_dev *mt76, u8 delay_on,
362 u8 delay_off)
363{
364 struct mt7603_dev *dev = container_of(mt76, struct mt7603_dev,
365 mt76);
366 u32 val, addr;
367
368 val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |
369 FIELD_PREP(MT_LED_STATUS_OFF, delay_off) |
370 FIELD_PREP(MT_LED_STATUS_ON, delay_on);
371
372 addr = mt7603_reg_map(dev, MT_LED_STATUS_0(mt76->led_pin));
373 mt76_wr(dev, addr, val);
374 addr = mt7603_reg_map(dev, MT_LED_STATUS_1(mt76->led_pin));
375 mt76_wr(dev, addr, val);
376
377 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
378 MT_LED_CTRL_KICK(mt76->led_pin);
379 if (mt76->led_al)
380 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
381 addr = mt7603_reg_map(dev, MT_LED_CTRL);
382 mt76_wr(dev, addr, val);
383}
384
385static int mt7603_led_set_blink(struct led_classdev *led_cdev,
386 unsigned long *delay_on,
387 unsigned long *delay_off)
388{
389 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
390 led_cdev);
391 u8 delta_on, delta_off;
392
393 delta_off = max_t(u8, *delay_off / 10, 1);
394 delta_on = max_t(u8, *delay_on / 10, 1);
395
396 mt7603_led_set_config(mt76, delta_on, delta_off);
397 return 0;
398}
399
400static void mt7603_led_set_brightness(struct led_classdev *led_cdev,
401 enum led_brightness brightness)
402{
403 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
404 led_cdev);
405
406 if (!brightness)
407 mt7603_led_set_config(mt76, 0, 0xff);
408 else
409 mt7603_led_set_config(mt76, 0xff, 0);
410}
411
412static u32 __mt7603_reg_addr(struct mt7603_dev *dev, u32 addr)
413{
414 if (addr < 0x100000)
415 return addr;
416
417 return mt7603_reg_map(dev, addr);
418}
419
420static u32 mt7603_rr(struct mt76_dev *mdev, u32 offset)
421{
422 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
423 u32 addr = __mt7603_reg_addr(dev, offset);
424
425 return dev->bus_ops->rr(mdev, addr);
426}
427
428static void mt7603_wr(struct mt76_dev *mdev, u32 offset, u32 val)
429{
430 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
431 u32 addr = __mt7603_reg_addr(dev, offset);
432
433 dev->bus_ops->wr(mdev, addr, val);
434}
435
436static u32 mt7603_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
437{
438 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
439 u32 addr = __mt7603_reg_addr(dev, offset);
440
441 return dev->bus_ops->rmw(mdev, addr, mask, val);
442}
443
444static void
445mt7603_regd_notifier(struct wiphy *wiphy,
446 struct regulatory_request *request)
447{
448 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
449 struct mt7603_dev *dev = hw->priv;
450
451 dev->mt76.region = request->dfs_region;
452 dev->ed_monitor = dev->ed_monitor_enabled &&
453 dev->mt76.region == NL80211_DFS_ETSI;
454}
455
456static int
457mt7603_txpower_signed(int val)
458{
459 bool sign = val & BIT(6);
460
461 if (!(val & BIT(7)))
462 return 0;
463
464 val &= GENMASK(5, 0);
465 if (!sign)
466 val = -val;
467
468 return val;
469}
470
471static void
472mt7603_init_txpower(struct mt7603_dev *dev,
473 struct ieee80211_supported_band *sband)
474{
475 struct ieee80211_channel *chan;
476 u8 *eeprom = (u8 *)dev->mt76.eeprom.data;
477 int target_power = eeprom[MT_EE_TX_POWER_0_START_2G + 2] & ~BIT(7);
478 u8 *rate_power = &eeprom[MT_EE_TX_POWER_CCK];
479 bool ext_pa = eeprom[MT_EE_NIC_CONF_0 + 1] & BIT(1);
480 int max_offset, cur_offset;
481 int i;
482
483 if (ext_pa && is_mt7603(dev))
484 target_power = eeprom[MT_EE_TX_POWER_TSSI_OFF] & ~BIT(7);
485
486 if (target_power & BIT(6))
487 target_power = -(target_power & GENMASK(5, 0));
488
489 max_offset = 0;
490 for (i = 0; i < 14; i++) {
491 cur_offset = mt7603_txpower_signed(rate_power[i]);
492 max_offset = max(max_offset, cur_offset);
493 }
494
495 target_power += max_offset;
496
497 dev->tx_power_limit = target_power;
498 dev->mphy.txpower_cur = target_power;
499
500 target_power = DIV_ROUND_UP(target_power, 2);
501
502
503 if (dev->mphy.antenna_mask & BIT(1))
504 target_power += 3;
505
506 for (i = 0; i < sband->n_channels; i++) {
507 chan = &sband->channels[i];
508 chan->max_power = min_t(int, chan->max_reg_power, target_power);
509 chan->orig_mpwr = target_power;
510 }
511}
512
513int mt7603_register_device(struct mt7603_dev *dev)
514{
515 struct mt76_bus_ops *bus_ops;
516 struct ieee80211_hw *hw = mt76_hw(dev);
517 struct wiphy *wiphy = hw->wiphy;
518 int ret;
519
520 dev->bus_ops = dev->mt76.bus;
521 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
522 GFP_KERNEL);
523 if (!bus_ops)
524 return -ENOMEM;
525
526 bus_ops->rr = mt7603_rr;
527 bus_ops->wr = mt7603_wr;
528 bus_ops->rmw = mt7603_rmw;
529 dev->mt76.bus = bus_ops;
530
531 INIT_LIST_HEAD(&dev->sta_poll_list);
532 spin_lock_init(&dev->sta_poll_lock);
533 spin_lock_init(&dev->ps_lock);
534
535 INIT_DELAYED_WORK(&dev->mt76.mac_work, mt7603_mac_work);
536 tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt7603_pre_tbtt_tasklet,
537 (unsigned long)dev);
538
539
540 dev->mphy.antenna_mask = 3;
541 if (mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4))
542 dev->mphy.antenna_mask = 1;
543
544 dev->slottime = 9;
545 dev->sensitivity_limit = 28;
546 dev->dynamic_sensitivity = true;
547
548 ret = mt7603_init_hardware(dev);
549 if (ret)
550 return ret;
551
552 hw->queues = 4;
553 hw->max_rates = 3;
554 hw->max_report_rates = 7;
555 hw->max_rate_tries = 11;
556
557 hw->sta_data_size = sizeof(struct mt7603_sta);
558 hw->vif_data_size = sizeof(struct mt7603_vif);
559
560 wiphy->iface_combinations = if_comb;
561 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
562
563 ieee80211_hw_set(hw, TX_STATUS_NO_AMPDU_LEN);
564 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
565
566
567 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
568 dev->mt76.led_cdev.brightness_set = mt7603_led_set_brightness;
569 dev->mt76.led_cdev.blink_set = mt7603_led_set_blink;
570 }
571
572 wiphy->reg_notifier = mt7603_regd_notifier;
573
574 ret = mt76_register_device(&dev->mt76, true, mt7603_rates,
575 ARRAY_SIZE(mt7603_rates));
576 if (ret)
577 return ret;
578
579 mt7603_init_debugfs(dev);
580 mt7603_init_txpower(dev, &dev->mphy.sband_2g.sband);
581
582 return 0;
583}
584
585void mt7603_unregister_device(struct mt7603_dev *dev)
586{
587 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
588 mt76_unregister_device(&dev->mt76);
589 mt7603_mcu_exit(dev);
590 mt7603_dma_cleanup(dev);
591 mt76_free_device(&dev->mt76);
592}
593
