1
2
3
4#include <linux/etherdevice.h>
5#include <linux/timekeeping.h>
6#include "mt7915.h"
7#include "../dma.h"
8#include "mac.h"
9
10#define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
11
12#define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
13#define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
14 IEEE80211_RADIOTAP_HE_##f)
15
16static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
18 .radar_pattern = {
19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
27 },
28};
29
30static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
32 .radar_pattern = {
33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
38 },
39};
40
41static const struct mt7915_dfs_radar_spec jp_radar_specs = {
42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
43 .radar_pattern = {
44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
52 },
53};
54
55static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
56 u16 idx, bool unicast)
57{
58 struct mt7915_sta *sta;
59 struct mt76_wcid *wcid;
60
61 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
62 return NULL;
63
64 wcid = rcu_dereference(dev->mt76.wcid[idx]);
65 if (unicast || !wcid)
66 return wcid;
67
68 if (!wcid->sta)
69 return NULL;
70
71 sta = container_of(wcid, struct mt7915_sta, wcid);
72 if (!sta->vif)
73 return NULL;
74
75 return &sta->vif->sta.wcid;
76}
77
78void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
79{
80}
81
82bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
83{
84 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
85 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
86
87 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
88 0, 5000);
89}
90
91static u32 mt7915_mac_wtbl_lmac_read(struct mt7915_dev *dev, u16 wcid,
92 u16 addr)
93{
94 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
95 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
96
97 return mt76_rr(dev, MT_WTBL_LMAC_OFFS(wcid, addr));
98}
99
100
101void mt7915_mac_sta_poll(struct mt7915_dev *dev)
102{
103 static const u8 ac_to_tid[] = {
104 [IEEE80211_AC_BE] = 0,
105 [IEEE80211_AC_BK] = 1,
106 [IEEE80211_AC_VI] = 4,
107 [IEEE80211_AC_VO] = 6
108 };
109 static const u8 hw_queue_map[] = {
110 [IEEE80211_AC_BK] = 0,
111 [IEEE80211_AC_BE] = 1,
112 [IEEE80211_AC_VI] = 2,
113 [IEEE80211_AC_VO] = 3,
114 };
115 struct ieee80211_sta *sta;
116 struct mt7915_sta *msta;
117 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
118 int i;
119
120 rcu_read_lock();
121
122 while (true) {
123 bool clear = false;
124 u16 idx;
125
126 spin_lock_bh(&dev->sta_poll_lock);
127 if (list_empty(&dev->sta_poll_list)) {
128 spin_unlock_bh(&dev->sta_poll_lock);
129 break;
130 }
131 msta = list_first_entry(&dev->sta_poll_list,
132 struct mt7915_sta, poll_list);
133 list_del_init(&msta->poll_list);
134 spin_unlock_bh(&dev->sta_poll_lock);
135
136 for (i = 0, idx = msta->wcid.idx; i < IEEE80211_NUM_ACS; i++) {
137 u32 tx_last = msta->airtime_ac[i];
138 u32 rx_last = msta->airtime_ac[i + IEEE80211_NUM_ACS];
139
140 msta->airtime_ac[i] =
141 mt7915_mac_wtbl_lmac_read(dev, idx, 20 + i);
142 msta->airtime_ac[i + IEEE80211_NUM_ACS] =
143 mt7915_mac_wtbl_lmac_read(dev, idx, 21 + i);
144 tx_time[i] = msta->airtime_ac[i] - tx_last;
145 rx_time[i] = msta->airtime_ac[i + IEEE80211_NUM_ACS] -
146 rx_last;
147
148 if ((tx_last | rx_last) & BIT(30))
149 clear = true;
150 }
151
152 if (clear) {
153 mt7915_mac_wtbl_update(dev, idx,
154 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
155 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
156 }
157
158 if (!msta->wcid.sta)
159 continue;
160
161 sta = container_of((void *)msta, struct ieee80211_sta,
162 drv_priv);
163 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
164 u32 tx_cur = tx_time[i];
165 u32 rx_cur = rx_time[hw_queue_map[i]];
166 u8 tid = ac_to_tid[i];
167
168 if (!tx_cur && !rx_cur)
169 continue;
170
171 ieee80211_sta_register_airtime(sta, tid, tx_cur,
172 rx_cur);
173 }
174 }
175
176 rcu_read_unlock();
177}
178
179static void
180mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
181 struct ieee80211_radiotap_he *he,
182 __le32 *rxv)
183{
184 u32 ru_h, ru_l;
185 u8 ru, offs = 0;
186
187 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0]));
188 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1]));
189 ru = (u8)(ru_l | ru_h << 4);
190
191 status->bw = RATE_INFO_BW_HE_RU;
192
193 switch (ru) {
194 case 0 ... 36:
195 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
196 offs = ru;
197 break;
198 case 37 ... 52:
199 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
200 offs = ru - 37;
201 break;
202 case 53 ... 60:
203 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
204 offs = ru - 53;
205 break;
206 case 61 ... 64:
207 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
208 offs = ru - 61;
209 break;
210 case 65 ... 66:
211 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
212 offs = ru - 65;
213 break;
214 case 67:
215 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
216 break;
217 case 68:
218 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
219 break;
220 }
221
222 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
223 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
224 le16_encode_bits(offs,
225 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
226}
227
228static void
229mt7915_mac_decode_he_radiotap(struct sk_buff *skb,
230 struct mt76_rx_status *status,
231 __le32 *rxv, u32 phy)
232{
233
234 static const struct ieee80211_radiotap_he known = {
235 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
236 HE_BITS(DATA1_DATA_DCM_KNOWN) |
237 HE_BITS(DATA1_STBC_KNOWN) |
238 HE_BITS(DATA1_CODING_KNOWN) |
239 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
240 HE_BITS(DATA1_DOPPLER_KNOWN) |
241 HE_BITS(DATA1_BSS_COLOR_KNOWN),
242 .data2 = HE_BITS(DATA2_GI_KNOWN) |
243 HE_BITS(DATA2_TXBF_KNOWN) |
244 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
245 HE_BITS(DATA2_TXOP_KNOWN),
246 };
247 struct ieee80211_radiotap_he *he = NULL;
248 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1;
249
250 he = skb_push(skb, sizeof(known));
251 memcpy(he, &known, sizeof(known));
252
253 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) |
254 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]);
255 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) |
256 le16_encode_bits(ltf_size,
257 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
258 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) |
259 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]);
260
261 switch (phy) {
262 case MT_PHY_TYPE_HE_SU:
263 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
264 HE_BITS(DATA1_UL_DL_KNOWN) |
265 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
266 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
267
268 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) |
269 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
270 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
271 break;
272 case MT_PHY_TYPE_HE_EXT_SU:
273 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
274 HE_BITS(DATA1_UL_DL_KNOWN);
275
276 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
277 break;
278 case MT_PHY_TYPE_HE_MU:
279 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
280 HE_BITS(DATA1_UL_DL_KNOWN) |
281 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
282
283 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
284 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
285
286 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
287 break;
288 case MT_PHY_TYPE_HE_TB:
289 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
290 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
291 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
292 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
293 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
294
295 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) |
296 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) |
297 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) |
298 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]);
299
300 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
301 break;
302 default:
303 break;
304 }
305}
306
307int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
308{
309 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
310 struct mt76_phy *mphy = &dev->mt76.phy;
311 struct mt7915_phy *phy = &dev->phy;
312 struct ieee80211_supported_band *sband;
313 struct ieee80211_hdr *hdr;
314 __le32 *rxd = (__le32 *)skb->data;
315 __le32 *rxv = NULL;
316 u32 mode = 0;
317 u32 rxd1 = le32_to_cpu(rxd[1]);
318 u32 rxd2 = le32_to_cpu(rxd[2]);
319 u32 rxd3 = le32_to_cpu(rxd[3]);
320 bool unicast, insert_ccmp_hdr = false;
321 u8 remove_pad;
322 int i, idx;
323
324 memset(status, 0, sizeof(*status));
325
326 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) {
327 mphy = dev->mt76.phy2;
328 if (!mphy)
329 return -EINVAL;
330
331 phy = mphy->priv;
332 status->ext_phy = true;
333 }
334
335 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
336 return -EINVAL;
337
338 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
339 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
340 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
341
342 if (status->wcid) {
343 struct mt7915_sta *msta;
344
345 msta = container_of(status->wcid, struct mt7915_sta, wcid);
346 spin_lock_bh(&dev->sta_poll_lock);
347 if (list_empty(&msta->poll_list))
348 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
349 spin_unlock_bh(&dev->sta_poll_lock);
350 }
351
352 status->freq = mphy->chandef.chan->center_freq;
353 status->band = mphy->chandef.chan->band;
354 if (status->band == NL80211_BAND_5GHZ)
355 sband = &mphy->sband_5g.sband;
356 else
357 sband = &mphy->sband_2g.sband;
358
359 if (!sband->channels)
360 return -EINVAL;
361
362 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
363 status->flag |= RX_FLAG_FAILED_FCS_CRC;
364
365 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
366 status->flag |= RX_FLAG_MMIC_ERROR;
367
368 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
369 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
370 status->flag |= RX_FLAG_DECRYPTED;
371 status->flag |= RX_FLAG_IV_STRIPPED;
372 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
373 }
374
375 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
376 status->flag |= RX_FLAG_AMPDU_DETAILS;
377
378
379 if (phy->rx_ampdu_ts != rxd[14]) {
380 if (!++phy->ampdu_ref)
381 phy->ampdu_ref++;
382 }
383 phy->rx_ampdu_ts = rxd[14];
384
385 status->ampdu_ref = phy->ampdu_ref;
386 }
387
388 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
389
390 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
391 return -EINVAL;
392
393 rxd += 6;
394 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
395 rxd += 4;
396 if ((u8 *)rxd - skb->data >= skb->len)
397 return -EINVAL;
398 }
399
400 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
401 u8 *data = (u8 *)rxd;
402
403 if (status->flag & RX_FLAG_DECRYPTED) {
404 status->iv[0] = data[5];
405 status->iv[1] = data[4];
406 status->iv[2] = data[3];
407 status->iv[3] = data[2];
408 status->iv[4] = data[1];
409 status->iv[5] = data[0];
410
411 insert_ccmp_hdr = FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
412 }
413 rxd += 4;
414 if ((u8 *)rxd - skb->data >= skb->len)
415 return -EINVAL;
416 }
417
418 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
419 rxd += 2;
420 if ((u8 *)rxd - skb->data >= skb->len)
421 return -EINVAL;
422 }
423
424
425 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
426 u32 v0, v1, v2;
427
428 rxv = rxd;
429 rxd += 2;
430 if ((u8 *)rxd - skb->data >= skb->len)
431 return -EINVAL;
432
433 v0 = le32_to_cpu(rxv[0]);
434 v1 = le32_to_cpu(rxv[1]);
435 v2 = le32_to_cpu(rxv[2]);
436
437 if (v0 & MT_PRXV_HT_AD_CODE)
438 status->enc_flags |= RX_ENC_FLAG_LDPC;
439
440 status->chains = mphy->antenna_mask;
441 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
442 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
443 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
444 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
445 status->signal = status->chain_signal[0];
446
447 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
448 if (!(status->chains & BIT(i)))
449 continue;
450
451 status->signal = max(status->signal,
452 status->chain_signal[i]);
453 }
454
455
456 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
457 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
458 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
459 bool cck = false;
460
461 rxd += 18;
462 if ((u8 *)rxd - skb->data >= skb->len)
463 return -EINVAL;
464
465 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
466 mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
467
468 switch (mode) {
469 case MT_PHY_TYPE_CCK:
470 cck = true;
471
472 case MT_PHY_TYPE_OFDM:
473 i = mt76_get_rate(&dev->mt76, sband, i, cck);
474 break;
475 case MT_PHY_TYPE_HT_GF:
476 case MT_PHY_TYPE_HT:
477 status->encoding = RX_ENC_HT;
478 if (i > 31)
479 return -EINVAL;
480 break;
481 case MT_PHY_TYPE_VHT:
482 status->nss =
483 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
484 status->encoding = RX_ENC_VHT;
485 if (i > 9)
486 return -EINVAL;
487 break;
488 case MT_PHY_TYPE_HE_MU:
489 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
490
491 case MT_PHY_TYPE_HE_SU:
492 case MT_PHY_TYPE_HE_EXT_SU:
493 case MT_PHY_TYPE_HE_TB:
494 status->nss =
495 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
496 status->encoding = RX_ENC_HE;
497 status->flag |= RX_FLAG_RADIOTAP_HE;
498 i &= GENMASK(3, 0);
499
500 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
501 status->he_gi = gi;
502
503 status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
504 break;
505 default:
506 return -EINVAL;
507 }
508 status->rate_idx = i;
509
510 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
511 case IEEE80211_STA_RX_BW_20:
512 break;
513 case IEEE80211_STA_RX_BW_40:
514 if (mode & MT_PHY_TYPE_HE_EXT_SU &&
515 (idx & MT_PRXV_TX_ER_SU_106T)) {
516 status->bw = RATE_INFO_BW_HE_RU;
517 status->he_ru =
518 NL80211_RATE_INFO_HE_RU_ALLOC_106;
519 } else {
520 status->bw = RATE_INFO_BW_40;
521 }
522 break;
523 case IEEE80211_STA_RX_BW_80:
524 status->bw = RATE_INFO_BW_80;
525 break;
526 case IEEE80211_STA_RX_BW_160:
527 status->bw = RATE_INFO_BW_160;
528 break;
529 default:
530 return -EINVAL;
531 }
532
533 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
534 if (mode < MT_PHY_TYPE_HE_SU && gi)
535 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
536 }
537 }
538
539 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
540
541 if (insert_ccmp_hdr) {
542 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
543
544 mt76_insert_ccmp_hdr(skb, key_id);
545 }
546
547 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE)
548 mt7915_mac_decode_he_radiotap(skb, status, rxv, mode);
549
550 hdr = mt76_skb_get_hdr(skb);
551 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
552 return 0;
553
554 status->aggr = unicast &&
555 !ieee80211_is_qos_nullfunc(hdr->frame_control);
556 status->tid = *ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_TID_MASK;
557 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
558
559 return 0;
560}
561
562void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
563 struct sk_buff *skb, struct mt76_wcid *wcid,
564 struct ieee80211_key_conf *key, bool beacon)
565{
566 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
567 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
568 bool multicast = is_multicast_ether_addr(hdr->addr1);
569 struct ieee80211_vif *vif = info->control.vif;
570 struct mt76_phy *mphy = &dev->mphy;
571 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
572 u8 fc_type, fc_stype, p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
573 __le16 fc = hdr->frame_control;
574 u16 tx_count = 4, seqno = 0;
575 u32 val;
576
577 if (vif) {
578 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
579
580 omac_idx = mvif->omac_idx;
581 wmm_idx = mvif->wmm_idx;
582 }
583
584 if (ext_phy && dev->mt76.phy2)
585 mphy = dev->mt76.phy2;
586
587 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
588 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
589
590 if (beacon) {
591 p_fmt = MT_TX_TYPE_FW;
592 q_idx = MT_LMAC_BCN0;
593 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
594 p_fmt = MT_TX_TYPE_CT;
595 q_idx = MT_LMAC_ALTX0;
596 } else {
597 p_fmt = MT_TX_TYPE_CT;
598 q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
599 mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb));
600 }
601
602 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
603 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) |
604 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
605 txwi[0] = cpu_to_le32(val);
606
607 val = MT_TXD1_LONG_FORMAT |
608 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
609 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
610 FIELD_PREP(MT_TXD1_HDR_INFO,
611 ieee80211_get_hdrlen_from_skb(skb) / 2) |
612 FIELD_PREP(MT_TXD1_TID,
613 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
614 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
615
616 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0)
617 val |= MT_TXD1_TGID;
618
619 txwi[1] = cpu_to_le32(val);
620
621 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
622 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
623 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
624 if (key) {
625 if (multicast && ieee80211_is_robust_mgmt_frame(skb) &&
626 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
627 val |= MT_TXD2_BIP;
628 txwi[3] = 0;
629 } else {
630 txwi[3] = cpu_to_le32(MT_TXD3_PROTECT_FRAME);
631 }
632 } else {
633 txwi[3] = 0;
634 }
635 txwi[2] = cpu_to_le32(val);
636
637 txwi[4] = 0;
638 txwi[5] = 0;
639 txwi[6] = 0;
640
641 if (!ieee80211_is_data(fc) || multicast) {
642 u16 rate;
643
644
645 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE | MT_TXD2_HTC_VLD);
646
647 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
648 rate = MT7915_5G_RATE_DEFAULT;
649 else
650 rate = MT7915_2G_RATE_DEFAULT;
651
652 val = MT_TXD6_FIXED_BW |
653 FIELD_PREP(MT_TXD6_TX_RATE, rate);
654 txwi[6] |= cpu_to_le32(val);
655 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
656 }
657
658 if (!ieee80211_is_beacon(fc))
659 txwi[3] |= cpu_to_le32(MT_TXD3_SW_POWER_MGMT);
660 else
661 tx_count = 0x1f;
662
663 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
664 txwi[3] |= cpu_to_le32(MT_TXD3_NO_ACK);
665
666 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
667 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
668 txwi[7] = cpu_to_le32(val);
669
670 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
671 if (ieee80211_is_data_qos(fc)) {
672 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
673 val |= MT_TXD3_SN_VALID;
674 } else if (ieee80211_is_back_req(fc)) {
675 struct ieee80211_bar *bar;
676
677 bar = (struct ieee80211_bar *)skb->data;
678 seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(bar->start_seq_num));
679 val |= MT_TXD3_SN_VALID;
680 }
681 val |= FIELD_PREP(MT_TXD3_SEQ, seqno);
682 txwi[3] |= cpu_to_le32(val);
683}
684
685int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
686 enum mt76_txq_id qid, struct mt76_wcid *wcid,
687 struct ieee80211_sta *sta,
688 struct mt76_tx_info *tx_info)
689{
690 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
691 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
692 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
693 struct ieee80211_key_conf *key = info->control.hw_key;
694 struct ieee80211_vif *vif = info->control.vif;
695 struct mt76_tx_cb *cb = mt76_tx_skb_cb(tx_info->skb);
696 struct mt76_txwi_cache *t;
697 struct mt7915_txp *txp;
698 int id, i, nbuf = tx_info->nbuf - 1;
699 u8 *txwi = (u8 *)txwi_ptr;
700
701 if (!wcid)
702 wcid = &dev->mt76.global_wcid;
703
704 cb->wcid = wcid->idx;
705
706 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, key,
707 false);
708
709 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
710 for (i = 0; i < nbuf; i++) {
711 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
712 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
713 }
714 txp->nbuf = nbuf;
715
716
717 tx_info->buf[1].len = MT_CT_PARSE_LEN;
718 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
719
720 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD);
721
722 if (!key)
723 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
724
725 if (ieee80211_is_mgmt(hdr->frame_control))
726 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
727
728 if (vif) {
729 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
730
731 txp->bss_idx = mvif->idx;
732 }
733
734 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
735 t->skb = tx_info->skb;
736
737 spin_lock_bh(&dev->token_lock);
738 id = idr_alloc(&dev->token, t, 0, MT7915_TOKEN_SIZE, GFP_ATOMIC);
739 spin_unlock_bh(&dev->token_lock);
740 if (id < 0)
741 return id;
742
743 txp->token = cpu_to_le16(id);
744 txp->rept_wds_wcid = 0xff;
745 tx_info->skb = DMA_DUMMY_DATA;
746
747 return 0;
748}
749
750static inline bool
751mt7915_tx_check_aggr_tid(struct mt7915_sta *msta, u8 tid)
752{
753 bool ret = false;
754
755 spin_lock_bh(&msta->ampdu_lock);
756 if (msta->ampdu_state[tid] == MT7915_AGGR_STOP)
757 ret = true;
758 spin_unlock_bh(&msta->ampdu_lock);
759
760 return ret;
761}
762
763static void
764mt7915_tx_check_aggr(struct ieee80211_sta *sta, struct sk_buff *skb)
765{
766 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
767 struct mt7915_sta *msta;
768 u16 tid;
769
770 if (!sta->ht_cap.ht_supported)
771 return;
772
773 if (skb_get_queue_mapping(skb) == IEEE80211_AC_VO)
774 return;
775
776 if (unlikely(!ieee80211_is_data_qos(hdr->frame_control)))
777 return;
778
779 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE)))
780 return;
781
782 msta = (struct mt7915_sta *)sta->drv_priv;
783 tid = ieee80211_get_tid(hdr);
784
785 if (mt7915_tx_check_aggr_tid(msta, tid)) {
786 ieee80211_start_tx_ba_session(sta, tid, 0);
787 mt7915_set_aggr_state(msta, tid, MT7915_AGGR_PROGRESS);
788 }
789}
790
791static inline void
792mt7915_tx_status(struct ieee80211_sta *sta, struct ieee80211_hw *hw,
793 struct ieee80211_tx_info *info, struct sk_buff *skb)
794{
795 struct ieee80211_tx_status status = {
796 .sta = sta,
797 .info = info,
798 };
799
800 if (skb)
801 status.skb = skb;
802
803 if (sta) {
804 struct mt7915_sta *msta;
805
806 msta = (struct mt7915_sta *)sta->drv_priv;
807 status.rate = &msta->stats.tx_rate;
808 }
809
810
811 ieee80211_tx_status_ext(hw, &status);
812}
813
814static void
815mt7915_tx_complete_status(struct mt76_dev *mdev, struct sk_buff *skb,
816 struct ieee80211_sta *sta, u8 stat)
817{
818 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
819 struct ieee80211_hw *hw;
820
821 hw = mt76_tx_status_get_hw(mdev, skb);
822
823 if (info->flags & IEEE80211_TX_CTL_AMPDU)
824 info->flags |= IEEE80211_TX_STAT_AMPDU;
825 else if (sta)
826 mt7915_tx_check_aggr(sta, skb);
827
828 if (stat)
829 ieee80211_tx_info_clear_status(info);
830
831 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
832 info->flags |= IEEE80211_TX_STAT_ACK;
833
834 info->status.tx_time = 0;
835
836 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
837 mt7915_tx_status(sta, hw, info, skb);
838 return;
839 }
840
841 if (sta || !(info->flags & IEEE80211_TX_CTL_NO_ACK))
842 mt7915_tx_status(sta, hw, info, NULL);
843
844 ieee80211_free_txskb(hw, skb);
845}
846
847void mt7915_txp_skb_unmap(struct mt76_dev *dev,
848 struct mt76_txwi_cache *t)
849{
850 struct mt7915_txp *txp;
851 int i;
852
853 txp = mt7915_txwi_to_txp(dev, t);
854 for (i = 1; i < txp->nbuf; i++)
855 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
856 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
857}
858
859void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
860{
861 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data;
862 struct mt76_dev *mdev = &dev->mt76;
863 struct mt76_txwi_cache *txwi;
864 struct ieee80211_sta *sta = NULL;
865 u8 i, count;
866
867
868
869
870
871
872 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
873 for (i = 0; i < count; i++) {
874 u32 msdu, info = le32_to_cpu(free->info[i]);
875 u8 stat;
876
877
878
879
880
881 if (info & MT_TX_FREE_PAIR) {
882 struct mt7915_sta *msta;
883 struct mt76_wcid *wcid;
884 u16 idx;
885
886 count++;
887 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
888 wcid = rcu_dereference(dev->mt76.wcid[idx]);
889 sta = wcid_to_sta(wcid);
890 if (!sta)
891 continue;
892
893 msta = container_of(wcid, struct mt7915_sta, wcid);
894 ieee80211_queue_work(mt76_hw(dev), &msta->stats_work);
895 continue;
896 }
897
898 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
899 stat = FIELD_GET(MT_TX_FREE_STATUS, info);
900
901 spin_lock_bh(&dev->token_lock);
902 txwi = idr_remove(&dev->token, msdu);
903 spin_unlock_bh(&dev->token_lock);
904
905 if (!txwi)
906 continue;
907
908 mt7915_txp_skb_unmap(mdev, txwi);
909 if (txwi->skb) {
910 mt7915_tx_complete_status(mdev, txwi->skb, sta, stat);
911 txwi->skb = NULL;
912 }
913
914 mt76_put_txwi(mdev, txwi);
915 }
916 dev_kfree_skb(skb);
917}
918
919void mt7915_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
920 struct mt76_queue_entry *e)
921{
922 struct mt7915_dev *dev;
923
924 if (!e->txwi) {
925 dev_kfree_skb_any(e->skb);
926 return;
927 }
928
929 dev = container_of(mdev, struct mt7915_dev, mt76);
930
931
932 if (e->skb == DMA_DUMMY_DATA) {
933 struct mt76_txwi_cache *t;
934 struct mt7915_txp *txp;
935
936 txp = mt7915_txwi_to_txp(mdev, e->txwi);
937
938 spin_lock_bh(&dev->token_lock);
939 t = idr_remove(&dev->token, le16_to_cpu(txp->token));
940 spin_unlock_bh(&dev->token_lock);
941 e->skb = t ? t->skb : NULL;
942 }
943
944 if (e->skb) {
945 struct mt76_tx_cb *cb = mt76_tx_skb_cb(e->skb);
946 struct mt76_wcid *wcid;
947
948 wcid = rcu_dereference(dev->mt76.wcid[cb->wcid]);
949
950 mt7915_tx_complete_status(mdev, e->skb, wcid_to_sta(wcid), 0);
951 }
952}
953
954void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
955{
956 struct mt7915_dev *dev = phy->dev;
957 bool ext_phy = phy != &dev->phy;
958 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy);
959
960 mt7915_l2_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
961 mt7915_l2_set(dev, reg, BIT(11) | BIT(9));
962}
963
964void mt7915_mac_reset_counters(struct mt7915_phy *phy)
965{
966 struct mt7915_dev *dev = phy->dev;
967 bool ext_phy = phy != &dev->phy;
968 int i;
969
970 for (i = 0; i < 4; i++) {
971 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
972 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
973 }
974
975 if (ext_phy) {
976 dev->mt76.phy2->survey_time = ktime_get_boottime();
977 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
978 } else {
979 dev->mt76.phy.survey_time = ktime_get_boottime();
980 i = 0;
981 }
982 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
983
984
985 mt76_rr(dev, MT_MIB_SDR9(ext_phy));
986 mt76_rr(dev, MT_MIB_SDR36(ext_phy));
987 mt76_rr(dev, MT_MIB_SDR37(ext_phy));
988
989 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(ext_phy),
990 MT_WF_RMAC_MIB_RXTIME_CLR);
991 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy),
992 MT_WF_RMAC_MIB_RXTIME_CLR);
993}
994
995void mt7915_mac_set_timing(struct mt7915_phy *phy)
996{
997 s16 coverage_class = phy->coverage_class;
998 struct mt7915_dev *dev = phy->dev;
999 bool ext_phy = phy != &dev->phy;
1000 u32 val, reg_offset;
1001 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1002 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1003 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1004 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1005 int sifs, offset;
1006 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
1007
1008 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1009 return;
1010
1011 if (is_5ghz)
1012 sifs = 16;
1013 else
1014 sifs = 10;
1015
1016 if (ext_phy) {
1017 coverage_class = max_t(s16, dev->phy.coverage_class,
1018 coverage_class);
1019 } else {
1020 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev);
1021
1022 if (phy_ext)
1023 coverage_class = max_t(s16, phy_ext->coverage_class,
1024 coverage_class);
1025 }
1026 mt76_set(dev, MT_ARB_SCR(ext_phy),
1027 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1028 udelay(1);
1029
1030 offset = 3 * coverage_class;
1031 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1032 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1033
1034 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
1035 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
1036 mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
1037 FIELD_PREP(MT_IFS_EIFS, 360) |
1038 FIELD_PREP(MT_IFS_RIFS, 2) |
1039 FIELD_PREP(MT_IFS_SIFS, sifs) |
1040 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1041
1042 if (phy->slottime < 20 || is_5ghz)
1043 val = MT7915_CFEND_RATE_DEFAULT;
1044 else
1045 val = MT7915_CFEND_RATE_11B;
1046
1047 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
1048 mt76_clear(dev, MT_ARB_SCR(ext_phy),
1049 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1050}
1051
1052
1053
1054
1055
1056
1057static void
1058mt7915_phy_update_channel(struct mt76_phy *mphy, int idx)
1059{
1060 struct mt7915_dev *dev = container_of(mphy->dev, struct mt7915_dev, mt76);
1061 struct mt76_channel_state *state;
1062 u64 busy_time, tx_time, rx_time, obss_time;
1063
1064 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
1065 MT_MIB_SDR9_BUSY_MASK);
1066 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
1067 MT_MIB_SDR36_TXTIME_MASK);
1068 rx_time = mt76_get_field(dev, MT_MIB_SDR37(idx),
1069 MT_MIB_SDR37_RXTIME_MASK);
1070 obss_time = mt76_get_field(dev, MT_WF_RMAC_MIB_AIRTIME14(idx),
1071 MT_MIB_OBSSTIME_MASK);
1072
1073
1074 state = mphy->chan_state;
1075 state->cc_busy += busy_time;
1076 state->cc_tx += tx_time;
1077 state->cc_rx += rx_time + obss_time;
1078 state->cc_bss_rx += rx_time;
1079}
1080
1081void mt7915_update_channel(struct mt76_dev *mdev)
1082{
1083 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1084
1085 mt7915_phy_update_channel(&mdev->phy, 0);
1086 if (mdev->phy2)
1087 mt7915_phy_update_channel(mdev->phy2, 1);
1088
1089
1090 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
1091 if (mdev->phy2)
1092 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(1),
1093 MT_WF_RMAC_MIB_RXTIME_CLR);
1094}
1095
1096static bool
1097mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1098{
1099 bool ret;
1100
1101 ret = wait_event_timeout(dev->reset_wait,
1102 (READ_ONCE(dev->reset_state) & state),
1103 MT7915_RESET_TIMEOUT);
1104
1105 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1106 return ret;
1107}
1108
1109static void
1110mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1111{
1112 struct ieee80211_hw *hw = priv;
1113
1114 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon);
1115}
1116
1117static void
1118mt7915_update_beacons(struct mt7915_dev *dev)
1119{
1120 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1121 IEEE80211_IFACE_ITER_RESUME_ALL,
1122 mt7915_update_vif_beacon, dev->mt76.hw);
1123
1124 if (!dev->mt76.phy2)
1125 return;
1126
1127 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1128 IEEE80211_IFACE_ITER_RESUME_ALL,
1129 mt7915_update_vif_beacon, dev->mt76.phy2->hw);
1130}
1131
1132static void
1133mt7915_dma_reset(struct mt7915_dev *dev)
1134{
1135 int i;
1136
1137 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1138 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1139 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1140 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1141 usleep_range(1000, 2000);
1142
1143 for (i = 0; i < __MT_TXQ_MAX; i++)
1144 mt76_queue_tx_cleanup(dev, i, true);
1145
1146 mt76_for_each_q_rx(&dev->mt76, i) {
1147 mt76_queue_rx_reset(dev, i);
1148 }
1149
1150
1151 mt7915_dma_prefetch(dev);
1152
1153 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1154 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1155 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1156 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1157}
1158
1159
1160void mt7915_mac_reset_work(struct work_struct *work)
1161{
1162 struct mt7915_phy *phy2;
1163 struct mt76_phy *ext_phy;
1164 struct mt7915_dev *dev;
1165
1166 dev = container_of(work, struct mt7915_dev, reset_work);
1167 ext_phy = dev->mt76.phy2;
1168 phy2 = ext_phy ? ext_phy->priv : NULL;
1169
1170 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1171 return;
1172
1173 ieee80211_stop_queues(mt76_hw(dev));
1174 if (ext_phy)
1175 ieee80211_stop_queues(ext_phy->hw);
1176
1177 set_bit(MT76_RESET, &dev->mphy.state);
1178 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1179 wake_up(&dev->mt76.mcu.wait);
1180 cancel_delayed_work_sync(&dev->phy.mac_work);
1181 if (phy2)
1182 cancel_delayed_work_sync(&phy2->mac_work);
1183
1184
1185 mt76_txq_schedule_all(&dev->mphy);
1186 if (ext_phy)
1187 mt76_txq_schedule_all(ext_phy);
1188
1189 tasklet_disable(&dev->mt76.tx_tasklet);
1190 napi_disable(&dev->mt76.napi[0]);
1191 napi_disable(&dev->mt76.napi[1]);
1192 napi_disable(&dev->mt76.napi[2]);
1193 napi_disable(&dev->mt76.tx_napi);
1194
1195 mutex_lock(&dev->mt76.mutex);
1196
1197 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1198
1199 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1200 mt7915_dma_reset(dev);
1201
1202 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1203 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1204 }
1205
1206 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1207 clear_bit(MT76_RESET, &dev->mphy.state);
1208
1209 tasklet_enable(&dev->mt76.tx_tasklet);
1210 napi_enable(&dev->mt76.tx_napi);
1211 napi_schedule(&dev->mt76.tx_napi);
1212
1213 napi_enable(&dev->mt76.napi[0]);
1214 napi_schedule(&dev->mt76.napi[0]);
1215
1216 napi_enable(&dev->mt76.napi[1]);
1217 napi_schedule(&dev->mt76.napi[1]);
1218
1219 napi_enable(&dev->mt76.napi[2]);
1220 napi_schedule(&dev->mt76.napi[2]);
1221
1222 ieee80211_wake_queues(mt76_hw(dev));
1223 if (ext_phy)
1224 ieee80211_wake_queues(ext_phy->hw);
1225
1226 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1227 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1228
1229 mutex_unlock(&dev->mt76.mutex);
1230
1231 mt7915_update_beacons(dev);
1232
1233 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->phy.mac_work,
1234 MT7915_WATCHDOG_TIME);
1235 if (phy2)
1236 ieee80211_queue_delayed_work(ext_phy->hw, &phy2->mac_work,
1237 MT7915_WATCHDOG_TIME);
1238}
1239
1240static void
1241mt7915_mac_update_mib_stats(struct mt7915_phy *phy)
1242{
1243 struct mt7915_dev *dev = phy->dev;
1244 struct mib_stats *mib = &phy->mib;
1245 bool ext_phy = phy != &dev->phy;
1246 int i, aggr0, aggr1;
1247
1248 memset(mib, 0, sizeof(*mib));
1249
1250 mib->fcs_err_cnt = mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1251 MT_MIB_SDR3_FCS_ERR_MASK);
1252
1253 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1254 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
1255 u32 val, val2;
1256
1257 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1258
1259 val2 = FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1260 if (val2 > mib->ack_fail_cnt)
1261 mib->ack_fail_cnt = val2;
1262
1263 val2 = FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1264 if (val2 > mib->ba_miss_cnt)
1265 mib->ba_miss_cnt = val2;
1266
1267 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1268 val2 = FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1269 if (val2 > mib->rts_retries_cnt) {
1270 mib->rts_cnt = FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1271 mib->rts_retries_cnt = val2;
1272 }
1273
1274 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1275 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1276
1277 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
1278 dev->mt76.aggr_stats[aggr0++] += val >> 16;
1279 dev->mt76.aggr_stats[aggr1++] += val2 & 0xffff;
1280 dev->mt76.aggr_stats[aggr1++] += val2 >> 16;
1281 }
1282}
1283
1284void mt7915_mac_sta_stats_work(struct work_struct *work)
1285{
1286 struct ieee80211_sta *sta;
1287 struct ieee80211_vif *vif;
1288 struct mt7915_sta_stats *stats;
1289 struct mt7915_sta *msta;
1290 struct mt7915_dev *dev;
1291
1292 msta = container_of(work, struct mt7915_sta, stats_work);
1293 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
1294 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
1295 dev = msta->vif->dev;
1296 stats = &msta->stats;
1297
1298
1299 if (time_after(jiffies, stats->jiffies + HZ)) {
1300 mt7915_mcu_get_rate_info(dev, RATE_CTRL_RU_INFO,
1301 msta->wcid.idx);
1302
1303 stats->jiffies = jiffies;
1304 }
1305
1306 if (test_and_clear_bit(IEEE80211_RC_SUPP_RATES_CHANGED |
1307 IEEE80211_RC_NSS_CHANGED |
1308 IEEE80211_RC_BW_CHANGED, &stats->changed))
1309 mt7915_mcu_add_rate_ctrl(dev, vif, sta);
1310
1311 if (test_and_clear_bit(IEEE80211_RC_SMPS_CHANGED, &stats->changed))
1312 mt7915_mcu_add_smps(dev, vif, sta);
1313
1314 spin_lock_bh(&dev->sta_poll_lock);
1315 if (list_empty(&msta->poll_list))
1316 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1317 spin_unlock_bh(&dev->sta_poll_lock);
1318}
1319
1320void mt7915_mac_work(struct work_struct *work)
1321{
1322 struct mt7915_phy *phy;
1323 struct mt76_dev *mdev;
1324
1325 phy = (struct mt7915_phy *)container_of(work, struct mt7915_phy,
1326 mac_work.work);
1327 mdev = &phy->dev->mt76;
1328
1329 mutex_lock(&mdev->mutex);
1330
1331 mt76_update_survey(mdev);
1332 if (++phy->mac_work_count == 5) {
1333 phy->mac_work_count = 0;
1334
1335 mt7915_mac_update_mib_stats(phy);
1336 }
1337
1338 mutex_unlock(&mdev->mutex);
1339
1340 ieee80211_queue_delayed_work(phy->mt76->hw, &phy->mac_work,
1341 MT7915_WATCHDOG_TIME);
1342}
1343
1344static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
1345{
1346 struct mt7915_dev *dev = phy->dev;
1347
1348 if (phy->rdd_state & BIT(0))
1349 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1350 if (phy->rdd_state & BIT(1))
1351 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1352}
1353
1354static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
1355{
1356 int err;
1357
1358 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1359 if (err < 0)
1360 return err;
1361
1362 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1);
1363}
1364
1365static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
1366{
1367 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1368 struct mt7915_dev *dev = phy->dev;
1369 bool ext_phy = phy != &dev->phy;
1370 int err;
1371
1372
1373 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1374 if (err < 0)
1375 return err;
1376
1377 err = mt7915_dfs_start_rdd(dev, ext_phy);
1378 if (err < 0)
1379 return err;
1380
1381 phy->rdd_state |= BIT(ext_phy);
1382
1383 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1384 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1385 err = mt7915_dfs_start_rdd(dev, 1);
1386 if (err < 0)
1387 return err;
1388
1389 phy->rdd_state |= BIT(1);
1390 }
1391
1392 return 0;
1393}
1394
1395static int
1396mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
1397{
1398 const struct mt7915_dfs_radar_spec *radar_specs;
1399 struct mt7915_dev *dev = phy->dev;
1400 int err, i;
1401
1402 switch (dev->mt76.region) {
1403 case NL80211_DFS_FCC:
1404 radar_specs = &fcc_radar_specs;
1405 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
1406 if (err < 0)
1407 return err;
1408 break;
1409 case NL80211_DFS_ETSI:
1410 radar_specs = &etsi_radar_specs;
1411 break;
1412 case NL80211_DFS_JP:
1413 radar_specs = &jp_radar_specs;
1414 break;
1415 default:
1416 return -EINVAL;
1417 }
1418
1419 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1420 err = mt7915_mcu_set_radar_th(dev, i,
1421 &radar_specs->radar_pattern[i]);
1422 if (err < 0)
1423 return err;
1424 }
1425
1426 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1427}
1428
1429int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
1430{
1431 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1432 struct mt7915_dev *dev = phy->dev;
1433 bool ext_phy = phy != &dev->phy;
1434 int err;
1435
1436 if (dev->mt76.region == NL80211_DFS_UNSET) {
1437 phy->dfs_state = -1;
1438 if (phy->rdd_state)
1439 goto stop;
1440
1441 return 0;
1442 }
1443
1444 if (test_bit(MT76_SCANNING, &phy->mt76->state))
1445 return 0;
1446
1447 if (phy->dfs_state == chandef->chan->dfs_state)
1448 return 0;
1449
1450 err = mt7915_dfs_init_radar_specs(phy);
1451 if (err < 0) {
1452 phy->dfs_state = -1;
1453 goto stop;
1454 }
1455
1456 phy->dfs_state = chandef->chan->dfs_state;
1457
1458 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1459 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1460 return mt7915_dfs_start_radar_detector(phy);
1461
1462 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
1463 MT_RX_SEL0, 0);
1464 }
1465
1466stop:
1467 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy,
1468 MT_RX_SEL0, 0);
1469 if (err < 0)
1470 return err;
1471
1472 mt7915_dfs_stop_radar_detector(phy);
1473 return 0;
1474}
1475
