1
2
3
4#ifndef __MT7915_REGS_H
5#define __MT7915_REGS_H
6
7
8#define MT_MCU_WFDMA1_BASE 0x3000
9#define MT_MCU_WFDMA1(ofs) (MT_MCU_WFDMA1_BASE + (ofs))
10
11#define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12#define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
13#define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
14#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
15#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
16
17#define MT_PLE_BASE 0x8000
18#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
19
20#define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
21#define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
22#define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
23#define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
24
25#define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
26 ((n) << 2))
27#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
28
29#define MT_MDP_BASE 0xf000
30#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
31
32#define MT_MDP_DCR0 MT_MDP(0x000)
33#define MT_MDP_DCR0_DAMSDU_EN BIT(15)
34
35#define MT_MDP_DCR1 MT_MDP(0x004)
36#define MT_MDP_DCR1_MAX_RX_LEN GENMASK(15, 3)
37
38#define MT_MDP_BNRCFR0(_band) MT_MDP(0x070 + ((_band) << 8))
39#define MT_MDP_RCFR0_MCU_RX_MGMT GENMASK(5, 4)
40#define MT_MDP_RCFR0_MCU_RX_CTL_NON_BAR GENMASK(7, 6)
41#define MT_MDP_RCFR0_MCU_RX_CTL_BAR GENMASK(9, 8)
42
43#define MT_MDP_BNRCFR1(_band) MT_MDP(0x074 + ((_band) << 8))
44#define MT_MDP_RCFR1_MCU_RX_BYPASS GENMASK(23, 22)
45#define MT_MDP_RCFR1_RX_DROPPED_UCAST GENMASK(28, 27)
46#define MT_MDP_RCFR1_RX_DROPPED_MCAST GENMASK(30, 29)
47#define MT_MDP_TO_HIF 0
48#define MT_MDP_TO_WM 1
49
50
51#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
52#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
53
54#define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
55#define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
56#define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
57#define MT_TIMEOUT_VAL_CCA GENMASK(31, 16)
58
59#define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
60#define MT_IFS_EIFS GENMASK(8, 0)
61#define MT_IFS_RIFS GENMASK(14, 10)
62#define MT_IFS_SIFS GENMASK(22, 16)
63#define MT_IFS_SLOT GENMASK(30, 24)
64
65#define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
66#define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
67#define MT_TMAC_CTCR0_INS_DDLMT_EN BIT(17)
68#define MT_TMAC_CTCR0_INS_DDLMT_VHT_SMPDU_EN BIT(18)
69
70
71#define MT_WF_DMA_BASE 0x21e00
72#define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs))
73
74#define MT_DMA_DCR0 MT_WF_DMA(0x000)
75#define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 3)
76#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
77
78
79#define MT_WF_ETBF_BASE(_band) ((_band) ? 0xa4000 : 0x24000)
80#define MT_WF_ETBF(_band, ofs) (MT_WF_ETBF_BASE(_band) + (ofs))
81
82#define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
83#define MT_ETBF_TX_FB_CPL GENMASK(31, 16)
84#define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
85
86#define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
87#define MT_ETBF_TX_IBF_CNT GENMASK(31, 16)
88#define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
89
90#define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8)
91#define MT_ETBF_RX_FB_ALL GENMASK(31, 24)
92#define MT_ETBF_RX_FB_HE GENMASK(23, 16)
93#define MT_ETBF_RX_FB_VHT GENMASK(15, 8)
94#define MT_ETBF_RX_FB_HT GENMASK(7, 0)
95
96
97#define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200)
98#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
99
100#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
101#define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
102
103#define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
104#define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
105#define MT_LPON_TCR_SW_WRITE BIT(0)
106
107
108#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
109#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
110
111#define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x014)
112#define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
113
114#define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
115#define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
116
117#define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
118#define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
119
120#define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
121#define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
122
123#define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x098)
124#define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
125#define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x09c)
126#define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
127
128#define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
129#define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
130#define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
131
132#define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
133#define MT_MIB_RTS_RETRIES_COUNT_MASK GENMASK(31, 16)
134#define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
135
136#define MT_MIB_MB_SDR1(_band, n) MT_WF_MIB(_band, 0x104 + ((n) << 4))
137#define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
138#define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(31, 16)
139
140#define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
141#define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
142
143#define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x0a8 + ((n) << 2))
144#define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x164 + ((n) << 2))
145#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
146#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
147
148#define MT_WTBLON_TOP_BASE 0x34000
149#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
150#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
151#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
152
153#define MT_WTBL_UPDATE MT_WTBLON_TOP(0x030)
154#define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
155#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
156#define MT_WTBL_UPDATE_BUSY BIT(31)
157
158#define MT_WTBL_BASE 0x38000
159#define MT_WTBL_LMAC_ID GENMASK(14, 8)
160#define MT_WTBL_LMAC_DW GENMASK(7, 2)
161#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
162 FIELD_PREP(MT_WTBL_LMAC_ID, _id) | \
163 FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
164
165
166#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
167#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
168
169#define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
170#define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
171#define MT_AGG_ACR_BAR_RATE GENMASK(29, 16)
172
173
174#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
175#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
176
177#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
178#define MT_ARB_SCR_TX_DISABLE BIT(8)
179#define MT_ARB_SCR_RX_DISABLE BIT(9)
180
181
182#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
183#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
184
185#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
186#define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
187#define MT_WF_RFCR_DROP_FCSFAIL BIT(1)
188#define MT_WF_RFCR_DROP_VERSION BIT(3)
189#define MT_WF_RFCR_DROP_PROBEREQ BIT(4)
190#define MT_WF_RFCR_DROP_MCAST BIT(5)
191#define MT_WF_RFCR_DROP_BCAST BIT(6)
192#define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7)
193#define MT_WF_RFCR_DROP_A3_MAC BIT(8)
194#define MT_WF_RFCR_DROP_A3_BSSID BIT(9)
195#define MT_WF_RFCR_DROP_A2_BSSID BIT(10)
196#define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11)
197#define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12)
198#define MT_WF_RFCR_DROP_CTL_RSV BIT(13)
199#define MT_WF_RFCR_DROP_CTS BIT(14)
200#define MT_WF_RFCR_DROP_RTS BIT(15)
201#define MT_WF_RFCR_DROP_DUPLICATE BIT(16)
202#define MT_WF_RFCR_DROP_OTHER_BSS BIT(17)
203#define MT_WF_RFCR_DROP_OTHER_UC BIT(18)
204#define MT_WF_RFCR_DROP_OTHER_TIM BIT(19)
205#define MT_WF_RFCR_DROP_NDPA BIT(20)
206#define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21)
207
208#define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
209#define MT_WF_RFCR1_DROP_ACK BIT(4)
210#define MT_WF_RFCR1_DROP_BF_POLL BIT(5)
211#define MT_WF_RFCR1_DROP_BA BIT(6)
212#define MT_WF_RFCR1_DROP_CFEND BIT(7)
213#define MT_WF_RFCR1_DROP_CFACK BIT(8)
214
215#define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4)
216#define MT_WF_RMAC_MIB_RXTIME_CLR BIT(31)
217#define MT_WF_RMAC_MIB_RXTIME_EN BIT(30)
218
219#define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8)
220#define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
221#define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
222
223
224#define MT_WFDMA0_BASE 0xd4000
225#define MT_WFDMA0(ofs) (MT_WFDMA0_BASE + (ofs))
226
227#define MT_WFDMA0_RST MT_WFDMA0(0x100)
228#define MT_WFDMA0_RST_LOGIC_RST BIT(4)
229#define MT_WFDMA0_RST_DMASHDL_ALL_RST BIT(5)
230
231#define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
232#define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
233#define MT_WFDMA0_BUSY_ENA_TX_FIFO1 BIT(1)
234#define MT_WFDMA0_BUSY_ENA_RX_FIFO BIT(2)
235
236#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
237#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
238#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
239
240#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
241#define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
242
243#define MT_RX_DATA_RING_BASE MT_WFDMA0(0x500)
244
245#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
246#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
247#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
248
249
250#define MT_WFDMA1_BASE 0xd5000
251#define MT_WFDMA1(ofs) (MT_WFDMA1_BASE + (ofs))
252
253#define MT_WFDMA1_RST MT_WFDMA1(0x100)
254#define MT_WFDMA1_RST_LOGIC_RST BIT(4)
255#define MT_WFDMA1_RST_DMASHDL_ALL_RST BIT(5)
256
257#define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
258#define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
259#define MT_WFDMA1_BUSY_ENA_TX_FIFO1 BIT(1)
260#define MT_WFDMA1_BUSY_ENA_RX_FIFO BIT(2)
261
262#define MT_MCU_CMD MT_WFDMA1(0x1f0)
263#define MT_MCU_CMD_STOP_DMA_FW_RELOAD BIT(1)
264#define MT_MCU_CMD_STOP_DMA BIT(2)
265#define MT_MCU_CMD_RESET_DONE BIT(3)
266#define MT_MCU_CMD_RECOVERY_DONE BIT(4)
267#define MT_MCU_CMD_NORMAL_STATE BIT(5)
268#define MT_MCU_CMD_ERROR_MASK GENMASK(5, 1)
269
270#define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
271#define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
272#define MT_WFDMA1_GLO_CFG_RX_DMA_EN BIT(2)
273#define MT_WFDMA1_GLO_CFG_OMIT_TX_INFO BIT(28)
274#define MT_WFDMA1_GLO_CFG_OMIT_RX_INFO BIT(27)
275
276#define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
277#define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
278
279#define MT_TX_RING_BASE MT_WFDMA1(0x300)
280#define MT_RX_EVENT_RING_BASE MT_WFDMA1(0x500)
281
282#define MT_WFDMA1_TX_RING0_EXT_CTRL MT_WFDMA1(0x600)
283#define MT_WFDMA1_TX_RING1_EXT_CTRL MT_WFDMA1(0x604)
284#define MT_WFDMA1_TX_RING2_EXT_CTRL MT_WFDMA1(0x608)
285#define MT_WFDMA1_TX_RING3_EXT_CTRL MT_WFDMA1(0x60c)
286#define MT_WFDMA1_TX_RING4_EXT_CTRL MT_WFDMA1(0x610)
287#define MT_WFDMA1_TX_RING5_EXT_CTRL MT_WFDMA1(0x614)
288#define MT_WFDMA1_TX_RING6_EXT_CTRL MT_WFDMA1(0x618)
289#define MT_WFDMA1_TX_RING7_EXT_CTRL MT_WFDMA1(0x61c)
290
291#define MT_WFDMA1_TX_RING16_EXT_CTRL MT_WFDMA1(0x640)
292#define MT_WFDMA1_TX_RING17_EXT_CTRL MT_WFDMA1(0x644)
293#define MT_WFDMA1_TX_RING18_EXT_CTRL MT_WFDMA1(0x648)
294#define MT_WFDMA1_TX_RING19_EXT_CTRL MT_WFDMA1(0x64c)
295#define MT_WFDMA1_TX_RING20_EXT_CTRL MT_WFDMA1(0x650)
296#define MT_WFDMA1_TX_RING21_EXT_CTRL MT_WFDMA1(0x654)
297#define MT_WFDMA1_TX_RING22_EXT_CTRL MT_WFDMA1(0x658)
298#define MT_WFDMA1_TX_RING23_EXT_CTRL MT_WFDMA1(0x65c)
299
300#define MT_WFDMA1_RX_RING0_EXT_CTRL MT_WFDMA1(0x680)
301#define MT_WFDMA1_RX_RING1_EXT_CTRL MT_WFDMA1(0x684)
302#define MT_WFDMA1_RX_RING2_EXT_CTRL MT_WFDMA1(0x688)
303#define MT_WFDMA1_RX_RING3_EXT_CTRL MT_WFDMA1(0x68c)
304
305
306#define MT_WFDMA_EXT_CSR_BASE 0xd7000
307#define MT_WFDMA_EXT_CSR(ofs) (MT_WFDMA_EXT_CSR_BASE + (ofs))
308
309#define MT_INT_SOURCE_CSR MT_WFDMA_EXT_CSR(0x10)
310#define MT_INT_MASK_CSR MT_WFDMA_EXT_CSR(0x14)
311#define MT_INT_RX_DONE_DATA BIT(16)
312#define MT_INT_RX_DONE_WM BIT(0)
313#define MT_INT_RX_DONE_WA BIT(1)
314#define MT_INT_RX_DONE(_n) ((_n) ? BIT((_n) - 1) : BIT(16))
315#define MT_INT_RX_DONE_ALL (BIT(0) | BIT(1) | BIT(16))
316#define MT_INT_TX_DONE_ALL (BIT(15) | GENMASK(27, 26) | BIT(30))
317#define MT_INT_MCU_CMD BIT(29)
318
319#define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
320#define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
321
322
323#define MT_WFDMA0_PCIE1_BASE 0xd8000
324#define MT_WFDMA0_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
325
326#define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
327#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
328#define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
329#define MT_WFDMA0_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
330
331
332#define MT_WFDMA1_PCIE1_BASE 0xd9000
333#define MT_WFDMA1_PCIE1(ofs) (MT_WFDMA0_PCIE1_BASE + (ofs))
334
335#define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
336#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
337#define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO1 BIT(1)
338#define MT_WFDMA1_PCIE1_BUSY_ENA_RX_FIFO BIT(2)
339
340#define MT_INFRA_CFG_BASE 0xf1000
341#define MT_INFRA(ofs) (MT_INFRA_CFG_BASE + (ofs))
342
343#define MT_HIF_REMAP_L1 MT_INFRA(0x1ac)
344#define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
345#define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
346#define MT_HIF_REMAP_L1_BASE GENMASK(31, 16)
347#define MT_HIF_REMAP_BASE_L1 0xe0000
348
349#define MT_HIF_REMAP_L2 MT_INFRA(0x1b0)
350#define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
351#define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
352#define MT_HIF_REMAP_L2_BASE GENMASK(31, 12)
353#define MT_HIF_REMAP_BASE_L2 0x00000
354
355#define MT_TOP_BASE 0x18060000
356#define MT_TOP(ofs) (MT_TOP_BASE + (ofs))
357
358#define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
359#define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
360#define MT_TOP_LPCR_HOST_DRV_OWN BIT(1)
361
362#define MT_TOP_MISC MT_TOP(0xf0)
363#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
364
365#define MT_HW_BOUND 0x70010020
366#define MT_HW_CHIPID 0x70010200
367#define MT_HW_REV 0x70010204
368
369#define MT_PCIE_MAC_BASE 0x74030000
370#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
371#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
372
373
374#define MT_WF_PHY_BASE 0x83080000
375#define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs))
376
377#define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
378#define MT_WF_PHY_RX_CTRL1_STSCNT_EN GENMASK(11, 9)
379
380#endif
381
