1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#ifndef __RTL92C_REG_H__ 5#define __RTL92C_REG_H__ 6 7#define REG_SYS_ISO_CTRL 0x0000 8#define REG_SYS_FUNC_EN 0x0002 9#define REG_APS_FSMCO 0x0004 10#define REG_SYS_CLKR 0x0008 11#define REG_9346CR 0x000A 12#define REG_EE_VPD 0x000C 13#define REG_AFE_MISC 0x0010 14#define REG_SPS0_CTRL 0x0011 15#define REG_SPS_OCP_CFG 0x0018 16#define REG_RSV_CTRL 0x001C 17#define REG_RF_CTRL 0x001F 18#define REG_LDOA15_CTRL 0x0020 19#define REG_LDOV12D_CTRL 0x0021 20#define REG_LDOHCI12_CTRL 0x0022 21#define REG_LPLDO_CTRL 0x0023 22#define REG_AFE_XTAL_CTRL 0x0024 23#define REG_AFE_PLL_CTRL 0x0028 24#define REG_EFUSE_CTRL 0x0030 25#define REG_EFUSE_TEST 0x0034 26#define REG_PWR_DATA 0x0038 27#define REG_CAL_TIMER 0x003C 28#define REG_ACLK_MON 0x003E 29#define REG_GPIO_MUXCFG 0x0040 30#define REG_GPIO_IO_SEL 0x0042 31#define REG_MAC_PINMUX_CFG 0x0043 32#define REG_GPIO_PIN_CTRL 0x0044 33#define REG_GPIO_INTM 0x0048 34#define REG_LEDCFG0 0x004C 35#define REG_LEDCFG1 0x004D 36#define REG_LEDCFG2 0x004E 37#define REG_LEDCFG3 0x004F 38#define REG_FSIMR 0x0050 39#define REG_FSISR 0x0054 40#define REG_HSIMR 0x0058 41#define REG_HSISR 0x005c 42 43/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 44#define REG_GPIO_PIN_CTRL_2 0x0060 45/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 46#define REG_GPIO_IO_SEL_2 0x0062 47/* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 48#define REG_MULTI_FUNC_CTRL 0x0068 49 50#define REG_MCUFWDL 0x0080 51 52#define REG_HMEBOX_EXT_0 0x0088 53#define REG_HMEBOX_EXT_1 0x008A 54#define REG_HMEBOX_EXT_2 0x008C 55#define REG_HMEBOX_EXT_3 0x008E 56 57#define REG_BIST_SCAN 0x00D0 58#define REG_BIST_RPT 0x00D4 59#define REG_BIST_ROM_RPT 0x00D8 60#define REG_USB_SIE_INTF 0x00E0 61#define REG_PCIE_MIO_INTF 0x00E4 62#define REG_PCIE_MIO_INTD 0x00E8 63#define REG_HPON_FSM 0x00EC 64#define REG_SYS_CFG 0x00F0 65#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/ 66 67#define REG_CR 0x0100 68#define REG_PBP 0x0104 69#define REG_TRXDMA_CTRL 0x010C 70#define REG_TRXFF_BNDY 0x0114 71#define REG_TRXFF_STATUS 0x0118 72#define REG_RXFF_PTR 0x011C 73#define REG_HIMR 0x0120 74#define REG_HISR 0x0124 75#define REG_HIMRE 0x0128 76#define REG_HISRE 0x012C 77#define REG_CPWM 0x012F 78#define REG_FWIMR 0x0130 79#define REG_FWISR 0x0134 80#define REG_PKTBUF_DBG_CTRL 0x0140 81#define REG_PKTBUF_DBG_DATA_L 0x0144 82#define REG_PKTBUF_DBG_DATA_H 0x0148 83 84#define REG_TC0_CTRL 0x0150 85#define REG_TC1_CTRL 0x0154 86#define REG_TC2_CTRL 0x0158 87#define REG_TC3_CTRL 0x015C 88#define REG_TC4_CTRL 0x0160 89#define REG_TCUNIT_BASE 0x0164 90#define REG_MBIST_START 0x0174 91#define REG_MBIST_DONE 0x0178 92#define REG_MBIST_FAIL 0x017C 93#define REG_C2HEVT_MSG_NORMAL 0x01A0 94#define REG_C2HEVT_MSG_TEST 0x01B8 95#define REG_C2HEVT_CLEAR 0x01BF 96#define REG_MCUTST_1 0x01c0 97#define REG_FMETHR 0x01C8 98#define REG_HMETFR 0x01CC 99#define REG_HMEBOX_0 0x01D0 100#define REG_HMEBOX_1 0x01D4 101#define REG_HMEBOX_2 0x01D8 102#define REG_HMEBOX_3 0x01DC 103 104#define REG_LLT_INIT 0x01E0 105#define REG_BB_ACCEESS_CTRL 0x01E8 106#define REG_BB_ACCESS_DATA 0x01EC 107 108#define REG_RQPN 0x0200 109#define REG_FIFOPAGE 0x0204 110#define REG_TDECTRL 0x0208 111#define REG_TXDMA_OFFSET_CHK 0x020C 112#define REG_TXDMA_STATUS 0x0210 113#define REG_RQPN_NPQ 0x0214 114 115#define REG_RXDMA_AGG_PG_TH 0x0280 116#define REG_RXPKT_NUM 0x0284 117#define REG_RXDMA_STATUS 0x0288 118 119#define REG_PCIE_CTRL_REG 0x0300 120#define REG_INT_MIG 0x0304 121#define REG_BCNQ_DESA 0x0308 122#define REG_HQ_DESA 0x0310 123#define REG_MGQ_DESA 0x0318 124#define REG_VOQ_DESA 0x0320 125#define REG_VIQ_DESA 0x0328 126#define REG_BEQ_DESA 0x0330 127#define REG_BKQ_DESA 0x0338 128#define REG_RX_DESA 0x0340 129#define REG_DBI 0x0348 130#define REG_MDIO 0x0354 131#define REG_DBG_SEL 0x0360 132#define REG_PCIE_HRPWM 0x0361 133#define REG_PCIE_HCPWM 0x0363 134#define REG_UART_CTRL 0x0364 135#define REG_UART_TX_DESA 0x0370 136#define REG_UART_RX_DESA 0x0378 137 138#define REG_HDAQ_DESA_NODEF 0x0000 139#define REG_CMDQ_DESA_NODEF 0x0000 140 141#define REG_VOQ_INFORMATION 0x0400 142#define REG_VIQ_INFORMATION 0x0404 143#define REG_BEQ_INFORMATION 0x0408 144#define REG_BKQ_INFORMATION 0x040C 145#define REG_MGQ_INFORMATION 0x0410 146#define REG_HGQ_INFORMATION 0x0414 147#define REG_BCNQ_INFORMATION 0x0418 148 149#define REG_CPU_MGQ_INFORMATION 0x041C 150#define REG_FWHW_TXQ_CTRL 0x0420 151#define REG_HWSEQ_CTRL 0x0423 152#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 153#define REG_TXPKTBUF_MGQ_BDNY 0x0425 154#define REG_MULTI_BCNQ_EN 0x0426 155#define REG_MULTI_BCNQ_OFFSET 0x0427 156#define REG_SPEC_SIFS 0x0428 157#define REG_RL 0x042A 158#define REG_DARFRC 0x0430 159#define REG_RARFRC 0x0438 160#define REG_RRSR 0x0440 161#define REG_ARFR0 0x0444 162#define REG_ARFR1 0x0448 163#define REG_ARFR2 0x044C 164#define REG_ARFR3 0x0450 165#define REG_AGGLEN_LMT 0x0458 166#define REG_AMPDU_MIN_SPACE 0x045C 167#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 168#define REG_FAST_EDCA_CTRL 0x0460 169#define REG_RD_RESP_PKT_TH 0x0463 170#define REG_INIRTS_RATE_SEL 0x0480 171#define REG_INIDATA_RATE_SEL 0x0484 172#define REG_POWER_STATUS 0x04A4 173#define REG_POWER_STAGE1 0x04B4 174#define REG_POWER_STAGE2 0x04B8 175#define REG_PKT_LIFE_TIME 0x04C0 176#define REG_STBC_SETTING 0x04C4 177#define REG_PROT_MODE_CTRL 0x04C8 178#define REG_BAR_MODE_CTRL 0x04CC 179#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 180#define REG_NQOS_SEQ 0x04DC 181#define REG_QOS_SEQ 0x04DE 182#define REG_NEED_CPU_HANDLE 0x04E0 183#define REG_PKT_LOSE_RPT 0x04E1 184#define REG_PTCL_ERR_STATUS 0x04E2 185#define REG_DUMMY 0x04FC 186 187#define REG_EDCA_VO_PARAM 0x0500 188#define REG_EDCA_VI_PARAM 0x0504 189#define REG_EDCA_BE_PARAM 0x0508 190#define REG_EDCA_BK_PARAM 0x050C 191#define REG_BCNTCFG 0x0510 192#define REG_PIFS 0x0512 193#define REG_RDG_PIFS 0x0513 194#define REG_SIFS_CTX 0x0514 195#define REG_SIFS_TRX 0x0516 196#define REG_SIFS_CCK 0x0514 197#define REG_SIFS_OFDM 0x0516 198#define REG_AGGR_BREAK_TIME 0x051A 199#define REG_SLOT 0x051B 200#define REG_TX_PTCL_CTRL 0x0520 201#define REG_TXPAUSE 0x0522 202#define REG_DIS_TXREQ_CLR 0x0523 203#define REG_RD_CTRL 0x0524 204#define REG_TBTT_PROHIBIT 0x0540 205#define REG_RD_NAV_NXT 0x0544 206#define REG_NAV_PROT_LEN 0x0546 207#define REG_BCN_CTRL 0x0550 208#define REG_MBID_NUM 0x0552 209#define REG_DUAL_TSF_RST 0x0553 210#define REG_BCN_INTERVAL 0x0554 211#define REG_MBSSID_BCN_SPACE 0x0554 212#define REG_DRVERLYINT 0x0558 213#define REG_BCNDMATIM 0x0559 214#define REG_ATIMWND 0x055A 215#define REG_USTIME_TSF 0x055C 216#define REG_BCN_MAX_ERR 0x055D 217#define REG_RXTSF_OFFSET_CCK 0x055E 218#define REG_RXTSF_OFFSET_OFDM 0x055F 219#define REG_TSFTR 0x0560 220#define REG_INIT_TSFTR 0x0564 221#define REG_PSTIMER 0x0580 222#define REG_TIMER0 0x0584 223#define REG_TIMER1 0x0588 224#define REG_ACMHWCTRL 0x05C0 225#define REG_ACMRSTCTRL 0x05C1 226#define REG_ACMAVG 0x05C2 227#define REG_VO_ADMTIME 0x05C4 228#define REG_VI_ADMTIME 0x05C6 229#define REG_BE_ADMTIME 0x05C8 230#define REG_EDCA_RANDOM_GEN 0x05CC 231#define REG_SCH_TXCMD 0x05D0 232 233#define REG_APSD_CTRL 0x0600 234#define REG_BWOPMODE 0x0603 235#define REG_TCR 0x0604 236#define REG_RCR 0x0608 237#define REG_RX_PKT_LIMIT 0x060C 238#define REG_RX_DLK_TIME 0x060D 239#define REG_RX_DRVINFO_SZ 0x060F 240 241#define REG_MACID 0x0610 242#define REG_BSSID 0x0618 243#define REG_MAR 0x0620 244#define REG_MBIDCAMCFG 0x0628 245 246#define REG_USTIME_EDCA 0x0638 247#define REG_MAC_SPEC_SIFS 0x063A 248#define REG_RESP_SIFS_CCK 0x063C 249#define REG_RESP_SIFS_OFDM 0x063E 250/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 251#define REG_R2T_SIFS 0x063C 252/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 253#define REG_T2T_SIFS 0x063E 254#define REG_ACKTO 0x0640 255#define REG_CTS2TO 0x0641 256#define REG_EIFS 0x0642 257 258#define REG_NAV_CTRL 0x0650 259#define REG_BACAMCMD 0x0654 260#define REG_BACAMCONTENT 0x0658 261#define REG_LBDLY 0x0660 262#define REG_FWDLY 0x0661 263#define REG_RXERR_RPT 0x0664 264#define REG_WMAC_TRXPTCL_CTL 0x0668 265 266#define REG_CAMCMD 0x0670 267#define REG_CAMWRITE 0x0674 268#define REG_CAMREAD 0x0678 269#define REG_CAMDBG 0x067C 270#define REG_SECCFG 0x0680 271 272#define REG_WOW_CTRL 0x0690 273#define REG_PSSTATUS 0x0691 274#define REG_PS_RX_INFO 0x0692 275#define REG_LPNAV_CTRL 0x0694 276#define REG_WKFMCAM_CMD 0x0698 277#define REG_WKFMCAM_RWD 0x069C 278#define REG_RXFLTMAP0 0x06A0 279#define REG_RXFLTMAP1 0x06A2 280#define REG_RXFLTMAP2 0x06A4 281#define REG_BCN_PSR_RPT 0x06A8 282#define REG_CALB32K_CTRL 0x06AC 283#define REG_PKT_MON_CTRL 0x06B4 284#define REG_BT_COEX_TABLE 0x06C0 285#define REG_WMAC_RESP_TXINFO 0x06D8 286 287#define REG_USB_INFO 0xFE17 288#define REG_USB_SPECIAL_OPTION 0xFE55 289#define REG_USB_DMA_AGG_TO 0xFE5B 290#define REG_USB_AGG_TO 0xFE5C 291#define REG_USB_AGG_TH 0xFE5D 292 293#define REG_TEST_USB_TXQS 0xFE48 294#define REG_TEST_SIE_VID 0xFE60 295#define REG_TEST_SIE_PID 0xFE62 296#define REG_TEST_SIE_OPTIONAL 0xFE64 297#define REG_TEST_SIE_CHIRP_K 0xFE65 298#define REG_TEST_SIE_PHY 0xFE66 299#define REG_TEST_SIE_MAC_ADDR 0xFE70 300#define REG_TEST_SIE_STRING 0xFE80 301 302#define REG_NORMAL_SIE_VID 0xFE60 303#define REG_NORMAL_SIE_PID 0xFE62 304#define REG_NORMAL_SIE_OPTIONAL 0xFE64 305#define REG_NORMAL_SIE_EP 0xFE65 306#define REG_NORMAL_SIE_PHY 0xFE68 307#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 308#define REG_NORMAL_SIE_STRING 0xFE80 309 310#define CR9346 REG_9346CR 311#define MSR (REG_CR + 2) 312#define ISR REG_HISR 313#define TSFR REG_TSFTR 314 315#define MACIDR0 REG_MACID 316#define MACIDR4 (REG_MACID + 4) 317 318#define PBP REG_PBP 319 320#define IDR0 MACIDR0 321#define IDR4 MACIDR4 322 323#define UNUSED_REGISTER 0x1BF 324#define DCAM UNUSED_REGISTER 325#define PSR UNUSED_REGISTER 326#define BBADDR UNUSED_REGISTER 327#define PHYDATAR UNUSED_REGISTER 328 329#define INVALID_BBRF_VALUE 0x12345678 330 331#define MAX_MSS_DENSITY_2T 0x13 332#define MAX_MSS_DENSITY_1T 0x0A 333 334#define CMDEEPROM_EN BIT(5) 335#define CMDEEPROM_SEL BIT(4) 336#define CMD9346CR_9356SEL BIT(4) 337#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 338#define AUTOLOAD_EFUSE CMDEEPROM_EN 339 340#define GPIOSEL_GPIO 0 341#define GPIOSEL_ENBT BIT(5) 342 343#define GPIO_IN REG_GPIO_PIN_CTRL 344#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 345#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 346#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 347 348#define MSR_NOLINK 0x00 349#define MSR_ADHOC 0x01 350#define MSR_INFRA 0x02 351#define MSR_AP 0x03 352#define MSR_MASK 0x03 353 354#define RRSR_RSC_OFFSET 21 355#define RRSR_SHORT_OFFSET 23 356#define RRSR_RSC_BW_40M 0x600000 357#define RRSR_RSC_UPSUBCHNL 0x400000 358#define RRSR_RSC_LOWSUBCHNL 0x200000 359#define RRSR_SHORT 0x800000 360#define RRSR_1M BIT(0) 361#define RRSR_2M BIT(1) 362#define RRSR_5_5M BIT(2) 363#define RRSR_11M BIT(3) 364#define RRSR_6M BIT(4) 365#define RRSR_9M BIT(5) 366#define RRSR_12M BIT(6) 367#define RRSR_18M BIT(7) 368#define RRSR_24M BIT(8) 369#define RRSR_36M BIT(9) 370#define RRSR_48M BIT(10) 371#define RRSR_54M BIT(11) 372#define RRSR_MCS0 BIT(12) 373#define RRSR_MCS1 BIT(13) 374#define RRSR_MCS2 BIT(14) 375#define RRSR_MCS3 BIT(15) 376#define RRSR_MCS4 BIT(16) 377#define RRSR_MCS5 BIT(17) 378#define RRSR_MCS6 BIT(18) 379#define RRSR_MCS7 BIT(19) 380#define BRSR_ACKSHORTPMB BIT(23) 381 382#define RATR_1M 0x00000001 383#define RATR_2M 0x00000002 384#define RATR_55M 0x00000004 385#define RATR_11M 0x00000008 386#define RATR_6M 0x00000010 387#define RATR_9M 0x00000020 388#define RATR_12M 0x00000040 389#define RATR_18M 0x00000080 390#define RATR_24M 0x00000100 391#define RATR_36M 0x00000200 392#define RATR_48M 0x00000400 393#define RATR_54M 0x00000800 394#define RATR_MCS0 0x00001000 395#define RATR_MCS1 0x00002000 396#define RATR_MCS2 0x00004000 397#define RATR_MCS3 0x00008000 398#define RATR_MCS4 0x00010000 399#define RATR_MCS5 0x00020000 400#define RATR_MCS6 0x00040000 401#define RATR_MCS7 0x00080000 402#define RATR_MCS8 0x00100000 403#define RATR_MCS9 0x00200000 404#define RATR_MCS10 0x00400000 405#define RATR_MCS11 0x00800000 406#define RATR_MCS12 0x01000000 407#define RATR_MCS13 0x02000000 408#define RATR_MCS14 0x04000000 409#define RATR_MCS15 0x08000000 410 411#define RATE_1M BIT(0) 412#define RATE_2M BIT(1) 413#define RATE_5_5M BIT(2) 414#define RATE_11M BIT(3) 415#define RATE_6M BIT(4) 416#define RATE_9M BIT(5) 417#define RATE_12M BIT(6) 418#define RATE_18M BIT(7) 419#define RATE_24M BIT(8) 420#define RATE_36M BIT(9) 421#define RATE_48M BIT(10) 422#define RATE_54M BIT(11) 423#define RATE_MCS0 BIT(12) 424#define RATE_MCS1 BIT(13) 425#define RATE_MCS2 BIT(14) 426#define RATE_MCS3 BIT(15) 427#define RATE_MCS4 BIT(16) 428#define RATE_MCS5 BIT(17) 429#define RATE_MCS6 BIT(18) 430#define RATE_MCS7 BIT(19) 431#define RATE_MCS8 BIT(20) 432#define RATE_MCS9 BIT(21) 433#define RATE_MCS10 BIT(22) 434#define RATE_MCS11 BIT(23) 435#define RATE_MCS12 BIT(24) 436#define RATE_MCS13 BIT(25) 437#define RATE_MCS14 BIT(26) 438#define RATE_MCS15 BIT(27) 439 440#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 441#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \ 442 | RATR_24M | RATR_36M | RATR_48M | RATR_54M) 443#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 444 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 445 RATR_MCS6 | RATR_MCS7) 446#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 447 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 448 RATR_MCS14 | RATR_MCS15) 449 450#define BW_OPMODE_20MHZ BIT(2) 451#define BW_OPMODE_5G BIT(1) 452#define BW_OPMODE_11J BIT(0) 453 454#define CAM_VALID BIT(15) 455#define CAM_NOTVALID 0x0000 456#define CAM_USEDK BIT(5) 457 458#define CAM_NONE 0x0 459#define CAM_WEP40 0x01 460#define CAM_TKIP 0x02 461#define CAM_AES 0x04 462#define CAM_WEP104 0x05 463 464#define TOTAL_CAM_ENTRY 32 465#define HALF_CAM_ENTRY 16 466 467#define CAM_WRITE BIT(16) 468#define CAM_READ 0x00000000 469#define CAM_POLLINIG BIT(31) 470 471#define SCR_USEDK 0x01 472#define SCR_TXSEC_ENABLE 0x02 473#define SCR_RXSEC_ENABLE 0x04 474 475#define WOW_PMEN BIT(0) 476#define WOW_WOMEN BIT(1) 477#define WOW_MAGIC BIT(2) 478#define WOW_UWF BIT(3) 479 480#define IMR8190_DISABLED 0x0 481#define IMR_BCNDMAINT6 BIT(31) 482#define IMR_BCNDMAINT5 BIT(30) 483#define IMR_BCNDMAINT4 BIT(29) 484#define IMR_BCNDMAINT3 BIT(28) 485#define IMR_BCNDMAINT2 BIT(27) 486#define IMR_BCNDMAINT1 BIT(26) 487#define IMR_BCNDOK8 BIT(25) 488#define IMR_BCNDOK7 BIT(24) 489#define IMR_BCNDOK6 BIT(23) 490#define IMR_BCNDOK5 BIT(22) 491#define IMR_BCNDOK4 BIT(21) 492#define IMR_BCNDOK3 BIT(20) 493#define IMR_BCNDOK2 BIT(19) 494#define IMR_BCNDOK1 BIT(18) 495#define IMR_TIMEOUT2 BIT(17) 496#define IMR_TIMEOUT1 BIT(16) 497#define IMR_TXFOVW BIT(15) 498#define IMR_PSTIMEOUT BIT(14) 499#define IMR_BCNINT BIT(13) 500#define IMR_RXFOVW BIT(12) 501#define IMR_RDU BIT(11) 502#define IMR_ATIMEND BIT(10) 503#define IMR_BDOK BIT(9) 504#define IMR_HIGHDOK BIT(8) 505#define IMR_TBDOK BIT(7) 506#define IMR_MGNTDOK BIT(6) 507#define IMR_TBDER BIT(5) 508#define IMR_BKDOK BIT(4) 509#define IMR_BEDOK BIT(3) 510#define IMR_VIDOK BIT(2) 511#define IMR_VODOK BIT(1) 512#define IMR_ROK BIT(0) 513 514#define IMR_TXERR BIT(11) 515#define IMR_RXERR BIT(10) 516#define IMR_C2HCMD BIT(9) 517#define IMR_CPWM BIT(8) 518#define IMR_OCPINT BIT(1) 519#define IMR_WLANOFF BIT(0) 520 521#define EFUSE_REAL_CONTENT_LEN 512 522#define EFUSE_OOB_PROTECT_BYTES 15 523 524#define EEPROM_DEFAULT_TSSI 0x0 525#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 526#define EEPROM_DEFAULT_CRYSTALCAP 0x5 527#define EEPROM_DEFAULT_BOARDTYPE 0x02 528#define EEPROM_DEFAULT_TXPOWER 0x1010 529#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 530 531#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 532#define EEPROM_DEFAULT_THERMALMETER 0x12 533#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 534#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 535#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 536#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 537#define EEPROM_DEFAULT_HT20_DIFF 2 538#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 539#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 540 541#define RF_OPTION1 0x79 542#define RF_OPTION2 0x7A 543#define RF_OPTION3 0x7B 544#define RF_OPTION4 0x7C 545 546#define EEPROM_DEFAULT_PID 0x1234 547#define EEPROM_DEFAULT_VID 0x5678 548#define EEPROM_DEFAULT_CUSTOMERID 0xAB 549#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 550#define EEPROM_DEFAULT_VERSION 0 551 552#define EEPROM_CHANNEL_PLAN_FCC 0x0 553#define EEPROM_CHANNEL_PLAN_IC 0x1 554#define EEPROM_CHANNEL_PLAN_ETSI 0x2 555#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 556#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 557#define EEPROM_CHANNEL_PLAN_MKK 0x5 558#define EEPROM_CHANNEL_PLAN_MKK1 0x6 559#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 560#define EEPROM_CHANNEL_PLAN_TELEC 0x8 561#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 562#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 563#define EEPROM_CHANNEL_PLAN_NCC 0xB 564#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 565 566#define EEPROM_CID_DEFAULT 0x0 567#define EEPROM_CID_TOSHIBA 0x4 568#define EEPROM_CID_CCX 0x10 569#define EEPROM_CID_QMI 0x0D 570#define EEPROM_CID_WHQL 0xFE 571 572#define RTL8192_EEPROM_ID 0x8129 573 574#define RTL8190_EEPROM_ID 0x8129 575#define EEPROM_HPON 0x02 576#define EEPROM_CLK 0x06 577#define EEPROM_TESTR 0x08 578 579#define EEPROM_VID 0x0A 580#define EEPROM_DID 0x0C 581#define EEPROM_SVID 0x0E 582#define EEPROM_SMID 0x10 583 584#define EEPROM_MAC_ADDR 0x16 585 586#define EEPROM_CCK_TX_PWR_INX 0x5A 587#define EEPROM_HT40_1S_TX_PWR_INX 0x60 588#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 589#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 590#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 591#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F 592#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 593 594#define EEPROM_TSSI_A 0x76 595#define EEPROM_TSSI_B 0x77 596#define EEPROM_THERMAL_METER 0x78 597#define EEPROM_XTAL_K 0x78 598#define EEPROM_RF_OPT1 0x79 599#define EEPROM_RF_OPT2 0x7A 600#define EEPROM_RF_OPT3 0x7B 601#define EEPROM_RF_OPT4 0x7C 602#define EEPROM_CHANNEL_PLAN 0x7D 603#define EEPROM_VERSION 0x7E 604#define EEPROM_CUSTOMER_ID 0x7F 605 606#define EEPROM_PWRDIFF 0x54 607 608#define EEPROM_TXPOWERCCK 0x5A 609#define EEPROM_TXPOWERHT40_1S 0x60 610#define EEPROM_TXPOWERHT40_2SDIFF 0x66 611#define EEPROM_TXPOWERHT20DIFF 0x69 612#define EEPROM_TXPOWER_OFDMDIFF 0x6C 613 614#define EEPROM_TXPWR_GROUP 0x6F 615 616#define EEPROM_CHANNELPLAN 0x75 617 618#define STOPBECON BIT(6) 619#define STOPHIGHT BIT(5) 620#define STOPMGT BIT(4) 621#define STOPVO BIT(3) 622#define STOPVI BIT(2) 623#define STOPBE BIT(1) 624#define STOPBK BIT(0) 625 626#define RCR_APPFCS BIT(31) 627#define RCR_APP_FCS BIT(31) 628#define RCR_APP_MIC BIT(30) 629#define RCR_APP_ICV BIT(29) 630#define RCR_APP_PHYSTS BIT(28) 631#define RCR_APP_PHYST_RXFF BIT(28) 632#define RCR_APP_BA_SSN BIT(27) 633#define RCR_ENMBID BIT(24) 634#define RCR_LSIGEN BIT(23) 635#define RCR_MFBEN BIT(22) 636#define RCR_HTC_LOC_CTRL BIT(14) 637#define RCR_AMF BIT(13) 638#define RCR_ACF BIT(12) 639#define RCR_ADF BIT(11) 640#define RCR_AICV BIT(9) 641#define RCR_ACRC32 BIT(8) 642#define RCR_CBSSID_BCN BIT(7) 643#define RCR_CBSSID_DATA BIT(6) 644#define RCR_CBSSID RCR_CBSSID_DATA 645#define RCR_APWRMGT BIT(5) 646#define RCR_ADD3 BIT(4) 647#define RCR_AB BIT(3) 648#define RCR_AM BIT(2) 649#define RCR_APM BIT(1) 650#define RCR_AAP BIT(0) 651#define RCR_MXDMA_OFFSET 8 652#define RCR_FIFO_OFFSET 13 653 654#define RSV_CTRL 0x001C 655#define RD_CTRL 0x0524 656 657#define REG_USB_VID 0xFE60 658#define REG_USB_PID 0xFE62 659#define REG_USB_OPTIONAL 0xFE64 660#define REG_USB_CHIRP_K 0xFE65 661#define REG_USB_PHY 0xFE66 662#define REG_USB_MAC_ADDR 0xFE70 663#define REG_USB_HRPWM 0xFE58 664#define REG_USB_HCPWM 0xFE57 665 666#define SW18_FPWM BIT(3) 667 668#define ISO_MD2PP BIT(0) 669#define ISO_UA2USB BIT(1) 670#define ISO_UD2CORE BIT(2) 671#define ISO_PA2PCIE BIT(3) 672#define ISO_PD2CORE BIT(4) 673#define ISO_IP2MAC BIT(5) 674#define ISO_DIOP BIT(6) 675#define ISO_DIOE BIT(7) 676#define ISO_EB2CORE BIT(8) 677#define ISO_DIOR BIT(9) 678 679#define PWC_EV25V BIT(14) 680#define PWC_EV12V BIT(15) 681 682#define FEN_BBRSTB BIT(0) 683#define FEN_BB_GLB_RSTN BIT(1) 684#define FEN_USBA BIT(2) 685#define FEN_UPLL BIT(3) 686#define FEN_USBD BIT(4) 687#define FEN_DIO_PCIE BIT(5) 688#define FEN_PCIEA BIT(6) 689#define FEN_PPLL BIT(7) 690#define FEN_PCIED BIT(8) 691#define FEN_DIOE BIT(9) 692#define FEN_CPUEN BIT(10) 693#define FEN_DCORE BIT(11) 694#define FEN_ELDR BIT(12) 695#define FEN_DIO_RF BIT(13) 696#define FEN_HWPDN BIT(14) 697#define FEN_MREGEN BIT(15) 698 699#define PFM_LDALL BIT(0) 700#define PFM_ALDN BIT(1) 701#define PFM_LDKP BIT(2) 702#define PFM_WOWL BIT(3) 703#define ENPDN BIT(4) 704#define PDN_PL BIT(5) 705#define APFM_ONMAC BIT(8) 706#define APFM_OFF BIT(9) 707#define APFM_RSM BIT(10) 708#define AFSM_HSUS BIT(11) 709#define AFSM_PCIE BIT(12) 710#define APDM_MAC BIT(13) 711#define APDM_HOST BIT(14) 712#define APDM_HPDN BIT(15) 713#define RDY_MACON BIT(16) 714#define SUS_HOST BIT(17) 715#define ROP_ALD BIT(20) 716#define ROP_PWR BIT(21) 717#define ROP_SPS BIT(22) 718#define SOP_MRST BIT(25) 719#define SOP_FUSE BIT(26) 720#define SOP_ABG BIT(27) 721#define SOP_AMB BIT(28) 722#define SOP_RCK BIT(29) 723#define SOP_A8M BIT(30) 724#define XOP_BTCK BIT(31) 725 726#define ANAD16V_EN BIT(0) 727#define ANA8M BIT(1) 728#define MACSLP BIT(4) 729#define LOADER_CLK_EN BIT(5) 730#define _80M_SSC_DIS BIT(7) 731#define _80M_SSC_EN_HO BIT(8) 732#define PHY_SSC_RSTB BIT(9) 733#define SEC_CLK_EN BIT(10) 734#define MAC_CLK_EN BIT(11) 735#define SYS_CLK_EN BIT(12) 736#define RING_CLK_EN BIT(13) 737 738#define BOOT_FROM_EEPROM BIT(4) 739#define EEPROM_EN BIT(5) 740 741#define AFE_BGEN BIT(0) 742#define AFE_MBEN BIT(1) 743#define MAC_ID_EN BIT(7) 744 745#define WLOCK_ALL BIT(0) 746#define WLOCK_00 BIT(1) 747#define WLOCK_04 BIT(2) 748#define WLOCK_08 BIT(3) 749#define WLOCK_40 BIT(4) 750#define R_DIS_PRST_0 BIT(5) 751#define R_DIS_PRST_1 BIT(6) 752#define LOCK_ALL_EN BIT(7) 753 754#define RF_EN BIT(0) 755#define RF_RSTB BIT(1) 756#define RF_SDMRSTB BIT(2) 757 758#define LDA15_EN BIT(0) 759#define LDA15_STBY BIT(1) 760#define LDA15_OBUF BIT(2) 761#define LDA15_REG_VOS BIT(3) 762#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 763 764#define LDV12_EN BIT(0) 765#define LDV12_SDBY BIT(1) 766#define LPLDO_HSM BIT(2) 767#define LPLDO_LSM_DIS BIT(3) 768#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 769 770#define XTAL_EN BIT(0) 771#define XTAL_BSEL BIT(1) 772#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 773#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 774#define XTAL_GATE_USB BIT(8) 775#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 776#define XTAL_GATE_AFE BIT(11) 777#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 778#define XTAL_RF_GATE BIT(14) 779#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 780#define XTAL_GATE_DIG BIT(17) 781#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 782#define XTAL_BT_GATE BIT(20) 783#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 784#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 785 786#define CKDLY_AFE BIT(26) 787#define CKDLY_USB BIT(27) 788#define CKDLY_DIG BIT(28) 789#define CKDLY_BT BIT(29) 790 791#define APLL_EN BIT(0) 792#define APLL_320_EN BIT(1) 793#define APLL_FREF_SEL BIT(2) 794#define APLL_EDGE_SEL BIT(3) 795#define APLL_WDOGB BIT(4) 796#define APLL_LPFEN BIT(5) 797 798#define APLL_REF_CLK_13MHZ 0x1 799#define APLL_REF_CLK_19_2MHZ 0x2 800#define APLL_REF_CLK_20MHZ 0x3 801#define APLL_REF_CLK_25MHZ 0x4 802#define APLL_REF_CLK_26MHZ 0x5 803#define APLL_REF_CLK_38_4MHZ 0x6 804#define APLL_REF_CLK_40MHZ 0x7 805 806#define APLL_320EN BIT(14) 807#define APLL_80EN BIT(15) 808#define APLL_1MEN BIT(24) 809 810#define ALD_EN BIT(18) 811#define EF_PD BIT(19) 812#define EF_FLAG BIT(31) 813 814#define EF_TRPT BIT(7) 815#define LDOE25_EN BIT(31) 816 817#define RSM_EN BIT(0) 818#define TIMER_EN BIT(4) 819 820#define TRSW0EN BIT(2) 821#define TRSW1EN BIT(3) 822#define EROM_EN BIT(4) 823#define ENBT BIT(5) 824#define ENUART BIT(8) 825#define UART_910 BIT(9) 826#define ENPMAC BIT(10) 827#define SIC_SWRST BIT(11) 828#define ENSIC BIT(12) 829#define SIC_23 BIT(13) 830#define ENHDP BIT(14) 831#define SIC_LBK BIT(15) 832 833#define LED0PL BIT(4) 834#define LED1PL BIT(12) 835#define LED0DIS BIT(7) 836 837#define MCUFWDL_EN BIT(0) 838#define MCUFWDL_RDY BIT(1) 839#define FWDL_CHKSUM_RPT BIT(2) 840#define MACINI_RDY BIT(3) 841#define BBINI_RDY BIT(4) 842#define RFINI_RDY BIT(5) 843#define WINTINI_RDY BIT(6) 844#define CPRST BIT(23) 845 846#define XCLK_VLD BIT(0) 847#define ACLK_VLD BIT(1) 848#define UCLK_VLD BIT(2) 849#define PCLK_VLD BIT(3) 850#define PCIRSTB BIT(4) 851#define V15_VLD BIT(5) 852#define TRP_B15V_EN BIT(7) 853#define SIC_IDLE BIT(8) 854#define BD_MAC2 BIT(9) 855#define BD_MAC1 BIT(10) 856#define IC_MACPHY_MODE BIT(11) 857#define BT_FUNC BIT(16) 858#define VENDOR_ID BIT(19) 859#define PAD_HWPD_IDN BIT(22) 860#define TRP_VAUX_EN BIT(23) 861#define TRP_BT_EN BIT(24) 862#define BD_PKG_SEL BIT(25) 863#define BD_HCI_SEL BIT(26) 864#define TYPE_ID BIT(27) 865#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 866 867#define CHIP_VER_RTL_MASK 0xF000 868#define CHIP_VER_RTL_SHIFT 12 869 870#define REG_LBMODE (REG_CR + 3) 871 872#define HCI_TXDMA_EN BIT(0) 873#define HCI_RXDMA_EN BIT(1) 874#define TXDMA_EN BIT(2) 875#define RXDMA_EN BIT(3) 876#define PROTOCOL_EN BIT(4) 877#define SCHEDULE_EN BIT(5) 878#define MACTXEN BIT(6) 879#define MACRXEN BIT(7) 880#define ENSWBCN BIT(8) 881#define ENSEC BIT(9) 882 883#define _NETTYPE(x) (((x) & 0x3) << 16) 884#define MASK_NETTYPE 0x30000 885#define NT_NO_LINK 0x0 886#define NT_LINK_AD_HOC 0x1 887#define NT_LINK_AP 0x2 888#define NT_AS_AP 0x3 889 890#define _LBMODE(x) (((x) & 0xF) << 24) 891#define MASK_LBMODE 0xF000000 892#define LOOPBACK_NORMAL 0x0 893#define LOOPBACK_IMMEDIATELY 0xB 894#define LOOPBACK_MAC_DELAY 0x3 895#define LOOPBACK_PHY 0x1 896#define LOOPBACK_DMA 0x7 897 898#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 899#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 900#define _PSRX_MASK 0xF 901#define _PSTX_MASK 0xF0 902#define _PSRX(x) (x) 903#define _PSTX(x) ((x) << 4) 904 905#define PBP_64 0x0 906#define PBP_128 0x1 907#define PBP_256 0x2 908#define PBP_512 0x3 909#define PBP_1024 0x4 910 911#define RXDMA_ARBBW_EN BIT(0) 912#define RXSHFT_EN BIT(1) 913#define RXDMA_AGG_EN BIT(2) 914#define QS_VO_QUEUE BIT(8) 915#define QS_VI_QUEUE BIT(9) 916#define QS_BE_QUEUE BIT(10) 917#define QS_BK_QUEUE BIT(11) 918#define QS_MANAGER_QUEUE BIT(12) 919#define QS_HIGH_QUEUE BIT(13) 920 921#define HQSEL_VOQ BIT(0) 922#define HQSEL_VIQ BIT(1) 923#define HQSEL_BEQ BIT(2) 924#define HQSEL_BKQ BIT(3) 925#define HQSEL_MGTQ BIT(4) 926#define HQSEL_HIQ BIT(5) 927 928#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 929#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 930#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 931#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 932#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 933#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 934 935#define QUEUE_LOW 1 936#define QUEUE_NORMAL 2 937#define QUEUE_HIGH 3 938 939#define _LLT_NO_ACTIVE 0x0 940#define _LLT_WRITE_ACCESS 0x1 941#define _LLT_READ_ACCESS 0x2 942 943#define _LLT_INIT_DATA(x) ((x) & 0xFF) 944#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 945#define _LLT_OP(x) (((x) & 0x3) << 30) 946#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 947 948#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 949#define BB_WRITE_EN BIT(30) 950#define BB_READ_EN BIT(31) 951 952#define _HPQ(x) ((x) & 0xFF) 953#define _LPQ(x) (((x) & 0xFF) << 8) 954#define _PUBQ(x) (((x) & 0xFF) << 16) 955#define _NPQ(x) ((x) & 0xFF) 956 957#define HPQ_PUBLIC_DIS BIT(24) 958#define LPQ_PUBLIC_DIS BIT(25) 959#define LD_RQPN BIT(31) 960 961#define BCN_VALID BIT(16) 962#define BCN_HEAD(x) (((x) & 0xFF) << 8) 963#define BCN_HEAD_MASK 0xFF00 964 965#define BLK_DESC_NUM_SHIFT 4 966#define BLK_DESC_NUM_MASK 0xF 967 968#define DROP_DATA_EN BIT(9) 969 970#define EN_AMPDU_RTY_NEW BIT(7) 971 972#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 973 974#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 975#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 976 977#define RATE_REG_BITMAP_ALL 0xFFFFF 978 979#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 980 981#define _RRSR_RSC(x) (((x) & 0x3) << 21) 982#define RRSR_RSC_RESERVED 0x0 983#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 984#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 985#define RRSR_RSC_DUPLICATE_MODE 0x3 986 987#define USE_SHORT_G1 BIT(20) 988 989#define _AGGLMT_MCS0(x) ((x) & 0xF) 990#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 991#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 992#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 993#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 994#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 995#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 996#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 997 998#define RETRY_LIMIT_SHORT_SHIFT 8 999#define RETRY_LIMIT_LONG_SHIFT 0 1000
1001#define _DARF_RC1(x) ((x) & 0x1F) 1002#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1003#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1004#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1005#define _DARF_RC5(x) ((x) & 0x1F) 1006#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1007#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1008#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1009 1010#define _RARF_RC1(x) ((x) & 0x1F) 1011#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1012#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1013#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1014#define _RARF_RC5(x) ((x) & 0x1F) 1015#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1016#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1017#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1018 1019#define AC_PARAM_TXOP_OFFSET 16 1020#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1021#define AC_PARAM_ECW_MAX_OFFSET 12 1022#define AC_PARAM_ECW_MIN_OFFSET 8 1023#define AC_PARAM_AIFS_OFFSET 0 1024 1025#define _AIFS(x) (x) 1026#define _ECW_MAX_MIN(x) ((x) << 8) 1027#define _TXOP_LIMIT(x) ((x) << 16) 1028 1029#define _BCNIFS(x) ((x) & 0xFF) 1030#define _BCNECW(x) ((((x) & 0xF)) << 8) 1031 1032#define _LRL(x) ((x) & 0x3F) 1033#define _SRL(x) (((x) & 0x3F) << 8) 1034 1035#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1036#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1037 1038#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1039#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1040 1041#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1042 1043#define DIS_EDCA_CNT_DWN BIT(11) 1044 1045#define EN_MBSSID BIT(1) 1046#define EN_TXBCN_RPT BIT(2) 1047#define EN_BCN_FUNCTION BIT(3) 1048 1049#define TSFTR_RST BIT(0) 1050#define TSFTR1_RST BIT(1) 1051 1052#define STOP_BCNQ BIT(6) 1053 1054#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1055#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1056 1057#define ACMHW_HWEN BIT(0) 1058#define ACMHW_BEQEN BIT(1) 1059#define ACMHW_VIQEN BIT(2) 1060#define ACMHW_VOQEN BIT(3) 1061#define ACMHW_BEQSTATUS BIT(4) 1062#define ACMHW_VIQSTATUS BIT(5) 1063#define ACMHW_VOQSTATUS BIT(6) 1064 1065#define APSDOFF BIT(6) 1066#define APSDOFF_STATUS BIT(7) 1067 1068#define BW_20MHZ BIT(2) 1069 1070#define RATE_BITMAP_ALL 0xFFFFF 1071 1072#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1073 1074#define TSFRST BIT(0) 1075#define DIS_GCLK BIT(1) 1076#define PAD_SEL BIT(2) 1077#define PWR_ST BIT(6) 1078#define PWRBIT_OW_EN BIT(7) 1079#define ACRC BIT(8) 1080#define CFENDFORM BIT(9) 1081#define ICV BIT(10) 1082 1083#define AAP BIT(0) 1084#define APM BIT(1) 1085#define AM BIT(2) 1086#define AB BIT(3) 1087#define ADD3 BIT(4) 1088#define APWRMGT BIT(5) 1089#define CBSSID BIT(6) 1090#define CBSSID_DATA BIT(6) 1091#define CBSSID_BCN BIT(7) 1092#define ACRC32 BIT(8) 1093#define AICV BIT(9) 1094#define ADF BIT(11) 1095#define ACF BIT(12) 1096#define AMF BIT(13) 1097#define HTC_LOC_CTRL BIT(14) 1098#define UC_DATA_EN BIT(16) 1099#define BM_DATA_EN BIT(17) 1100#define MFBEN BIT(22) 1101#define LSIGEN BIT(23) 1102#define ENMBID BIT(24) 1103#define APP_BASSN BIT(27) 1104#define APP_PHYSTS BIT(28) 1105#define APP_ICV BIT(29) 1106#define APP_MIC BIT(30) 1107#define APP_FCS BIT(31) 1108 1109#define _MIN_SPACE(x) ((x) & 0x7) 1110#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1111 1112#define RXERR_TYPE_OFDM_PPDU 0 1113#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1114#define RXERR_TYPE_OFDM_MPDU_OK 2 1115#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1116#define RXERR_TYPE_CCK_PPDU 4 1117#define RXERR_TYPE_CCK_FALSE_ALARM 5 1118#define RXERR_TYPE_CCK_MPDU_OK 6 1119#define RXERR_TYPE_CCK_MPDU_FAIL 7 1120#define RXERR_TYPE_HT_PPDU 8 1121#define RXERR_TYPE_HT_FALSE_ALARM 9 1122#define RXERR_TYPE_HT_MPDU_TOTAL 10 1123#define RXERR_TYPE_HT_MPDU_OK 11 1124#define RXERR_TYPE_HT_MPDU_FAIL 12 1125#define RXERR_TYPE_RX_FULL_DROP 15 1126 1127#define RXERR_COUNTER_MASK 0xFFFFF 1128#define RXERR_RPT_RST BIT(27) 1129#define _RXERR_RPT_SEL(type) ((type) << 28) 1130 1131#define SCR_TXUSEDK BIT(0) 1132#define SCR_RXUSEDK BIT(1) 1133#define SCR_TXENCENABLE BIT(2) 1134#define SCR_RXDECENABLE BIT(3) 1135#define SCR_SKBYA2 BIT(4) 1136#define SCR_NOSKMC BIT(5) 1137#define SCR_TXBCUSEDK BIT(6) 1138#define SCR_RXBCUSEDK BIT(7) 1139 1140#define USB_IS_HIGH_SPEED 0 1141#define USB_IS_FULL_SPEED 1 1142#define USB_SPEED_MASK BIT(5) 1143 1144#define USB_NORMAL_SIE_EP_MASK 0xF 1145#define USB_NORMAL_SIE_EP_SHIFT 4 1146 1147#define USB_TEST_EP_MASK 0x30 1148#define USB_TEST_EP_SHIFT 4 1149 1150#define USB_AGG_EN BIT(3) 1151 1152#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1153 1154#define POLLING_LLT_THRESHOLD 20 1155#define POLLING_READY_TIMEOUT_COUNT 1000 1156 1157#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1158#define EPROM_CMD_CONFIG 0x3 1159#define EPROM_CMD_LOAD 1 1160 1161#define HWSET_MAX_SIZE 128 1162#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1163#define EFUSE_MAX_SECTION 16 1164 1165#define WL_HWPDN_EN BIT(0) 1166 1167#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1168 1169#define RPMAC_RESET 0x100 1170#define RPMAC_TXSTART 0x104 1171#define RPMAC_TXLEGACYSIG 0x108 1172#define RPMAC_TXHTSIG1 0x10c 1173#define RPMAC_TXHTSIG2 0x110 1174#define RPMAC_PHYDEBUG 0x114 1175#define RPMAC_TXPACKETNUM 0x118 1176#define RPMAC_TXIDLE 0x11c 1177#define RPMAC_TXMACHEADER0 0x120 1178#define RPMAC_TXMACHEADER1 0x124 1179#define RPMAC_TXMACHEADER2 0x128 1180#define RPMAC_TXMACHEADER3 0x12c 1181#define RPMAC_TXMACHEADER4 0x130 1182#define RPMAC_TXMACHEADER5 0x134 1183#define RPMAC_TXDADATYPE 0x138 1184#define RPMAC_TXRANDOMSEED 0x13c 1185#define RPMAC_CCKPLCPPREAMBLE 0x140 1186#define RPMAC_CCKPLCPHEADER 0x144 1187#define RPMAC_CCKCRC16 0x148 1188#define RPMAC_OFDMRXCRC32OK 0x170 1189#define RPMAC_OFDMRXCRC32ER 0x174 1190#define RPMAC_OFDMRXPARITYER 0x178 1191#define RPMAC_OFDMRXCRC8ER 0x17c 1192#define RPMAC_CCKCRXRC16ER 0x180 1193#define RPMAC_CCKCRXRC32ER 0x184 1194#define RPMAC_CCKCRXRC32OK 0x188 1195#define RPMAC_TXSTATUS 0x18c 1196 1197#define RFPGA0_RFMOD 0x800 1198 1199#define RFPGA0_TXINFO 0x804 1200#define RFPGA0_PSDFUNCTION 0x808 1201 1202#define RFPGA0_TXGAINSTAGE 0x80c 1203 1204#define RFPGA0_RFTIMING1 0x810 1205#define RFPGA0_RFTIMING2 0x814 1206 1207#define RFPGA0_XA_HSSIPARAMETER1 0x820 1208#define RFPGA0_XA_HSSIPARAMETER2 0x824 1209#define RFPGA0_XB_HSSIPARAMETER1 0x828 1210#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1211 1212#define RFPGA0_XA_LSSIPARAMETER 0x840 1213#define RFPGA0_XB_LSSIPARAMETER 0x844 1214 1215#define RFPGA0_RFWAKEUPPARAMETER 0x850 1216#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1217 1218#define RFPGA0_XAB_SWITCHCONTROL 0x858 1219#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1220 1221#define RFPGA0_XA_RFINTERFACEOE 0x860 1222#define RFPGA0_XB_RFINTERFACEOE 0x864 1223 1224#define RFPGA0_XAB_RFINTERFACESW 0x870 1225#define RFPGA0_XCD_RFINTERFACESW 0x874 1226 1227#define RFPGA0_XAB_RFPARAMETER 0x878 1228#define RFPGA0_XCD_RFPARAMETER 0x87c 1229 1230#define RFPGA0_ANALOGPARAMETER1 0x880 1231#define RFPGA0_ANALOGPARAMETER2 0x884 1232#define RFPGA0_ANALOGPARAMETER3 0x888 1233#define RFPGA0_ANALOGPARAMETER4 0x88c 1234 1235#define RFPGA0_XA_LSSIREADBACK 0x8a0 1236#define RFPGA0_XB_LSSIREADBACK 0x8a4 1237#define RFPGA0_XC_LSSIREADBACK 0x8a8 1238#define RFPGA0_XD_LSSIREADBACK 0x8ac 1239 1240#define RFPGA0_PSDREPORT 0x8b4 1241#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1242#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1243#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1244#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1245 1246#define RFPGA1_RFMOD 0x900 1247 1248#define RFPGA1_TXBLOCK 0x904 1249#define RFPGA1_DEBUGSELECT 0x908 1250#define RFPGA1_TXINFO 0x90c 1251 1252#define RCCK0_SYSTEM 0xa00 1253 1254#define RCCK0_AFESETTING 0xa04 1255#define RCCK0_CCA 0xa08 1256 1257#define RCCK0_RXAGC1 0xa0c 1258#define RCCK0_RXAGC2 0xa10 1259 1260#define RCCK0_RXHP 0xa14 1261 1262#define RCCK0_DSPPARAMETER1 0xa18 1263#define RCCK0_DSPPARAMETER2 0xa1c 1264 1265#define RCCK0_TXFILTER1 0xa20 1266#define RCCK0_TXFILTER2 0xa24 1267#define RCCK0_DEBUGPORT 0xa28 1268#define RCCK0_FALSEALARMREPORT 0xa2c 1269#define RCCK0_TRSSIREPORT 0xa50 1270#define RCCK0_RXREPORT 0xa54 1271#define RCCK0_FACOUNTERLOWER 0xa5c 1272#define RCCK0_FACOUNTERUPPER 0xa58 1273 1274#define ROFDM0_LSTF 0xc00 1275 1276#define ROFDM0_TRXPATHENABLE 0xc04 1277#define ROFDM0_TRMUXPAR 0xc08 1278#define ROFDM0_TRSWISOLATION 0xc0c 1279 1280#define ROFDM0_XARXAFE 0xc10 1281#define ROFDM0_XARXIQIMBALANCE 0xc14 1282#define ROFDM0_XBRXAFE 0xc18 1283#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1284#define ROFDM0_XCRXAFE 0xc20 1285#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1286#define ROFDM0_XDRXAFE 0xc28 1287#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1288 1289#define ROFDM0_RXDETECTOR1 0xc30 1290#define ROFDM0_RXDETECTOR2 0xc34 1291#define ROFDM0_RXDETECTOR3 0xc38 1292#define ROFDM0_RXDETECTOR4 0xc3c 1293 1294#define ROFDM0_RXDSP 0xc40 1295#define ROFDM0_CFOANDDAGC 0xc44 1296#define ROFDM0_CCADROPTHRESHOLD 0xc48 1297#define ROFDM0_ECCATHRESHOLD 0xc4c 1298 1299#define ROFDM0_XAAGCCORE1 0xc50 1300#define ROFDM0_XAAGCCORE2 0xc54 1301#define ROFDM0_XBAGCCORE1 0xc58 1302#define ROFDM0_XBAGCCORE2 0xc5c 1303#define ROFDM0_XCAGCCORE1 0xc60 1304#define ROFDM0_XCAGCCORE2 0xc64 1305#define ROFDM0_XDAGCCORE1 0xc68 1306#define ROFDM0_XDAGCCORE2 0xc6c 1307 1308#define ROFDM0_AGCPARAMETER1 0xc70 1309#define ROFDM0_AGCPARAMETER2 0xc74 1310#define ROFDM0_AGCRSSITABLE 0xc78 1311#define ROFDM0_HTSTFAGC 0xc7c 1312 1313#define ROFDM0_XATXIQIMBALANCE 0xc80 1314#define ROFDM0_XATXAFE 0xc84 1315#define ROFDM0_XBTXIQIMBALANCE 0xc88 1316#define ROFDM0_XBTXAFE 0xc8c 1317#define ROFDM0_XCTXIQIMBALANCE 0xc90 1318#define ROFDM0_XCTXAFE 0xc94 1319#define ROFDM0_XDTXIQIMBALANCE 0xc98 1320#define ROFDM0_XDTXAFE 0xc9c 1321 1322#define ROFDM0_RXIQEXTANTA 0xca0 1323 1324#define ROFDM0_RXHPPARAMETER 0xce0 1325#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1326#define ROFDM0_FRAMESYNC 0xcf0 1327#define ROFDM0_DFSREPORT 0xcf4 1328#define ROFDM0_TXCOEFF1 0xca4 1329#define ROFDM0_TXCOEFF2 0xca8 1330#define ROFDM0_TXCOEFF3 0xcac 1331#define ROFDM0_TXCOEFF4 0xcb0 1332#define ROFDM0_TXCOEFF5 0xcb4 1333#define ROFDM0_TXCOEFF6 0xcb8 1334 1335#define ROFDM1_LSTF 0xd00 1336#define ROFDM1_TRXPATHENABLE 0xd04 1337 1338#define ROFDM1_CF0 0xd08 1339#define ROFDM1_CSI1 0xd10 1340#define ROFDM1_SBD 0xd14 1341#define ROFDM1_CSI2 0xd18 1342#define ROFDM1_CFOTRACKING 0xd2c 1343#define ROFDM1_TRXMESAURE1 0xd34 1344#define ROFDM1_INTFDET 0xd3c 1345#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1346#define ROFDM1_PSEUDONOISESTATECD 0xd54 1347#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1348 1349#define ROFDM_PHYCOUNTER1 0xda0 1350#define ROFDM_PHYCOUNTER2 0xda4 1351#define ROFDM_PHYCOUNTER3 0xda8 1352 1353#define ROFDM_SHORTCFOAB 0xdac 1354#define ROFDM_SHORTCFOCD 0xdb0 1355#define ROFDM_LONGCFOAB 0xdb4 1356#define ROFDM_LONGCFOCD 0xdb8 1357#define ROFDM_TAILCF0AB 0xdbc 1358#define ROFDM_TAILCF0CD 0xdc0 1359#define ROFDM_PWMEASURE1 0xdc4 1360#define ROFDM_PWMEASURE2 0xdc8 1361#define ROFDM_BWREPORT 0xdcc 1362#define ROFDM_AGCREPORT 0xdd0 1363#define ROFDM_RXSNR 0xdd4 1364#define ROFDM_RXEVMCSI 0xdd8 1365#define ROFDM_SIGREPORT 0xddc 1366 1367#define RTXAGC_A_RATE18_06 0xe00 1368#define RTXAGC_A_RATE54_24 0xe04 1369#define RTXAGC_A_CCK1_MCS32 0xe08 1370#define RTXAGC_A_MCS03_MCS00 0xe10 1371#define RTXAGC_A_MCS07_MCS04 0xe14 1372#define RTXAGC_A_MCS11_MCS08 0xe18 1373#define RTXAGC_A_MCS15_MCS12 0xe1c 1374 1375#define RTXAGC_B_RATE18_06 0x830 1376#define RTXAGC_B_RATE54_24 0x834 1377#define RTXAGC_B_CCK1_55_MCS32 0x838 1378#define RTXAGC_B_MCS03_MCS00 0x83c 1379#define RTXAGC_B_MCS07_MCS04 0x848 1380#define RTXAGC_B_MCS11_MCS08 0x84c 1381#define RTXAGC_B_MCS15_MCS12 0x868 1382#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1383 1384#define RZEBRA1_HSSIENABLE 0x0 1385#define RZEBRA1_TRXENABLE1 0x1 1386#define RZEBRA1_TRXENABLE2 0x2 1387#define RZEBRA1_AGC 0x4 1388#define RZEBRA1_CHARGEPUMP 0x5 1389#define RZEBRA1_CHANNEL 0x7 1390 1391#define RZEBRA1_TXGAIN 0x8 1392#define RZEBRA1_TXLPF 0x9 1393#define RZEBRA1_RXLPF 0xb 1394#define RZEBRA1_RXHPFCORNER 0xc 1395 1396#define RGLOBALCTRL 0 1397#define RRTL8256_TXLPF 19 1398#define RRTL8256_RXLPF 11 1399#define RRTL8258_TXLPF 0x11 1400#define RRTL8258_RXLPF 0x13 1401#define RRTL8258_RSSILPF 0xa 1402 1403#define RF_AC 0x00 1404 1405#define RF_IQADJ_G1 0x01 1406#define RF_IQADJ_G2 0x02 1407#define RF_POW_TRSW 0x05 1408 1409#define RF_GAIN_RX 0x06 1410#define RF_GAIN_TX 0x07 1411 1412#define RF_TXM_IDAC 0x08 1413#define RF_BS_IQGEN 0x0F 1414 1415#define RF_MODE1 0x10 1416#define RF_MODE2 0x11 1417 1418#define RF_RX_AGC_HP 0x12 1419#define RF_TX_AGC 0x13 1420#define RF_BIAS 0x14 1421#define RF_IPA 0x15 1422#define RF_POW_ABILITY 0x17 1423#define RF_MODE_AG 0x18 1424#define RRFCHANNEL 0x18 1425#define RF_CHNLBW 0x18 1426#define RF_TOP 0x19 1427 1428#define RF_RX_G1 0x1A 1429#define RF_RX_G2 0x1B 1430 1431#define RF_RX_BB2 0x1C 1432#define RF_RX_BB1 0x1D 1433 1434#define RF_RCK1 0x1E 1435#define RF_RCK2 0x1F 1436 1437#define RF_TX_G1 0x20 1438#define RF_TX_G2 0x21 1439#define RF_TX_G3 0x22 1440 1441#define RF_TX_BB1 0x23 1442#define RF_T_METER 0x24 1443 1444#define RF_SYN_G1 0x25 1445#define RF_SYN_G2 0x26 1446#define RF_SYN_G3 0x27 1447#define RF_SYN_G4 0x28 1448#define RF_SYN_G5 0x29 1449#define RF_SYN_G6 0x2A 1450#define RF_SYN_G7 0x2B 1451#define RF_SYN_G8 0x2C 1452 1453#define RF_RCK_OS 0x30 1454#define RF_TXPA_G1 0x31 1455#define RF_TXPA_G2 0x32 1456#define RF_TXPA_G3 0x33 1457 1458#define BBBRESETB 0x100 1459#define BGLOBALRESETB 0x200 1460#define BOFDMTXSTART 0x4 1461#define BCCKTXSTART 0x8 1462#define BCRC32DEBUG 0x100 1463#define BPMACLOOPBACK 0x10 1464#define BTXLSIG 0xffffff 1465#define BOFDMTXRATE 0xf 1466#define BOFDMTXRESERVED 0x10 1467#define BOFDMTXLENGTH 0x1ffe0 1468#define BOFDMTXPARITY 0x20000 1469#define BTXHTSIG1 0xffffff 1470#define BTXHTMCSRATE 0x7f 1471#define BTXHTBW 0x80 1472#define BTXHTLENGTH 0xffff00 1473#define BTXHTSIG2 0xffffff 1474#define BTXHTSMOOTHING 0x1 1475#define BTXHTSOUNDING 0x2 1476#define BTXHTRESERVED 0x4 1477#define BTXHTAGGREATION 0x8 1478#define BTXHTSTBC 0x30 1479#define BTXHTADVANCECODING 0x40 1480#define BTXHTSHORTGI 0x80 1481#define BTXHTNUMBERHT_LTF 0x300 1482#define BTXHTCRC8 0x3fc00 1483#define BCOUNTERRESET 0x10000 1484#define BNUMOFOFDMTX 0xffff 1485#define BNUMOFCCKTX 0xffff0000 1486#define BTXIDLEINTERVAL 0xffff 1487#define BOFDMSERVICE 0xffff0000 1488#define BTXMACHEADER 0xffffffff 1489#define BTXDATAINIT 0xff 1490#define BTXHTMODE 0x100 1491#define BTXDATATYPE 0x30000 1492#define BTXRANDOMSEED 0xffffffff 1493#define BCCKTXPREAMBLE 0x1 1494#define BCCKTXSFD 0xffff0000 1495#define BCCKTXSIG 0xff 1496#define BCCKTXSERVICE 0xff00 1497#define BCCKLENGTHEXT 0x8000 1498#define BCCKTXLENGHT 0xffff0000 1499#define BCCKTXCRC16 0xffff 1500#define BCCKTXSTATUS 0x1 1501#define BOFDMTXSTATUS 0x2 1502#define IS_BB_REG_OFFSET_92S(_offset) \ 1503 (((_offset) >= 0x800) && ((_offset) <= 0xfff)) 1504 1505#define BRFMOD 0x1 1506#define BJAPANMODE 0x2 1507#define BCCKTXSC 0x30 1508#define BCCKEN 0x1000000 1509#define BOFDMEN 0x2000000 1510 1511#define BOFDMRXADCPHASE 0x10000 1512#define BOFDMTXDACPHASE 0x40000 1513#define BXATXAGC 0x3f 1514 1515#define BXBTXAGC 0xf00 1516#define BXCTXAGC 0xf000 1517#define BXDTXAGC 0xf0000 1518 1519#define BPASTART 0xf0000000 1520#define BTRSTART 0x00f00000 1521#define BRFSTART 0x0000f000 1522#define BBBSTART 0x000000f0 1523#define BBBCCKSTART 0x0000000f 1524#define BPAEND 0xf 1525#define BTREND 0x0f000000 1526#define BRFEND 0x000f0000 1527#define BCCAMASK 0x000000f0 1528#define BR2RCCAMASK 0x00000f00 1529#define BHSSI_R2TDELAY 0xf8000000 1530#define BHSSI_T2RDELAY 0xf80000 1531#define BCONTXHSSI 0x400 1532#define BIGFROMCCK 0x200 1533#define BAGCADDRESS 0x3f 1534#define BRXHPTX 0x7000 1535#define BRXHP2RX 0x38000 1536#define BRXHPCCKINI 0xc0000 1537#define BAGCTXCODE 0xc00000 1538#define BAGCRXCODE 0x300000 1539 1540#define B3WIREDATALENGTH 0x800 1541#define B3WIREADDREAALENGTH 0x400 1542 1543#define B3WIRERFPOWERDOWN 0x1 1544#define B5GPAPEPOLARITY 0x40000000 1545#define B2GPAPEPOLARITY 0x80000000 1546#define BRFSW_TXDEFAULTANT 0x3 1547#define BRFSW_TXOPTIONANT 0x30 1548#define BRFSW_RXDEFAULTANT 0x300 1549#define BRFSW_RXOPTIONANT 0x3000 1550#define BRFSI_3WIREDATA 0x1 1551#define BRFSI_3WIRECLOCK 0x2 1552#define BRFSI_3WIRELOAD 0x4 1553#define BRFSI_3WIRERW 0x8 1554#define BRFSI_3WIRE 0xf 1555 1556#define BRFSI_RFENV 0x10 1557 1558#define BRFSI_TRSW 0x20 1559#define BRFSI_TRSWB 0x40 1560#define BRFSI_ANTSW 0x100 1561#define BRFSI_ANTSWB 0x200 1562#define BRFSI_PAPE 0x400 1563#define BRFSI_PAPE5G 0x800 1564#define BBANDSELECT 0x1 1565#define BHTSIG2_GI 0x80 1566#define BHTSIG2_SMOOTHING 0x01 1567#define BHTSIG2_SOUNDING 0x02 1568#define BHTSIG2_AGGREATON 0x08 1569#define BHTSIG2_STBC 0x30 1570#define BHTSIG2_ADVCODING 0x40 1571#define BHTSIG2_NUMOFHTLTF 0x300 1572#define BHTSIG2_CRC8 0x3fc 1573#define BHTSIG1_MCS 0x7f 1574#define BHTSIG1_BANDWIDTH 0x80 1575#define BHTSIG1_HTLENGTH 0xffff 1576#define BLSIG_RATE 0xf 1577#define BLSIG_RESERVED 0x10 1578#define BLSIG_LENGTH 0x1fffe 1579#define BLSIG_PARITY 0x20 1580#define BCCKRXPHASE 0x4 1581 1582#define BLSSIREADADDRESS 0x7f800000 1583#define BLSSIREADEDGE 0x80000000 1584 1585#define BLSSIREADBACKDATA 0xfffff 1586 1587#define BLSSIREADOKFLAG 0x1000 1588#define BCCKSAMPLERATE 0x8 1589#define BREGULATOR0STANDBY 0x1 1590#define BREGULATORPLLSTANDBY 0x2 1591#define BREGULATOR1STANDBY 0x4 1592#define BPLLPOWERUP 0x8 1593#define BDPLLPOWERUP 0x10 1594#define BDA10POWERUP 0x20 1595#define BAD7POWERUP 0x200 1596#define BDA6POWERUP 0x2000 1597#define BXTALPOWERUP 0x4000 1598#define B40MDCLKPOWERUP 0x8000 1599#define BDA6DEBUGMODE 0x20000 1600#define BDA6SWING 0x380000 1601 1602#define BADCLKPHASE 0x4000000 1603#define B80MCLKDELAY 0x18000000 1604#define BAFEWATCHDOGENABLE 0x20000000 1605 1606#define BXTALCAP01 0xc0000000 1607#define BXTALCAP23 0x3 1608#define BXTALCAP92X 0x0f000000 1609#define BXTALCAP 0x0f000000 1610 1611#define BINTDIFCLKENABLE 0x400 1612#define BEXTSIGCLKENABLE 0x800 1613#define BBANDGAP_MBIAS_POWERUP 0x10000 1614#define BAD11SH_GAIN 0xc0000 1615#define BAD11NPUT_RANGE 0x700000 1616#define BAD110P_CURRENT 0x3800000 1617#define BLPATH_LOOPBACK 0x4000000 1618#define BQPATH_LOOPBACK 0x8000000 1619#define BAFE_LOOPBACK 0x10000000 1620#define BDA10_SWING 0x7e0 1621#define BDA10_REVERSE 0x800 1622#define BDA_CLK_SOURCE 0x1000 1623#define BDA7INPUT_RANGE 0x6000 1624#define BDA7_GAIN 0x38000 1625#define BDA7OUTPUT_CM_MODE 0x40000 1626#define BDA7INPUT_CM_MODE 0x380000 1627#define BDA7CURRENT 0xc00000 1628#define BREGULATOR_ADJUST 0x7000000 1629#define BAD11POWERUP_ATTX 0x1 1630#define BDA10PS_ATTX 0x10 1631#define BAD11POWERUP_ATRX 0x100 1632#define BDA10PS_ATRX 0x1000 1633#define BCCKRX_AGC_FORMAT 0x200 1634#define BPSDFFT_SAMPLE_POINT 0xc000 1635#define BPSD_AVERAGE_NUM 0x3000 1636#define BIQPATH_CONTROL 0xc00 1637#define BPSD_FREQ 0x3ff 1638#define BPSD_ANTENNA_PATH 0x30 1639#define BPSD_IQ_SWITCH 0x40 1640#define BPSD_RX_TRIGGER 0x400000 1641#define BPSD_TX_TRIGGER 0x80000000 1642#define BPSD_SINE_TONE_SCALE 0x7f000000 1643#define BPSD_REPORT 0xffff 1644 1645#define BOFDM_TXSC 0x30000000 1646#define BCCK_TXON 0x1 1647#define BOFDM_TXON 0x2 1648#define BDEBUG_PAGE 0xfff 1649#define BDEBUG_ITEM 0xff 1650#define BANTL 0x10 1651#define BANT_NONHT 0x100 1652#define BANT_HT1 0x1000 1653#define BANT_HT2 0x10000 1654#define BANT_HT1S1 0x100000 1655#define BANT_NONHTS1 0x1000000 1656 1657#define BCCK_BBMODE 0x3 1658#define BCCK_TXPOWERSAVING 0x80 1659#define BCCK_RXPOWERSAVING 0x40 1660 1661#define BCCK_SIDEBAND 0x10 1662 1663#define BCCK_SCRAMBLE 0x8 1664#define BCCK_ANTDIVERSITY 0x8000 1665#define BCCK_CARRIER_RECOVERY 0x4000 1666#define BCCK_TXRATE 0x3000 1667#define BCCK_DCCANCEL 0x0800 1668#define BCCK_ISICANCEL 0x0400 1669#define BCCK_MATCH_FILTER 0x0200 1670#define BCCK_EQUALIZER 0x0100 1671#define BCCK_PREAMBLE_DETECT 0x800000 1672#define BCCK_FAST_FALSECCA 0x400000 1673#define BCCK_CH_ESTSTART 0x300000 1674#define BCCK_CCA_COUNT 0x080000 1675#define BCCK_CS_LIM 0x070000 1676#define BCCK_BIST_MODE 0x80000000 1677#define BCCK_CCAMASK 0x40000000 1678#define BCCK_TX_DAC_PHASE 0x4 1679#define BCCK_RX_ADC_PHASE 0x20000000 1680#define BCCKR_CP_MODE 0x0100 1681#define BCCK_TXDC_OFFSET 0xf0 1682#define BCCK_RXDC_OFFSET 0xf 1683#define BCCK_CCA_MODE 0xc000 1684#define BCCK_FALSECS_LIM 0x3f00 1685#define BCCK_CS_RATIO 0xc00000 1686#define BCCK_CORGBIT_SEL 0x300000 1687#define BCCK_PD_LIM 0x0f0000 1688#define BCCK_NEWCCA 0x80000000 1689#define BCCK_RXHP_OF_IG 0x8000 1690#define BCCK_RXIG 0x7f00 1691#define BCCK_LNA_POLARITY 0x800000 1692#define BCCK_RX1ST_BAIN 0x7f0000 1693#define BCCK_RF_EXTEND 0x20000000 1694#define BCCK_RXAGC_SATLEVEL 0x1f000000 1695#define BCCK_RXAGC_SATCOUNT 0xe0 1696#define BCCK_FIXED_RXAGC 0x8000 1697#define BCCK_ANTENNA_POLARITY 0x2000 1698#define BCCK_TXFILTER_TYPE 0x0c00 1699#define BCCK_RXAGC_REPORTTYPE 0x0300 1700#define BCCK_RXDAGC_EN 0x80000000 1701#define BCCK_RXDAGC_PERIOD 0x20000000 1702#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1703#define BCCK_TIMING_RECOVERY 0x800000 1704#define BCCK_TXC0 0x3f0000 1705#define BCCK_TXC1 0x3f000000 1706#define BCCK_TXC2 0x3f 1707#define BCCK_TXC3 0x3f00 1708#define BCCK_TXC4 0x3f0000 1709#define BCCK_TXC5 0x3f000000 1710#define BCCK_TXC6 0x3f 1711#define BCCK_TXC7 0x3f00 1712#define BCCK_DEBUGPORT 0xff0000 1713#define BCCK_DAC_DEBUG 0x0f000000 1714#define BCCK_FALSEALARM_ENABLE 0x8000 1715#define BCCK_FALSEALARM_READ 0x4000 1716#define BCCK_TRSSI 0x7f 1717#define BCCK_RXAGC_REPORT 0xfe 1718#define BCCK_RXREPORT_ANTSEL 0x80000000 1719#define BCCK_RXREPORT_MFOFF 0x40000000 1720#define BCCK_RXREPORT_SQLOSS 0x20000000 1721#define BCCK_RXREPORT_PKTLOSS 0x10000000 1722#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1723#define BCCK_RXREPORT_RATEERROR 0x04000000 1724#define BCCK_RXREPORT_RXRATE 0x03000000 1725#define BCCK_RXFA_COUNTER_LOWER 0xff 1726#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1727#define BCCK_RXHPAGC_START 0xe000 1728#define BCCK_RXHPAGC_FINAL 0x1c00 1729#define BCCK_RXFALSEALARM_ENABLE 0x8000 1730#define BCCK_FACOUNTER_FREEZE 0x4000 1731#define BCCK_TXPATH_SEL 0x10000000 1732#define BCCK_DEFAULT_RXPATH 0xc000000 1733#define BCCK_OPTION_RXPATH 0x3000000 1734 1735#define BNUM_OFSTF 0x3 1736#define BSHIFT_L 0xc0 1737#define BGI_TH 0xc 1738#define BRXPATH_A 0x1 1739#define BRXPATH_B 0x2 1740#define BRXPATH_C 0x4 1741#define BRXPATH_D 0x8 1742#define BTXPATH_A 0x1 1743#define BTXPATH_B 0x2 1744#define BTXPATH_C 0x4 1745#define BTXPATH_D 0x8 1746#define BTRSSI_FREQ 0x200 1747#define BADC_BACKOFF 0x3000 1748#define BDFIR_BACKOFF 0xc000 1749#define BTRSSI_LATCH_PHASE 0x10000 1750#define BRX_LDC_OFFSET 0xff 1751#define BRX_QDC_OFFSET 0xff00 1752#define BRX_DFIR_MODE 0x1800000 1753#define BRX_DCNF_TYPE 0xe000000 1754#define BRXIQIMB_A 0x3ff 1755#define BRXIQIMB_B 0xfc00 1756#define BRXIQIMB_C 0x3f0000 1757#define BRXIQIMB_D 0xffc00000 1758#define BDC_DC_NOTCH 0x60000 1759#define BRXNB_NOTCH 0x1f000000 1760#define BPD_TH 0xf 1761#define BPD_TH_OPT2 0xc000 1762#define BPWED_TH 0x700 1763#define BIFMF_WIN_L 0x800 1764#define BPD_OPTION 0x1000 1765#define BMF_WIN_L 0xe000 1766#define BBW_SEARCH_L 0x30000 1767#define BWIN_ENH_L 0xc0000 1768#define BBW_TH 0x700000 1769#define BED_TH2 0x3800000 1770#define BBW_OPTION 0x4000000 1771#define BRADIO_TH 0x18000000 1772#define BWINDOW_L 0xe0000000 1773#define BSBD_OPTION 0x1 1774#define BFRAME_TH 0x1c 1775#define BFS_OPTION 0x60 1776#define BDC_SLOPE_CHECK 0x80 1777#define BFGUARD_COUNTER_DC_L 0xe00 1778#define BFRAME_WEIGHT_SHORT 0x7000 1779#define BSUB_TUNE 0xe00000 1780#define BFRAME_DC_LENGTH 0xe000000 1781#define BSBD_START_OFFSET 0x30000000 1782#define BFRAME_TH_2 0x7 1783#define BFRAME_GI2_TH 0x38 1784#define BGI2_SYNC_EN 0x40 1785#define BSARCH_SHORT_EARLY 0x300 1786#define BSARCH_SHORT_LATE 0xc00 1787#define BSARCH_GI2_LATE 0x70000 1788#define BCFOANTSUM 0x1 1789#define BCFOACC 0x2 1790#define BCFOSTARTOFFSET 0xc 1791#define BCFOLOOPBACK 0x70 1792#define BCFOSUMWEIGHT 0x80 1793#define BDAGCENABLE 0x10000 1794#define BTXIQIMB_A 0x3ff 1795#define BTXIQIMB_b 0xfc00 1796#define BTXIQIMB_C 0x3f0000 1797#define BTXIQIMB_D 0xffc00000 1798#define BTXIDCOFFSET 0xff 1799#define BTXIQDCOFFSET 0xff00 1800#define BTXDFIRMODE 0x10000 1801#define BTXPESUDO_NOISEON 0x4000000 1802#define BTXPESUDO_NOISE_A 0xff 1803#define BTXPESUDO_NOISE_B 0xff00 1804#define BTXPESUDO_NOISE_C 0xff0000 1805#define BTXPESUDO_NOISE_D 0xff000000 1806#define BCCA_DROPOPTION 0x20000 1807#define BCCA_DROPTHRES 0xfff00000 1808#define BEDCCA_H 0xf 1809#define BEDCCA_L 0xf0 1810#define BLAMBDA_ED 0x300 1811#define BRX_INITIALGAIN 0x7f 1812#define BRX_ANTDIV_EN 0x80 1813#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1814#define BRX_HIGHPOWER_FLOW 0x8000 1815#define BRX_AGC_FREEZE_THRES 0xc0000 1816#define BRX_FREEZESTEP_AGC1 0x300000 1817#define BRX_FREEZESTEP_AGC2 0xc00000 1818#define BRX_FREEZESTEP_AGC3 0x3000000 1819#define BRX_FREEZESTEP_AGC0 0xc000000 1820#define BRXRSSI_CMP_EN 0x10000000 1821#define BRXQUICK_AGCEN 0x20000000 1822#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1823#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1824#define BRX_AGCSHIFT 0x7f 1825#define BTRSW_TRI_ONLY 0x80 1826#define BPOWER_THRES 0x300 1827#define BRXAGC_EN 0x1 1828#define BRXAGC_TOGETHER_EN 0x2 1829#define BRXAGC_MIN 0x4 1830#define BRXHP_INI 0x7 1831#define BRXHP_TRLNA 0x70 1832#define BRXHP_RSSI 0x700 1833#define BRXHP_BBP1 0x7000 1834#define BRXHP_BBP2 0x70000 1835#define BRXHP_BBP3 0x700000 1836#define BRSSI_H 0x7f0000 1837#define BRSSI_GEN 0x7f000000 1838#define BRXSETTLE_TRSW 0x7 1839#define BRXSETTLE_LNA 0x38 1840#define BRXSETTLE_RSSI 0x1c0 1841#define BRXSETTLE_BBP 0xe00 1842#define BRXSETTLE_RXHP 0x7000 1843#define BRXSETTLE_ANTSW_RSSI 0x38000 1844#define BRXSETTLE_ANTSW 0xc0000 1845#define BRXPROCESS_TIME_DAGC 0x300000 1846#define BRXSETTLE_HSSI 0x400000 1847#define BRXPROCESS_TIME_BBPPW 0x800000 1848#define BRXANTENNA_POWER_SHIFT 0x3000000 1849#define BRSSI_TABLE_SELECT 0xc000000 1850#define BRXHP_FINAL 0x7000000 1851#define BRXHPSETTLE_BBP 0x7 1852#define BRXHTSETTLE_HSSI 0x8 1853#define BRXHTSETTLE_RXHP 0x70 1854#define BRXHTSETTLE_BBPPW 0x80 1855#define BRXHTSETTLE_IDLE 0x300 1856#define BRXHTSETTLE_RESERVED 0x1c00 1857#define BRXHT_RXHP_EN 0x8000 1858#define BRXAGC_FREEZE_THRES 0x30000 1859#define BRXAGC_TOGETHEREN 0x40000 1860#define BRXHTAGC_MIN 0x80000 1861#define BRXHTAGC_EN 0x100000 1862#define BRXHTDAGC_EN 0x200000 1863#define BRXHT_RXHP_BBP 0x1c00000 1864#define BRXHT_RXHP_FINAL 0xe0000000 1865#define BRXPW_RADIO_TH 0x3 1866#define BRXPW_RADIO_EN 0x4 1867#define BRXMF_HOLD 0x3800 1868#define BRXPD_DELAY_TH1 0x38 1869#define BRXPD_DELAY_TH2 0x1c0 1870#define BRXPD_DC_COUNT_MAX 0x600 1871#define BRXPD_DELAY_TH 0x8000 1872#define BRXPROCESS_DELAY 0xf0000 1873#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1874#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1875#define BRXSGI_GUARD_L 0xc000000 1876#define BRXSGI_SEARCH_L 0x30000000 1877#define BRXSGI_TH 0xc0000000 1878#define BDFSCNT0 0xff 1879#define BDFSCNT1 0xff00 1880#define BDFSFLAG 0xf0000 1881#define BMF_WEIGHT_SUM 0x300000 1882#define BMINIDX_TH 0x7f000000 1883#define BDAFORMAT 0x40000 1884#define BTXCH_EMU_ENABLE 0x01000000 1885#define BTRSW_ISOLATION_A 0x7f 1886#define BTRSW_ISOLATION_B 0x7f00 1887#define BTRSW_ISOLATION_C 0x7f0000 1888#define BTRSW_ISOLATION_D 0x7f000000 1889#define BEXT_LNA_GAIN 0x7c00 1890 1891#define BSTBC_EN 0x4 1892#define BANTENNA_MAPPING 0x10 1893#define BNSS 0x20 1894#define BCFO_ANTSUM_ID 0x200 1895#define BPHY_COUNTER_RESET 0x8000000 1896#define BCFO_REPORT_GET 0x4000000 1897#define BOFDM_CONTINUE_TX 0x10000000 1898#define BOFDM_SINGLE_CARRIER 0x20000000 1899#define BOFDM_SINGLE_TONE 0x40000000 1900#define BHT_DETECT 0x100 1901#define BCFOEN 0x10000 1902#define BCFOVALUE 0xfff00000 1903#define BSIGTONE_RE 0x3f 1904#define BSIGTONE_IM 0x7f00 1905#define BCOUNTER_CCA 0xffff 1906#define BCOUNTER_PARITYFAIL 0xffff0000 1907#define BCOUNTER_RATEILLEGAL 0xffff 1908#define BCOUNTER_CRC8FAIL 0xffff0000 1909#define BCOUNTER_MCSNOSUPPORT 0xffff 1910#define BCOUNTER_FASTSYNC 0xffff 1911#define BSHORTCFO 0xfff 1912#define BSHORTCFOT_LENGTH 12 1913#define BSHORTCFOF_LENGTH 11 1914#define BLONGCFO 0x7ff 1915#define BLONGCFOT_LENGTH 11 1916#define BLONGCFOF_LENGTH 11 1917#define BTAILCFO 0x1fff 1918#define BTAILCFOT_LENGTH 13 1919#define BTAILCFOF_LENGTH 12 1920#define BNOISE_EN_PWDB 0xffff 1921#define BCC_POWER_DB 0xffff0000 1922#define BMOISE_PWDB 0xffff 1923#define BPOWERMEAST_LENGTH 10 1924#define BPOWERMEASF_LENGTH 3 1925#define BRX_HT_BW 0x1 1926#define BRXSC 0x6 1927#define BRX_HT 0x8 1928#define BNB_INTF_DET_ON 0x1 1929#define BINTF_WIN_LEN_CFG 0x30 1930#define BNB_INTF_TH_CFG 0x1c0 1931#define BRFGAIN 0x3f 1932#define BTABLESEL 0x40 1933#define BTRSW 0x80 1934#define BRXSNR_A 0xff 1935#define BRXSNR_B 0xff00 1936#define BRXSNR_C 0xff0000 1937#define BRXSNR_D 0xff000000 1938#define BSNR_EVMT_LENGTH 8 1939#define BSNR_EVMF_LENGTH 1 1940#define BCSI1ST 0xff 1941#define BCSI2ND 0xff00 1942#define BRXEVM1ST 0xff0000 1943#define BRXEVM2ND 0xff000000 1944#define BSIGEVM 0xff 1945#define BPWDB 0xff00 1946#define BSGIEN 0x10000 1947 1948#define BSFACTOR_QMA1 0xf 1949#define BSFACTOR_QMA2 0xf0 1950#define BSFACTOR_QMA3 0xf00 1951#define BSFACTOR_QMA4 0xf000 1952#define BSFACTOR_QMA5 0xf0000 1953#define BSFACTOR_QMA6 0xf0000 1954#define BSFACTOR_QMA7 0xf00000 1955#define BSFACTOR_QMA8 0xf000000 1956#define BSFACTOR_QMA9 0xf0000000 1957#define BCSI_SCHEME 0x100000 1958 1959#define BNOISE_LVL_TOP_SET 0x3 1960#define BCHSMOOTH 0x4 1961#define BCHSMOOTH_CFG1 0x38 1962#define BCHSMOOTH_CFG2 0x1c0 1963#define BCHSMOOTH_CFG3 0xe00 1964#define BCHSMOOTH_CFG4 0x7000 1965#define BMRCMODE 0x800000 1966#define BTHEVMCFG 0x7000000 1967 1968#define BLOOP_FIT_TYPE 0x1 1969#define BUPD_CFO 0x40 1970#define BUPD_CFO_OFFDATA 0x80 1971#define BADV_UPD_CFO 0x100 1972#define BADV_TIME_CTRL 0x800 1973#define BUPD_CLKO 0x1000 1974#define BFC 0x6000 1975#define BTRACKING_MODE 0x8000 1976#define BPHCMP_ENABLE 0x10000 1977#define BUPD_CLKO_LTF 0x20000 1978#define BCOM_CH_CFO 0x40000 1979#define BCSI_ESTI_MODE 0x80000 1980#define BADV_UPD_EQZ 0x100000 1981#define BUCHCFG 0x7000000 1982#define BUPDEQZ 0x8000000 1983 1984#define BRX_PESUDO_NOISE_ON 0x20000000 1985#define BRX_PESUDO_NOISE_A 0xff 1986#define BRX_PESUDO_NOISE_B 0xff00 1987#define BRX_PESUDO_NOISE_C 0xff0000 1988#define BRX_PESUDO_NOISE_D 0xff000000 1989#define BRX_PESUDO_NOISESTATE_A 0xffff 1990#define BRX_PESUDO_NOISESTATE_B 0xffff0000 1991#define BRX_PESUDO_NOISESTATE_C 0xffff 1992#define BRX_PESUDO_NOISESTATE_D 0xffff0000 1993 1994#define BZEBRA1_HSSIENABLE 0x8 1995#define BZEBRA1_TRXCONTROL 0xc00 1996#define BZEBRA1_TRXGAINSETTING 0x07f 1997#define BZEBRA1_RXCOUNTER 0xc00 1998#define BZEBRA1_TXCHANGEPUMP 0x38 1999#define BZEBRA1_RXCHANGEPUMP 0x7 2000#define BZEBRA1_CHANNEL_NUM 0xf80
2001#define BZEBRA1_TXLPFBW 0x400 2002#define BZEBRA1_RXLPFBW 0x600 2003 2004#define BRTL8256REG_MODE_CTRL1 0x100 2005#define BRTL8256REG_MODE_CTRL0 0x40 2006#define BRTL8256REG_TXLPFBW 0x18 2007#define BRTL8256REG_RXLPFBW 0x600 2008 2009#define BRTL8258_TXLPFBW 0xc 2010#define BRTL8258_RXLPFBW 0xc00 2011#define BRTL8258_RSSILPFBW 0xc0 2012 2013#define BBYTE0 0x1 2014#define BBYTE1 0x2 2015#define BBYTE2 0x4 2016#define BBYTE3 0x8 2017#define BWORD0 0x3 2018#define BWORD1 0xc 2019#define BWORD 0xf 2020 2021#define BENABLE 0x1 2022#define BDISABLE 0x0 2023 2024#define LEFT_ANTENNA 0x0 2025#define RIGHT_ANTENNA 0x1 2026 2027#define TCHECK_TXSTATUS 500 2028#define TUPDATE_RXCOUNTER 100 2029 2030#endif 2031