linux/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
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   1/* Copyright (C) 2016 Broadcom Corporation
   2 *
   3 * This program is free software; you can redistribute it and/or
   4 * modify it under the terms of the GNU General Public License as
   5 * published by the Free Software Foundation version 2.
   6 *
   7 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   8 * kind, whether express or implied; without even the implied warranty
   9 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10 * GNU General Public License for more details.
  11 *
  12 * This file contains the Northstar2 IOMUX driver that supports group
  13 * based PINMUX configuration. The PWM is functional only when the
  14 * corresponding mfio pin group is selected as gpio.
  15 */
  16
  17#include <linux/err.h>
  18#include <linux/io.h>
  19#include <linux/of.h>
  20#include <linux/pinctrl/pinconf.h>
  21#include <linux/pinctrl/pinconf-generic.h>
  22#include <linux/pinctrl/pinctrl.h>
  23#include <linux/pinctrl/pinmux.h>
  24#include <linux/platform_device.h>
  25#include <linux/slab.h>
  26
  27#include "../core.h"
  28#include "../pinctrl-utils.h"
  29
  30#define NS2_NUM_IOMUX                   19
  31#define NS2_NUM_PWM_MUX                 4
  32
  33#define NS2_PIN_MUX_BASE0               0x00
  34#define NS2_PIN_MUX_BASE1               0x01
  35#define NS2_PIN_CONF_BASE               0x02
  36#define NS2_MUX_PAD_FUNC1_OFFSET        0x04
  37
  38#define NS2_PIN_SRC_MASK                0x01
  39#define NS2_PIN_PULL_MASK               0x03
  40#define NS2_PIN_DRIVE_STRENGTH_MASK     0x07
  41
  42#define NS2_PIN_PULL_UP                 0x01
  43#define NS2_PIN_PULL_DOWN               0x02
  44
  45#define NS2_PIN_INPUT_EN_MASK           0x01
  46
  47/*
  48 * Northstar2 IOMUX register description
  49 *
  50 * @base: base address number
  51 * @offset: register offset for mux configuration of a group
  52 * @shift: bit shift for mux configuration of a group
  53 * @mask: mask bits
  54 * @alt: alternate function to set to
  55 */
  56struct ns2_mux {
  57        unsigned int base;
  58        unsigned int offset;
  59        unsigned int shift;
  60        unsigned int mask;
  61        unsigned int alt;
  62};
  63
  64/*
  65 * Keep track of Northstar2 IOMUX configuration and prevent double
  66 * configuration
  67 *
  68 * @ns2_mux: Northstar2 IOMUX register description
  69 * @is_configured: flag to indicate whether a mux setting has already
  70 * been configured
  71 */
  72struct ns2_mux_log {
  73        struct ns2_mux mux;
  74        bool is_configured;
  75};
  76
  77/*
  78 * Group based IOMUX configuration
  79 *
  80 * @name: name of the group
  81 * @pins: array of pins used by this group
  82 * @num_pins: total number of pins used by this group
  83 * @mux: Northstar2 group based IOMUX configuration
  84 */
  85struct ns2_pin_group {
  86        const char *name;
  87        const unsigned int *pins;
  88        const unsigned int num_pins;
  89        const struct ns2_mux mux;
  90};
  91
  92/*
  93 * Northstar2 mux function and supported pin groups
  94 *
  95 * @name: name of the function
  96 * @groups: array of groups that can be supported by this function
  97 * @num_groups: total number of groups that can be supported by function
  98 */
  99struct ns2_pin_function {
 100        const char *name;
 101        const char * const *groups;
 102        const unsigned int num_groups;
 103};
 104
 105/*
 106 * Northstar2 IOMUX pinctrl core
 107 *
 108 * @pctl: pointer to pinctrl_dev
 109 * @dev: pointer to device
 110 * @base0: first IOMUX register base
 111 * @base1: second IOMUX register base
 112 * @pinconf_base: configuration register base
 113 * @groups: pointer to array of groups
 114 * @num_groups: total number of groups
 115 * @functions: pointer to array of functions
 116 * @num_functions: total number of functions
 117 * @mux_log: pointer to the array of mux logs
 118 * @lock: lock to protect register access
 119 */
 120struct ns2_pinctrl {
 121        struct pinctrl_dev *pctl;
 122        struct device *dev;
 123        void __iomem *base0;
 124        void __iomem *base1;
 125        void __iomem *pinconf_base;
 126
 127        const struct ns2_pin_group *groups;
 128        unsigned int num_groups;
 129
 130        const struct ns2_pin_function *functions;
 131        unsigned int num_functions;
 132
 133        struct ns2_mux_log *mux_log;
 134
 135        spinlock_t lock;
 136};
 137
 138/*
 139 * Pin configuration info
 140 *
 141 * @base: base address number
 142 * @offset: register offset from base
 143 * @src_shift: slew rate control bit shift in the register
 144 * @input_en: input enable control bit shift
 145 * @pull_shift: pull-up/pull-down control bit shift in the register
 146 * @drive_shift: drive strength control bit shift in the register
 147 */
 148struct ns2_pinconf {
 149        unsigned int base;
 150        unsigned int offset;
 151        unsigned int src_shift;
 152        unsigned int input_en;
 153        unsigned int pull_shift;
 154        unsigned int drive_shift;
 155};
 156
 157/*
 158 * Description of a pin in Northstar2
 159 *
 160 * @pin: pin number
 161 * @name: pin name
 162 * @pin_conf: pin configuration structure
 163 */
 164struct ns2_pin {
 165        unsigned int pin;
 166        char *name;
 167        struct ns2_pinconf pin_conf;
 168};
 169
 170#define NS2_PIN_DESC(p, n, b, o, s, i, pu, d)   \
 171{                                               \
 172        .pin = p,                               \
 173        .name = n,                              \
 174        .pin_conf = {                           \
 175                .base = b,                      \
 176                .offset = o,                    \
 177                .src_shift = s,                 \
 178                .input_en = i,                  \
 179                .pull_shift = pu,               \
 180                .drive_shift = d,               \
 181        }                                       \
 182}
 183
 184/*
 185 * List of pins in Northstar2
 186 */
 187static struct ns2_pin ns2_pins[] = {
 188        NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
 189        NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
 190        NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
 191        NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
 192        NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
 193        NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
 194        NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
 195        NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
 196        NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
 197        NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
 198        NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
 199        NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
 200        NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
 201        NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
 202        NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
 203        NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
 204        NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
 205        NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
 206        NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
 207        NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
 208        NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
 209        NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
 210        NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
 211        NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
 212        NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
 213        NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
 214        NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
 215        NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
 216        NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
 217        NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
 218        NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
 219        NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
 220        NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
 221        NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
 222        NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
 223        NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
 224        NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
 225        NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
 226        NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
 227        NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
 228        NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
 229        NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
 230        NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
 231        NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
 232        NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
 233        NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
 234        NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
 235        NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
 236        NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
 237        NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
 238        NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
 239        NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
 240        NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
 241        NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
 242        NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
 243        NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
 244        NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
 245        NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
 246        NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
 247        NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
 248        NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
 249        NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
 250        NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
 251        NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
 252        NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
 253        NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
 254        NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
 255        NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
 256        NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
 257        NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
 258        NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
 259        NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
 260        NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
 261        NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
 262        NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
 263        NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
 264        NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
 265        NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
 266        NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
 267        NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
 268        NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
 269        NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
 270        NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
 271        NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
 272        NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
 273        NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
 274        NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
 275        NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
 276        NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
 277        NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
 278        NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
 279        NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
 280        NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
 281        NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
 282        NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
 283        NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
 284        NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
 285        NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
 286        NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
 287        NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
 288        NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
 289        NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
 290        NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
 291        NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
 292        NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
 293        NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
 294        NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
 295        NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
 296        NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
 297        NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
 298        NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
 299        NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
 300        NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
 301        NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
 302        NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
 303        NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
 304        NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
 305        NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
 306        NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
 307};
 308
 309/*
 310 * List of groups of pins
 311 */
 312
 313static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
 314        11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
 315static const unsigned int nor_data_pins[] =  {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
 316        10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
 317
 318static const unsigned int gpio_0_1_pins[] = {24, 25};
 319static const unsigned int pwm_0_pins[] = {24};
 320static const unsigned int pwm_1_pins[] = {25};
 321
 322static const unsigned int uart1_ext_clk_pins[] = {26};
 323static const unsigned int nor_adv_pins[] = {26};
 324
 325static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
 326static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
 327static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
 328static const unsigned int pwm_2_pins[] = {27};
 329static const unsigned int pwm_3_pins[] = {28};
 330
 331static const unsigned int gpio_6_7_pins[] = {31, 32};
 332static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
 333static const unsigned int nor_addr_4_5_pins[] = {31, 32};
 334
 335static const unsigned int gpio_8_9_pins[] = {33, 34};
 336static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
 337static const unsigned int nor_addr_6_7_pins[] = {33, 34};
 338
 339static const unsigned int gpio_10_11_pins[] = {35, 36};
 340static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
 341static const unsigned int nor_addr_8_9_pins[] = {35, 36};
 342
 343static const unsigned int gpio_12_13_pins[] = {37, 38};
 344static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
 345static const unsigned int nor_addr_10_11_pins[] = {37, 38};
 346
 347static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
 348static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
 349static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
 350
 351static const unsigned int gpio_18_19_pins[] = {43, 44};
 352static const unsigned int uart0_rts_cts_pins[] = {43, 44};
 353
 354static const unsigned int gpio_20_21_pins[] = {45, 46};
 355static const unsigned int uart0_in_out_pins[] = {45, 46};
 356
 357static const unsigned int gpio_22_23_pins[] = {47, 48};
 358static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
 359
 360static const unsigned int gpio_24_25_pins[] = {49, 50};
 361static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
 362
 363static const unsigned int gpio_26_27_pins[] = {51, 52};
 364static const unsigned int uart1_rts_cts_pins[] = {51, 52};
 365
 366static const unsigned int gpio_28_29_pins[] = {53, 54};
 367static const unsigned int uart1_in_out_pins[] = {53, 54};
 368
 369static const unsigned int gpio_30_31_pins[] = {55, 56};
 370static const unsigned int uart2_rts_cts_pins[] = {55, 56};
 371
 372#define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al)  \
 373{                                                       \
 374        .name = __stringify(group_name) "_grp",         \
 375        .pins = group_name ## _pins,                    \
 376        .num_pins = ARRAY_SIZE(group_name ## _pins),    \
 377        .mux = {                                        \
 378                .base = ba,                             \
 379                .offset = off,                          \
 380                .shift = sh,                            \
 381                .mask = ma,                             \
 382                .alt = al,                              \
 383        }                                               \
 384}
 385
 386/*
 387 * List of Northstar2 pin groups
 388 */
 389static const struct ns2_pin_group ns2_pin_groups[] = {
 390        NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
 391        NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
 392        NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
 393
 394        NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
 395        NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
 396
 397        NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
 398        NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
 399        NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
 400
 401        NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
 402        NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
 403        NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
 404
 405        NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
 406        NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
 407        NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
 408
 409        NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
 410        NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
 411        NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
 412
 413        NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
 414        NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
 415        NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
 416
 417        NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
 418        NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
 419        NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
 420
 421        NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
 422        NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
 423
 424        NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
 425        NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
 426
 427        NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
 428        NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
 429
 430        NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
 431        NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
 432
 433        NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
 434        NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
 435
 436        NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
 437        NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
 438
 439        NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
 440        NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
 441
 442        NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
 443        NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
 444        NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
 445        NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
 446};
 447
 448/*
 449 * List of groups supported by functions
 450 */
 451
 452static const char * const nand_grps[] = {"nand_grp"};
 453
 454static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
 455        "nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
 456        "nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
 457
 458static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
 459        "gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
 460        "gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
 461        "gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
 462        "gpio_30_31_grp"};
 463
 464static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
 465        "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
 466        "pcie_a2_clk_wak_grp"};
 467
 468static const char * const uart0_grps[] = {"uart0_modem_grp",
 469        "uart0_rts_cts_grp", "uart0_in_out_grp"};
 470
 471static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
 472        "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
 473        "uart1_in_out_grp"};
 474
 475static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
 476
 477static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
 478        "pwm_2_grp", "pwm_3_grp"};
 479
 480#define NS2_PIN_FUNCTION(func)                          \
 481{                                                       \
 482        .name = #func,                                  \
 483        .groups = func ## _grps,                        \
 484        .num_groups = ARRAY_SIZE(func ## _grps),        \
 485}
 486
 487/*
 488 * List of supported functions
 489 */
 490static const struct ns2_pin_function ns2_pin_functions[] = {
 491        NS2_PIN_FUNCTION(nand),
 492        NS2_PIN_FUNCTION(nor),
 493        NS2_PIN_FUNCTION(gpio),
 494        NS2_PIN_FUNCTION(pcie),
 495        NS2_PIN_FUNCTION(uart0),
 496        NS2_PIN_FUNCTION(uart1),
 497        NS2_PIN_FUNCTION(uart2),
 498        NS2_PIN_FUNCTION(pwm),
 499};
 500
 501static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
 502{
 503        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 504
 505        return pinctrl->num_groups;
 506}
 507
 508static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
 509                                      unsigned int selector)
 510{
 511        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 512
 513        return pinctrl->groups[selector].name;
 514}
 515
 516static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
 517                              unsigned int selector, const unsigned int **pins,
 518                              unsigned int *num_pins)
 519{
 520        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 521
 522        *pins = pinctrl->groups[selector].pins;
 523        *num_pins = pinctrl->groups[selector].num_pins;
 524
 525        return 0;
 526}
 527
 528static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
 529                             struct seq_file *s, unsigned int offset)
 530{
 531        seq_printf(s, " %s", dev_name(pctrl_dev->dev));
 532}
 533
 534static const struct pinctrl_ops ns2_pinctrl_ops = {
 535        .get_groups_count = ns2_get_groups_count,
 536        .get_group_name = ns2_get_group_name,
 537        .get_group_pins = ns2_get_group_pins,
 538        .pin_dbg_show = ns2_pin_dbg_show,
 539        .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 540        .dt_free_map = pinctrl_utils_free_map,
 541};
 542
 543static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
 544{
 545        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 546
 547        return pinctrl->num_functions;
 548}
 549
 550static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
 551                                         unsigned int selector)
 552{
 553        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 554
 555        return pinctrl->functions[selector].name;
 556}
 557
 558static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
 559                                   unsigned int selector,
 560                                   const char * const **groups,
 561                                   unsigned int * const num_groups)
 562{
 563        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 564
 565        *groups = pinctrl->functions[selector].groups;
 566        *num_groups = pinctrl->functions[selector].num_groups;
 567
 568        return 0;
 569}
 570
 571static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
 572                          const struct ns2_pin_function *func,
 573                          const struct ns2_pin_group *grp,
 574                          struct ns2_mux_log *mux_log)
 575{
 576        const struct ns2_mux *mux = &grp->mux;
 577        int i;
 578        u32 val, mask;
 579        unsigned long flags;
 580        void __iomem *base_address;
 581
 582        for (i = 0; i < NS2_NUM_IOMUX; i++) {
 583                if ((mux->shift != mux_log[i].mux.shift) ||
 584                        (mux->base != mux_log[i].mux.base) ||
 585                        (mux->offset != mux_log[i].mux.offset))
 586                        continue;
 587
 588                /* if this is a new configuration, just do it! */
 589                if (!mux_log[i].is_configured)
 590                        break;
 591
 592                /*
 593                 * IOMUX has been configured previously and one is trying to
 594                 * configure it to a different function
 595                 */
 596                if (mux_log[i].mux.alt != mux->alt) {
 597                        dev_err(pinctrl->dev,
 598                                "double configuration error detected!\n");
 599                        dev_err(pinctrl->dev, "func:%s grp:%s\n",
 600                                func->name, grp->name);
 601                        return -EINVAL;
 602                }
 603
 604                return 0;
 605        }
 606        if (i == NS2_NUM_IOMUX)
 607                return -EINVAL;
 608
 609        mask = mux->mask;
 610        mux_log[i].mux.alt = mux->alt;
 611        mux_log[i].is_configured = true;
 612
 613        switch (mux->base) {
 614        case NS2_PIN_MUX_BASE0:
 615                base_address = pinctrl->base0;
 616                break;
 617
 618        case NS2_PIN_MUX_BASE1:
 619                base_address = pinctrl->base1;
 620                break;
 621
 622        default:
 623                return -EINVAL;
 624        }
 625
 626        spin_lock_irqsave(&pinctrl->lock, flags);
 627        val = readl(base_address + grp->mux.offset);
 628        val &= ~(mask << grp->mux.shift);
 629        val |= grp->mux.alt << grp->mux.shift;
 630        writel(val, (base_address + grp->mux.offset));
 631        spin_unlock_irqrestore(&pinctrl->lock, flags);
 632
 633        return 0;
 634}
 635
 636static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
 637                             unsigned int func_select, unsigned int grp_select)
 638{
 639        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
 640        const struct ns2_pin_function *func;
 641        const struct ns2_pin_group *grp;
 642
 643        if (grp_select >= pinctrl->num_groups ||
 644                func_select >= pinctrl->num_functions)
 645                return -EINVAL;
 646
 647        func = &pinctrl->functions[func_select];
 648        grp = &pinctrl->groups[grp_select];
 649
 650        dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
 651                func_select, func->name, grp_select, grp->name);
 652
 653        dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
 654                grp->mux.offset, grp->mux.shift, grp->mux.alt);
 655
 656        return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
 657}
 658
 659static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
 660                            u16 enable)
 661{
 662        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 663        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 664        unsigned long flags;
 665        u32 val;
 666        void __iomem *base_address;
 667
 668        base_address = pinctrl->pinconf_base;
 669        spin_lock_irqsave(&pinctrl->lock, flags);
 670        val = readl(base_address + pin_data->pin_conf.offset);
 671        val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
 672
 673        if (!enable)
 674                val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
 675
 676        writel(val, (base_address + pin_data->pin_conf.offset));
 677        spin_unlock_irqrestore(&pinctrl->lock, flags);
 678
 679        dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
 680        return 0;
 681}
 682
 683static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
 684{
 685        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 686        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 687        unsigned long flags;
 688        int enable;
 689
 690        spin_lock_irqsave(&pinctrl->lock, flags);
 691        enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
 692        enable = (enable >> pin_data->pin_conf.input_en) &
 693                        NS2_PIN_INPUT_EN_MASK;
 694        spin_unlock_irqrestore(&pinctrl->lock, flags);
 695
 696        if (!enable)
 697                enable = NS2_PIN_INPUT_EN_MASK;
 698        else
 699                enable = 0;
 700
 701        dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
 702        return enable;
 703}
 704
 705static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
 706                            u32 slew)
 707{
 708        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 709        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 710        unsigned long flags;
 711        u32 val;
 712        void __iomem *base_address;
 713
 714        base_address = pinctrl->pinconf_base;
 715        spin_lock_irqsave(&pinctrl->lock, flags);
 716        val = readl(base_address + pin_data->pin_conf.offset);
 717        val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
 718
 719        if (slew)
 720                val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
 721
 722        writel(val, (base_address + pin_data->pin_conf.offset));
 723        spin_unlock_irqrestore(&pinctrl->lock, flags);
 724
 725        dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
 726        return 0;
 727}
 728
 729static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
 730                            u16 *slew)
 731{
 732        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 733        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 734        unsigned long flags;
 735        u32 val;
 736
 737        spin_lock_irqsave(&pinctrl->lock, flags);
 738        val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
 739        *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
 740        spin_unlock_irqrestore(&pinctrl->lock, flags);
 741
 742        dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
 743        return 0;
 744}
 745
 746static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
 747                            bool pull_up, bool pull_down)
 748{
 749        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 750        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 751        unsigned long flags;
 752        u32 val;
 753        void __iomem *base_address;
 754
 755        base_address = pinctrl->pinconf_base;
 756        spin_lock_irqsave(&pinctrl->lock, flags);
 757        val = readl(base_address + pin_data->pin_conf.offset);
 758        val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
 759
 760        if (pull_up == true)
 761                val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
 762        if (pull_down == true)
 763                val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
 764        writel(val, (base_address + pin_data->pin_conf.offset));
 765        spin_unlock_irqrestore(&pinctrl->lock, flags);
 766
 767        dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
 768                pin, pull_up, pull_down);
 769        return 0;
 770}
 771
 772static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
 773                             unsigned int pin, bool *pull_up,
 774                             bool *pull_down)
 775{
 776        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 777        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 778        unsigned long flags;
 779        u32 val;
 780
 781        spin_lock_irqsave(&pinctrl->lock, flags);
 782        val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
 783        val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
 784        *pull_up = false;
 785        *pull_down = false;
 786
 787        if (val == NS2_PIN_PULL_UP)
 788                *pull_up = true;
 789
 790        if (val == NS2_PIN_PULL_DOWN)
 791                *pull_down = true;
 792        spin_unlock_irqrestore(&pinctrl->lock, flags);
 793}
 794
 795static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
 796                                u32 strength)
 797{
 798        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 799        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 800        u32 val;
 801        unsigned long flags;
 802        void __iomem *base_address;
 803
 804        /* make sure drive strength is supported */
 805        if (strength < 2 || strength > 16 || (strength % 2))
 806                return -ENOTSUPP;
 807
 808        base_address = pinctrl->pinconf_base;
 809        spin_lock_irqsave(&pinctrl->lock, flags);
 810        val = readl(base_address + pin_data->pin_conf.offset);
 811        val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
 812        val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
 813        writel(val, (base_address + pin_data->pin_conf.offset));
 814        spin_unlock_irqrestore(&pinctrl->lock, flags);
 815
 816        dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
 817                pin, strength);
 818        return 0;
 819}
 820
 821static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
 822                                 u16 *strength)
 823{
 824        struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
 825        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 826        u32 val;
 827        unsigned long flags;
 828
 829        spin_lock_irqsave(&pinctrl->lock, flags);
 830        val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
 831        *strength = (val >> pin_data->pin_conf.drive_shift) &
 832                                        NS2_PIN_DRIVE_STRENGTH_MASK;
 833        *strength = (*strength + 1) * 2;
 834        spin_unlock_irqrestore(&pinctrl->lock, flags);
 835
 836        dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
 837                pin, *strength);
 838        return 0;
 839}
 840
 841static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 842                              unsigned long *config)
 843{
 844        struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
 845        enum pin_config_param param = pinconf_to_config_param(*config);
 846        bool pull_up, pull_down;
 847        u16 arg = 0;
 848        int ret;
 849
 850        if (pin_data->pin_conf.base == -1)
 851                return -ENOTSUPP;
 852
 853        switch (param) {
 854        case PIN_CONFIG_BIAS_DISABLE:
 855                ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
 856                if ((pull_up == false) && (pull_down == false))
 857                        return 0;
 858                else
 859                        return -EINVAL;
 860
 861        case PIN_CONFIG_BIAS_PULL_UP:
 862                ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
 863                if (pull_up)
 864                        return 0;
 865                else
 866                        return -EINVAL;
 867
 868        case PIN_CONFIG_BIAS_PULL_DOWN:
 869                ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
 870                if (pull_down)
 871                        return 0;
 872                else
 873                        return -EINVAL;
 874
 875        case PIN_CONFIG_DRIVE_STRENGTH:
 876                ret = ns2_pin_get_strength(pctldev, pin, &arg);
 877                if (ret)
 878                        return ret;
 879                *config = pinconf_to_config_packed(param, arg);
 880                return 0;
 881
 882        case PIN_CONFIG_SLEW_RATE:
 883                ret = ns2_pin_get_slew(pctldev, pin, &arg);
 884                if (ret)
 885                        return ret;
 886                *config = pinconf_to_config_packed(param, arg);
 887                return 0;
 888
 889        case PIN_CONFIG_INPUT_ENABLE:
 890                ret = ns2_pin_get_enable(pctldev, pin);
 891                if (ret)
 892                        return 0;
 893                else
 894                        return -EINVAL;
 895
 896        default:
 897                return -ENOTSUPP;
 898        }
 899}
 900
 901static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
 902                              unsigned long *configs, unsigned int num_configs)
 903{
 904        struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
 905        enum pin_config_param param;
 906        unsigned int i;
 907        u32 arg;
 908        int ret = -ENOTSUPP;
 909
 910        if (pin_data->pin_conf.base == -1)
 911                return -ENOTSUPP;
 912
 913        for (i = 0; i < num_configs; i++) {
 914                param = pinconf_to_config_param(configs[i]);
 915                arg = pinconf_to_config_argument(configs[i]);
 916
 917                switch (param) {
 918                case PIN_CONFIG_BIAS_DISABLE:
 919                        ret = ns2_pin_set_pull(pctrldev, pin, false, false);
 920                        if (ret < 0)
 921                                goto out;
 922                        break;
 923
 924                case PIN_CONFIG_BIAS_PULL_UP:
 925                        ret = ns2_pin_set_pull(pctrldev, pin, true, false);
 926                        if (ret < 0)
 927                                goto out;
 928                        break;
 929
 930                case PIN_CONFIG_BIAS_PULL_DOWN:
 931                        ret = ns2_pin_set_pull(pctrldev, pin, false, true);
 932                        if (ret < 0)
 933                                goto out;
 934                        break;
 935
 936                case PIN_CONFIG_DRIVE_STRENGTH:
 937                        ret = ns2_pin_set_strength(pctrldev, pin, arg);
 938                        if (ret < 0)
 939                                goto out;
 940                        break;
 941
 942                case PIN_CONFIG_SLEW_RATE:
 943                        ret = ns2_pin_set_slew(pctrldev, pin, arg);
 944                        if (ret < 0)
 945                                goto out;
 946                        break;
 947
 948                case PIN_CONFIG_INPUT_ENABLE:
 949                        ret = ns2_pin_set_enable(pctrldev, pin, arg);
 950                        if (ret < 0)
 951                                goto out;
 952                        break;
 953
 954                default:
 955                        dev_err(pctrldev->dev, "invalid configuration\n");
 956                        return -ENOTSUPP;
 957                }
 958        }
 959out:
 960        return ret;
 961}
 962static const struct pinmux_ops ns2_pinmux_ops = {
 963        .get_functions_count = ns2_get_functions_count,
 964        .get_function_name = ns2_get_function_name,
 965        .get_function_groups = ns2_get_function_groups,
 966        .set_mux = ns2_pinmux_enable,
 967};
 968
 969static const struct pinconf_ops ns2_pinconf_ops = {
 970        .is_generic = true,
 971        .pin_config_get = ns2_pin_config_get,
 972        .pin_config_set = ns2_pin_config_set,
 973};
 974
 975static struct pinctrl_desc ns2_pinctrl_desc = {
 976        .name = "ns2-pinmux",
 977        .pctlops = &ns2_pinctrl_ops,
 978        .pmxops = &ns2_pinmux_ops,
 979        .confops = &ns2_pinconf_ops,
 980};
 981
 982static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
 983{
 984        struct ns2_mux_log *log;
 985        unsigned int i;
 986
 987        pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
 988                                        sizeof(struct ns2_mux_log),
 989                                        GFP_KERNEL);
 990        if (!pinctrl->mux_log)
 991                return -ENOMEM;
 992
 993        for (i = 0; i < NS2_NUM_IOMUX; i++)
 994                pinctrl->mux_log[i].is_configured = false;
 995        /* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
 996        log = &pinctrl->mux_log[0];
 997        log->mux.base = NS2_PIN_MUX_BASE0;
 998        log->mux.offset = 0;
 999        log->mux.shift = 31;
1000        log->mux.alt = 0;
1001
1002        /*
1003         * Groups 1 through 14 use two bits each in the
1004         * IOMUX_PAD_FUNCTION_1 register starting with
1005         * bit position 30.
1006         */
1007        for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
1008                log = &pinctrl->mux_log[i];
1009                log->mux.base = NS2_PIN_MUX_BASE0;
1010                log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
1011                log->mux.shift = 32 - (i * 2);
1012                log->mux.alt = 0;
1013        }
1014
1015        /*
1016         * Groups 15 through 18 use one bit each in the
1017         * AUX_SEL register.
1018         */
1019        for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
1020                log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1021                log->mux.base = NS2_PIN_MUX_BASE1;
1022                log->mux.offset = 0;
1023                log->mux.shift = i;
1024                log->mux.alt =  0;
1025        }
1026        return 0;
1027}
1028
1029static int ns2_pinmux_probe(struct platform_device *pdev)
1030{
1031        struct ns2_pinctrl *pinctrl;
1032        struct resource *res;
1033        int i, ret;
1034        struct pinctrl_pin_desc *pins;
1035        unsigned int num_pins = ARRAY_SIZE(ns2_pins);
1036
1037        pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1038        if (!pinctrl)
1039                return -ENOMEM;
1040
1041        pinctrl->dev = &pdev->dev;
1042        platform_set_drvdata(pdev, pinctrl);
1043        spin_lock_init(&pinctrl->lock);
1044
1045        pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1046        if (IS_ERR(pinctrl->base0))
1047                return PTR_ERR(pinctrl->base0);
1048
1049        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1050        if (!res)
1051                return -EINVAL;
1052        pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1053                                        resource_size(res));
1054        if (!pinctrl->base1) {
1055                dev_err(&pdev->dev, "unable to map I/O space\n");
1056                return -ENOMEM;
1057        }
1058
1059        pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1060        if (IS_ERR(pinctrl->pinconf_base))
1061                return PTR_ERR(pinctrl->pinconf_base);
1062
1063        ret = ns2_mux_log_init(pinctrl);
1064        if (ret) {
1065                dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
1066                return ret;
1067        }
1068
1069        pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
1070        if (!pins)
1071                return -ENOMEM;
1072
1073        for (i = 0; i < num_pins; i++) {
1074                pins[i].number = ns2_pins[i].pin;
1075                pins[i].name = ns2_pins[i].name;
1076                pins[i].drv_data = &ns2_pins[i];
1077        }
1078
1079        pinctrl->groups = ns2_pin_groups;
1080        pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1081        pinctrl->functions = ns2_pin_functions;
1082        pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1083        ns2_pinctrl_desc.pins = pins;
1084        ns2_pinctrl_desc.npins = num_pins;
1085
1086        pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1087                        pinctrl);
1088        if (IS_ERR(pinctrl->pctl)) {
1089                dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1090                return PTR_ERR(pinctrl->pctl);
1091        }
1092
1093        return 0;
1094}
1095
1096static const struct of_device_id ns2_pinmux_of_match[] = {
1097        {.compatible = "brcm,ns2-pinmux"},
1098        { }
1099};
1100
1101static struct platform_driver ns2_pinmux_driver = {
1102        .driver = {
1103                .name = "ns2-pinmux",
1104                .of_match_table = ns2_pinmux_of_match,
1105        },
1106        .probe = ns2_pinmux_probe,
1107};
1108
1109static int __init ns2_pinmux_init(void)
1110{
1111        return platform_driver_register(&ns2_pinmux_driver);
1112}
1113arch_initcall(ns2_pinmux_init);
1114