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7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/machine.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/reboot.h>
23#include <linux/pm.h>
24#include <linux/log2.h>
25#include <linux/qcom_scm.h>
26
27#include <linux/soc/qcom/irq.h>
28
29#include "../core.h"
30#include "../pinconf.h"
31#include "pinctrl-msm.h"
32#include "../pinctrl-utils.h"
33
34#define MAX_NR_GPIO 300
35#define MAX_NR_TILES 4
36#define PS_HOLD_OFFSET 0x820
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57
58struct msm_pinctrl {
59 struct device *dev;
60 struct pinctrl_dev *pctrl;
61 struct gpio_chip chip;
62 struct pinctrl_desc desc;
63 struct notifier_block restart_nb;
64
65 struct irq_chip irq_chip;
66 int irq;
67
68 bool intr_target_use_scm;
69
70 raw_spinlock_t lock;
71
72 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
73 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
74 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
75
76 const struct msm_pinctrl_soc_data *soc;
77 void __iomem *regs[MAX_NR_TILES];
78 u32 phys_base[MAX_NR_TILES];
79};
80
81#define MSM_ACCESSOR(name) \
82static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
83 const struct msm_pingroup *g) \
84{ \
85 return readl(pctrl->regs[g->tile] + g->name##_reg); \
86} \
87static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
88 const struct msm_pingroup *g) \
89{ \
90 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
91}
92
93MSM_ACCESSOR(ctl)
94MSM_ACCESSOR(io)
95MSM_ACCESSOR(intr_cfg)
96MSM_ACCESSOR(intr_status)
97MSM_ACCESSOR(intr_target)
98
99static int msm_get_groups_count(struct pinctrl_dev *pctldev)
100{
101 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
102
103 return pctrl->soc->ngroups;
104}
105
106static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
107 unsigned group)
108{
109 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110
111 return pctrl->soc->groups[group].name;
112}
113
114static int msm_get_group_pins(struct pinctrl_dev *pctldev,
115 unsigned group,
116 const unsigned **pins,
117 unsigned *num_pins)
118{
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120
121 *pins = pctrl->soc->groups[group].pins;
122 *num_pins = pctrl->soc->groups[group].npins;
123 return 0;
124}
125
126static const struct pinctrl_ops msm_pinctrl_ops = {
127 .get_groups_count = msm_get_groups_count,
128 .get_group_name = msm_get_group_name,
129 .get_group_pins = msm_get_group_pins,
130 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
131 .dt_free_map = pinctrl_utils_free_map,
132};
133
134static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
135{
136 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
137 struct gpio_chip *chip = &pctrl->chip;
138
139 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
140}
141
142static int msm_get_functions_count(struct pinctrl_dev *pctldev)
143{
144 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
145
146 return pctrl->soc->nfunctions;
147}
148
149static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
150 unsigned function)
151{
152 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
153
154 return pctrl->soc->functions[function].name;
155}
156
157static int msm_get_function_groups(struct pinctrl_dev *pctldev,
158 unsigned function,
159 const char * const **groups,
160 unsigned * const num_groups)
161{
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
163
164 *groups = pctrl->soc->functions[function].groups;
165 *num_groups = pctrl->soc->functions[function].ngroups;
166 return 0;
167}
168
169static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
170 unsigned function,
171 unsigned group)
172{
173 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
174 const struct msm_pingroup *g;
175 unsigned long flags;
176 u32 val, mask;
177 int i;
178
179 g = &pctrl->soc->groups[group];
180 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
181
182 for (i = 0; i < g->nfuncs; i++) {
183 if (g->funcs[i] == function)
184 break;
185 }
186
187 if (WARN_ON(i == g->nfuncs))
188 return -EINVAL;
189
190 raw_spin_lock_irqsave(&pctrl->lock, flags);
191
192 val = msm_readl_ctl(pctrl, g);
193 val &= ~mask;
194 val |= i << g->mux_bit;
195 msm_writel_ctl(val, pctrl, g);
196
197 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
198
199 return 0;
200}
201
202static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
203 struct pinctrl_gpio_range *range,
204 unsigned offset)
205{
206 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
207 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
208
209
210 if (!g->nfuncs)
211 return 0;
212
213
214 return msm_pinmux_set_mux(pctldev, g->funcs[0], offset);
215}
216
217static const struct pinmux_ops msm_pinmux_ops = {
218 .request = msm_pinmux_request,
219 .get_functions_count = msm_get_functions_count,
220 .get_function_name = msm_get_function_name,
221 .get_function_groups = msm_get_function_groups,
222 .gpio_request_enable = msm_pinmux_request_gpio,
223 .set_mux = msm_pinmux_set_mux,
224};
225
226static int msm_config_reg(struct msm_pinctrl *pctrl,
227 const struct msm_pingroup *g,
228 unsigned param,
229 unsigned *mask,
230 unsigned *bit)
231{
232 switch (param) {
233 case PIN_CONFIG_BIAS_DISABLE:
234 case PIN_CONFIG_BIAS_PULL_DOWN:
235 case PIN_CONFIG_BIAS_BUS_HOLD:
236 case PIN_CONFIG_BIAS_PULL_UP:
237 *bit = g->pull_bit;
238 *mask = 3;
239 break;
240 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
241 *bit = g->od_bit;
242 *mask = 1;
243 break;
244 case PIN_CONFIG_DRIVE_STRENGTH:
245 *bit = g->drv_bit;
246 *mask = 7;
247 break;
248 case PIN_CONFIG_OUTPUT:
249 case PIN_CONFIG_INPUT_ENABLE:
250 *bit = g->oe_bit;
251 *mask = 1;
252 break;
253 default:
254 return -ENOTSUPP;
255 }
256
257 return 0;
258}
259
260#define MSM_NO_PULL 0
261#define MSM_PULL_DOWN 1
262#define MSM_KEEPER 2
263#define MSM_PULL_UP_NO_KEEPER 2
264#define MSM_PULL_UP 3
265
266static unsigned msm_regval_to_drive(u32 val)
267{
268 return (val + 1) * 2;
269}
270
271static int msm_config_group_get(struct pinctrl_dev *pctldev,
272 unsigned int group,
273 unsigned long *config)
274{
275 const struct msm_pingroup *g;
276 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
277 unsigned param = pinconf_to_config_param(*config);
278 unsigned mask;
279 unsigned arg;
280 unsigned bit;
281 int ret;
282 u32 val;
283
284 g = &pctrl->soc->groups[group];
285
286 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
287 if (ret < 0)
288 return ret;
289
290 val = msm_readl_ctl(pctrl, g);
291 arg = (val >> bit) & mask;
292
293
294 switch (param) {
295 case PIN_CONFIG_BIAS_DISABLE:
296 if (arg != MSM_NO_PULL)
297 return -EINVAL;
298 arg = 1;
299 break;
300 case PIN_CONFIG_BIAS_PULL_DOWN:
301 if (arg != MSM_PULL_DOWN)
302 return -EINVAL;
303 arg = 1;
304 break;
305 case PIN_CONFIG_BIAS_BUS_HOLD:
306 if (pctrl->soc->pull_no_keeper)
307 return -ENOTSUPP;
308
309 if (arg != MSM_KEEPER)
310 return -EINVAL;
311 arg = 1;
312 break;
313 case PIN_CONFIG_BIAS_PULL_UP:
314 if (pctrl->soc->pull_no_keeper)
315 arg = arg == MSM_PULL_UP_NO_KEEPER;
316 else
317 arg = arg == MSM_PULL_UP;
318 if (!arg)
319 return -EINVAL;
320 break;
321 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
322
323 if (!arg)
324 return -EINVAL;
325 arg = 1;
326 break;
327 case PIN_CONFIG_DRIVE_STRENGTH:
328 arg = msm_regval_to_drive(arg);
329 break;
330 case PIN_CONFIG_OUTPUT:
331
332 if (!arg)
333 return -EINVAL;
334
335 val = msm_readl_io(pctrl, g);
336 arg = !!(val & BIT(g->in_bit));
337 break;
338 case PIN_CONFIG_INPUT_ENABLE:
339
340 if (arg)
341 return -EINVAL;
342 arg = 1;
343 break;
344 default:
345 return -ENOTSUPP;
346 }
347
348 *config = pinconf_to_config_packed(param, arg);
349
350 return 0;
351}
352
353static int msm_config_group_set(struct pinctrl_dev *pctldev,
354 unsigned group,
355 unsigned long *configs,
356 unsigned num_configs)
357{
358 const struct msm_pingroup *g;
359 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
360 unsigned long flags;
361 unsigned param;
362 unsigned mask;
363 unsigned arg;
364 unsigned bit;
365 int ret;
366 u32 val;
367 int i;
368
369 g = &pctrl->soc->groups[group];
370
371 for (i = 0; i < num_configs; i++) {
372 param = pinconf_to_config_param(configs[i]);
373 arg = pinconf_to_config_argument(configs[i]);
374
375 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
376 if (ret < 0)
377 return ret;
378
379
380 switch (param) {
381 case PIN_CONFIG_BIAS_DISABLE:
382 arg = MSM_NO_PULL;
383 break;
384 case PIN_CONFIG_BIAS_PULL_DOWN:
385 arg = MSM_PULL_DOWN;
386 break;
387 case PIN_CONFIG_BIAS_BUS_HOLD:
388 if (pctrl->soc->pull_no_keeper)
389 return -ENOTSUPP;
390
391 arg = MSM_KEEPER;
392 break;
393 case PIN_CONFIG_BIAS_PULL_UP:
394 if (pctrl->soc->pull_no_keeper)
395 arg = MSM_PULL_UP_NO_KEEPER;
396 else
397 arg = MSM_PULL_UP;
398 break;
399 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
400 arg = 1;
401 break;
402 case PIN_CONFIG_DRIVE_STRENGTH:
403
404 if (arg > 16 || arg < 2 || (arg % 2) != 0)
405 arg = -1;
406 else
407 arg = (arg / 2) - 1;
408 break;
409 case PIN_CONFIG_OUTPUT:
410
411 raw_spin_lock_irqsave(&pctrl->lock, flags);
412 val = msm_readl_io(pctrl, g);
413 if (arg)
414 val |= BIT(g->out_bit);
415 else
416 val &= ~BIT(g->out_bit);
417 msm_writel_io(val, pctrl, g);
418 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
419
420
421 arg = 1;
422 break;
423 case PIN_CONFIG_INPUT_ENABLE:
424
425 arg = 0;
426 break;
427 default:
428 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
429 param);
430 return -EINVAL;
431 }
432
433
434 if (arg & ~mask) {
435 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
436 return -EINVAL;
437 }
438
439 raw_spin_lock_irqsave(&pctrl->lock, flags);
440 val = msm_readl_ctl(pctrl, g);
441 val &= ~(mask << bit);
442 val |= arg << bit;
443 msm_writel_ctl(val, pctrl, g);
444 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
445 }
446
447 return 0;
448}
449
450static const struct pinconf_ops msm_pinconf_ops = {
451 .is_generic = true,
452 .pin_config_group_get = msm_config_group_get,
453 .pin_config_group_set = msm_config_group_set,
454};
455
456static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
457{
458 const struct msm_pingroup *g;
459 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
460 unsigned long flags;
461 u32 val;
462
463 g = &pctrl->soc->groups[offset];
464
465 raw_spin_lock_irqsave(&pctrl->lock, flags);
466
467 val = msm_readl_ctl(pctrl, g);
468 val &= ~BIT(g->oe_bit);
469 msm_writel_ctl(val, pctrl, g);
470
471 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
472
473 return 0;
474}
475
476static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
477{
478 const struct msm_pingroup *g;
479 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
480 unsigned long flags;
481 u32 val;
482
483 g = &pctrl->soc->groups[offset];
484
485 raw_spin_lock_irqsave(&pctrl->lock, flags);
486
487 val = msm_readl_io(pctrl, g);
488 if (value)
489 val |= BIT(g->out_bit);
490 else
491 val &= ~BIT(g->out_bit);
492 msm_writel_io(val, pctrl, g);
493
494 val = msm_readl_ctl(pctrl, g);
495 val |= BIT(g->oe_bit);
496 msm_writel_ctl(val, pctrl, g);
497
498 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
499
500 return 0;
501}
502
503static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
504{
505 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
506 const struct msm_pingroup *g;
507 u32 val;
508
509 g = &pctrl->soc->groups[offset];
510
511 val = msm_readl_ctl(pctrl, g);
512
513 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
514 GPIO_LINE_DIRECTION_IN;
515}
516
517static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
518{
519 const struct msm_pingroup *g;
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
521 u32 val;
522
523 g = &pctrl->soc->groups[offset];
524
525 val = msm_readl_io(pctrl, g);
526 return !!(val & BIT(g->in_bit));
527}
528
529static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
530{
531 const struct msm_pingroup *g;
532 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
533 unsigned long flags;
534 u32 val;
535
536 g = &pctrl->soc->groups[offset];
537
538 raw_spin_lock_irqsave(&pctrl->lock, flags);
539
540 val = msm_readl_io(pctrl, g);
541 if (value)
542 val |= BIT(g->out_bit);
543 else
544 val &= ~BIT(g->out_bit);
545 msm_writel_io(val, pctrl, g);
546
547 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
548}
549
550#ifdef CONFIG_DEBUG_FS
551#include <linux/seq_file.h>
552
553static void msm_gpio_dbg_show_one(struct seq_file *s,
554 struct pinctrl_dev *pctldev,
555 struct gpio_chip *chip,
556 unsigned offset,
557 unsigned gpio)
558{
559 const struct msm_pingroup *g;
560 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
561 unsigned func;
562 int is_out;
563 int drive;
564 int pull;
565 int val;
566 u32 ctl_reg, io_reg;
567
568 static const char * const pulls_keeper[] = {
569 "no pull",
570 "pull down",
571 "keeper",
572 "pull up"
573 };
574
575 static const char * const pulls_no_keeper[] = {
576 "no pull",
577 "pull down",
578 "pull up",
579 };
580
581 if (!gpiochip_line_is_valid(chip, offset))
582 return;
583
584 g = &pctrl->soc->groups[offset];
585 ctl_reg = msm_readl_ctl(pctrl, g);
586 io_reg = msm_readl_io(pctrl, g);
587
588 is_out = !!(ctl_reg & BIT(g->oe_bit));
589 func = (ctl_reg >> g->mux_bit) & 7;
590 drive = (ctl_reg >> g->drv_bit) & 7;
591 pull = (ctl_reg >> g->pull_bit) & 3;
592
593 if (is_out)
594 val = !!(io_reg & BIT(g->out_bit));
595 else
596 val = !!(io_reg & BIT(g->in_bit));
597
598 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
599 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
600 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
601 if (pctrl->soc->pull_no_keeper)
602 seq_printf(s, " %s", pulls_no_keeper[pull]);
603 else
604 seq_printf(s, " %s", pulls_keeper[pull]);
605 seq_puts(s, "\n");
606}
607
608static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
609{
610 unsigned gpio = chip->base;
611 unsigned i;
612
613 for (i = 0; i < chip->ngpio; i++, gpio++)
614 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
615}
616
617#else
618#define msm_gpio_dbg_show NULL
619#endif
620
621static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
622 unsigned long *valid_mask,
623 unsigned int ngpios)
624{
625 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
626 int ret;
627 unsigned int len, i;
628 const int *reserved = pctrl->soc->reserved_gpios;
629 u16 *tmp;
630
631
632 if (reserved) {
633 bitmap_fill(valid_mask, ngpios);
634 for (i = 0; reserved[i] >= 0; i++) {
635 if (i >= ngpios || reserved[i] >= ngpios) {
636 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
637 return -EINVAL;
638 }
639 clear_bit(reserved[i], valid_mask);
640 }
641
642 return 0;
643 }
644
645
646 len = ret = device_property_count_u16(pctrl->dev, "gpios");
647 if (ret < 0)
648 return 0;
649
650 if (ret > ngpios)
651 return -EINVAL;
652
653 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
654 if (!tmp)
655 return -ENOMEM;
656
657 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
658 if (ret < 0) {
659 dev_err(pctrl->dev, "could not read list of GPIOs\n");
660 goto out;
661 }
662
663 bitmap_zero(valid_mask, ngpios);
664 for (i = 0; i < len; i++)
665 set_bit(tmp[i], valid_mask);
666
667out:
668 kfree(tmp);
669 return ret;
670}
671
672static const struct gpio_chip msm_gpio_template = {
673 .direction_input = msm_gpio_direction_input,
674 .direction_output = msm_gpio_direction_output,
675 .get_direction = msm_gpio_get_direction,
676 .get = msm_gpio_get,
677 .set = msm_gpio_set,
678 .request = gpiochip_generic_request,
679 .free = gpiochip_generic_free,
680 .dbg_show = msm_gpio_dbg_show,
681};
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703static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
704 const struct msm_pingroup *g,
705 struct irq_data *d)
706{
707 int loop_limit = 100;
708 unsigned val, val2, intstat;
709 unsigned pol;
710
711 do {
712 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
713
714 pol = msm_readl_intr_cfg(pctrl, g);
715 pol ^= BIT(g->intr_polarity_bit);
716 msm_writel_intr_cfg(pol, pctrl, g);
717
718 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
719 intstat = msm_readl_intr_status(pctrl, g);
720 if (intstat || (val == val2))
721 return;
722 } while (loop_limit-- > 0);
723 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
724 val, val2);
725}
726
727static void msm_gpio_irq_mask(struct irq_data *d)
728{
729 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
730 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
731 const struct msm_pingroup *g;
732 unsigned long flags;
733 u32 val;
734
735 if (d->parent_data)
736 irq_chip_mask_parent(d);
737
738 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
739 return;
740
741 g = &pctrl->soc->groups[d->hwirq];
742
743 raw_spin_lock_irqsave(&pctrl->lock, flags);
744
745 val = msm_readl_intr_cfg(pctrl, g);
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766 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
767 val &= ~BIT(g->intr_raw_status_bit);
768
769 val &= ~BIT(g->intr_enable_bit);
770 msm_writel_intr_cfg(val, pctrl, g);
771
772 clear_bit(d->hwirq, pctrl->enabled_irqs);
773
774 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
775}
776
777static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
778{
779 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
780 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
781 const struct msm_pingroup *g;
782 unsigned long flags;
783 u32 val;
784
785 if (d->parent_data)
786 irq_chip_unmask_parent(d);
787
788 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
789 return;
790
791 g = &pctrl->soc->groups[d->hwirq];
792
793 raw_spin_lock_irqsave(&pctrl->lock, flags);
794
795 if (status_clear) {
796
797
798
799
800
801 val = msm_readl_intr_status(pctrl, g);
802 val &= ~BIT(g->intr_status_bit);
803 msm_writel_intr_status(val, pctrl, g);
804 }
805
806 val = msm_readl_intr_cfg(pctrl, g);
807 val |= BIT(g->intr_raw_status_bit);
808 val |= BIT(g->intr_enable_bit);
809 msm_writel_intr_cfg(val, pctrl, g);
810
811 set_bit(d->hwirq, pctrl->enabled_irqs);
812
813 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
814}
815
816static void msm_gpio_irq_enable(struct irq_data *d)
817{
818
819
820
821
822
823
824
825
826
827 if (d->parent_data) {
828 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0);
829 irq_chip_enable_parent(d);
830 }
831
832 msm_gpio_irq_clear_unmask(d, true);
833}
834
835static void msm_gpio_irq_disable(struct irq_data *d)
836{
837 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
838 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
839
840 if (d->parent_data)
841 irq_chip_disable_parent(d);
842
843 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
844 msm_gpio_irq_mask(d);
845}
846
847static void msm_gpio_irq_unmask(struct irq_data *d)
848{
849 msm_gpio_irq_clear_unmask(d, false);
850}
851
852
853
854
855
856
857
858
859
860
861static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
862{
863 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
864 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
865 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
866 int loop_limit = 100;
867 unsigned int val;
868 unsigned int type;
869
870
871 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
872 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
873
874 do {
875
876 irq_chip_set_type_parent(d, type);
877
878
879
880
881
882
883
884 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
885 if (type == IRQ_TYPE_EDGE_RISING) {
886 if (!val)
887 return;
888 type = IRQ_TYPE_EDGE_FALLING;
889 } else if (type == IRQ_TYPE_EDGE_FALLING) {
890 if (val)
891 return;
892 type = IRQ_TYPE_EDGE_RISING;
893 }
894 } while (loop_limit-- > 0);
895 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
896}
897
898static void msm_gpio_irq_ack(struct irq_data *d)
899{
900 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
901 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
902 const struct msm_pingroup *g;
903 unsigned long flags;
904 u32 val;
905
906 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
907 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
908 msm_gpio_update_dual_edge_parent(d);
909 return;
910 }
911
912 g = &pctrl->soc->groups[d->hwirq];
913
914 raw_spin_lock_irqsave(&pctrl->lock, flags);
915
916 val = msm_readl_intr_status(pctrl, g);
917 if (g->intr_ack_high)
918 val |= BIT(g->intr_status_bit);
919 else
920 val &= ~BIT(g->intr_status_bit);
921 msm_writel_intr_status(val, pctrl, g);
922
923 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
924 msm_gpio_update_dual_edge_pos(pctrl, g, d);
925
926 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
927}
928
929static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
930 unsigned int type)
931{
932 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
933 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
934
935 return type == IRQ_TYPE_EDGE_BOTH &&
936 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
937 test_bit(d->hwirq, pctrl->skip_wake_irqs);
938}
939
940static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
941{
942 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
943 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
944 const struct msm_pingroup *g;
945 unsigned long flags;
946 u32 val;
947
948 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
949 set_bit(d->hwirq, pctrl->dual_edge_irqs);
950 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
951 msm_gpio_update_dual_edge_parent(d);
952 return 0;
953 }
954
955 if (d->parent_data)
956 irq_chip_set_type_parent(d, type);
957
958 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
959 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
960 irq_set_handler_locked(d, handle_fasteoi_irq);
961 return 0;
962 }
963
964 g = &pctrl->soc->groups[d->hwirq];
965
966 raw_spin_lock_irqsave(&pctrl->lock, flags);
967
968
969
970
971 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
972 set_bit(d->hwirq, pctrl->dual_edge_irqs);
973 else
974 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
975
976
977
978
979
980 if (pctrl->intr_target_use_scm) {
981 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
982 int ret;
983
984 qcom_scm_io_readl(addr, &val);
985
986 val &= ~(7 << g->intr_target_bit);
987 val |= g->intr_target_kpss_val << g->intr_target_bit;
988
989 ret = qcom_scm_io_writel(addr, val);
990 if (ret)
991 dev_err(pctrl->dev,
992 "Failed routing %lu interrupt to Apps proc",
993 d->hwirq);
994 } else {
995 val = msm_readl_intr_target(pctrl, g);
996 val &= ~(7 << g->intr_target_bit);
997 val |= g->intr_target_kpss_val << g->intr_target_bit;
998 msm_writel_intr_target(val, pctrl, g);
999 }
1000
1001
1002
1003
1004
1005
1006 val = msm_readl_intr_cfg(pctrl, g);
1007 val |= BIT(g->intr_raw_status_bit);
1008 if (g->intr_detection_width == 2) {
1009 val &= ~(3 << g->intr_detection_bit);
1010 val &= ~(1 << g->intr_polarity_bit);
1011 switch (type) {
1012 case IRQ_TYPE_EDGE_RISING:
1013 val |= 1 << g->intr_detection_bit;
1014 val |= BIT(g->intr_polarity_bit);
1015 break;
1016 case IRQ_TYPE_EDGE_FALLING:
1017 val |= 2 << g->intr_detection_bit;
1018 val |= BIT(g->intr_polarity_bit);
1019 break;
1020 case IRQ_TYPE_EDGE_BOTH:
1021 val |= 3 << g->intr_detection_bit;
1022 val |= BIT(g->intr_polarity_bit);
1023 break;
1024 case IRQ_TYPE_LEVEL_LOW:
1025 break;
1026 case IRQ_TYPE_LEVEL_HIGH:
1027 val |= BIT(g->intr_polarity_bit);
1028 break;
1029 }
1030 } else if (g->intr_detection_width == 1) {
1031 val &= ~(1 << g->intr_detection_bit);
1032 val &= ~(1 << g->intr_polarity_bit);
1033 switch (type) {
1034 case IRQ_TYPE_EDGE_RISING:
1035 val |= BIT(g->intr_detection_bit);
1036 val |= BIT(g->intr_polarity_bit);
1037 break;
1038 case IRQ_TYPE_EDGE_FALLING:
1039 val |= BIT(g->intr_detection_bit);
1040 break;
1041 case IRQ_TYPE_EDGE_BOTH:
1042 val |= BIT(g->intr_detection_bit);
1043 val |= BIT(g->intr_polarity_bit);
1044 break;
1045 case IRQ_TYPE_LEVEL_LOW:
1046 break;
1047 case IRQ_TYPE_LEVEL_HIGH:
1048 val |= BIT(g->intr_polarity_bit);
1049 break;
1050 }
1051 } else {
1052 BUG();
1053 }
1054 msm_writel_intr_cfg(val, pctrl, g);
1055
1056 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1057 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1058
1059 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1060
1061 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1062 irq_set_handler_locked(d, handle_level_irq);
1063 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1064 irq_set_handler_locked(d, handle_edge_irq);
1065
1066 return 0;
1067}
1068
1069static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1070{
1071 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1072 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1073
1074
1075
1076
1077
1078
1079
1080 if (d->parent_data)
1081 irq_chip_set_wake_parent(d, on);
1082
1083 irq_set_irq_wake(pctrl->irq, on);
1084
1085 return 0;
1086}
1087
1088static int msm_gpio_irq_reqres(struct irq_data *d)
1089{
1090 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1091 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1092 int ret;
1093
1094 if (!try_module_get(gc->owner))
1095 return -ENODEV;
1096
1097 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1098 if (ret)
1099 goto out;
1100 msm_gpio_direction_input(gc, d->hwirq);
1101
1102 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1103 dev_err(gc->parent,
1104 "unable to lock HW IRQ %lu for IRQ\n",
1105 d->hwirq);
1106 ret = -EINVAL;
1107 goto out;
1108 }
1109 return 0;
1110out:
1111 module_put(gc->owner);
1112 return ret;
1113}
1114
1115static void msm_gpio_irq_relres(struct irq_data *d)
1116{
1117 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1118
1119 gpiochip_unlock_as_irq(gc, d->hwirq);
1120 module_put(gc->owner);
1121}
1122
1123static int msm_gpio_irq_set_affinity(struct irq_data *d,
1124 const struct cpumask *dest, bool force)
1125{
1126 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1127 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1128
1129 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1130 return irq_chip_set_affinity_parent(d, dest, force);
1131
1132 return 0;
1133}
1134
1135static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1136{
1137 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1138 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1139
1140 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1141 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1142
1143 return 0;
1144}
1145
1146static void msm_gpio_irq_handler(struct irq_desc *desc)
1147{
1148 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1149 const struct msm_pingroup *g;
1150 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1151 struct irq_chip *chip = irq_desc_get_chip(desc);
1152 int irq_pin;
1153 int handled = 0;
1154 u32 val;
1155 int i;
1156
1157 chained_irq_enter(chip, desc);
1158
1159
1160
1161
1162
1163 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1164 g = &pctrl->soc->groups[i];
1165 val = msm_readl_intr_status(pctrl, g);
1166 if (val & BIT(g->intr_status_bit)) {
1167 irq_pin = irq_find_mapping(gc->irq.domain, i);
1168 generic_handle_irq(irq_pin);
1169 handled++;
1170 }
1171 }
1172
1173
1174 if (handled == 0)
1175 handle_bad_irq(desc);
1176
1177 chained_irq_exit(chip, desc);
1178}
1179
1180static int msm_gpio_wakeirq(struct gpio_chip *gc,
1181 unsigned int child,
1182 unsigned int child_type,
1183 unsigned int *parent,
1184 unsigned int *parent_type)
1185{
1186 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1187 const struct msm_gpio_wakeirq_map *map;
1188 int i;
1189
1190 *parent = GPIO_NO_WAKE_IRQ;
1191 *parent_type = IRQ_TYPE_EDGE_RISING;
1192
1193 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1194 map = &pctrl->soc->wakeirq_map[i];
1195 if (map->gpio == child) {
1196 *parent = map->wakeirq;
1197 break;
1198 }
1199 }
1200
1201 return 0;
1202}
1203
1204static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1205{
1206 if (pctrl->soc->reserved_gpios)
1207 return true;
1208
1209 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1210}
1211
1212static int msm_gpio_init(struct msm_pinctrl *pctrl)
1213{
1214 struct gpio_chip *chip;
1215 struct gpio_irq_chip *girq;
1216 int i, ret;
1217 unsigned gpio, ngpio = pctrl->soc->ngpios;
1218 struct device_node *np;
1219 bool skip;
1220
1221 if (WARN_ON(ngpio > MAX_NR_GPIO))
1222 return -EINVAL;
1223
1224 chip = &pctrl->chip;
1225 chip->base = -1;
1226 chip->ngpio = ngpio;
1227 chip->label = dev_name(pctrl->dev);
1228 chip->parent = pctrl->dev;
1229 chip->owner = THIS_MODULE;
1230 chip->of_node = pctrl->dev->of_node;
1231 if (msm_gpio_needs_valid_mask(pctrl))
1232 chip->init_valid_mask = msm_gpio_init_valid_mask;
1233
1234 pctrl->irq_chip.name = "msmgpio";
1235 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1236 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1237 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1238 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1239 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1240 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1241 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1242 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1243 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1244 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1245 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1246
1247 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1248 if (np) {
1249 chip->irq.parent_domain = irq_find_matching_host(np,
1250 DOMAIN_BUS_WAKEUP);
1251 of_node_put(np);
1252 if (!chip->irq.parent_domain)
1253 return -EPROBE_DEFER;
1254 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1255 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1256
1257
1258
1259
1260 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1261 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1262 gpio = pctrl->soc->wakeirq_map[i].gpio;
1263 set_bit(gpio, pctrl->skip_wake_irqs);
1264 }
1265 }
1266
1267 girq = &chip->irq;
1268 girq->chip = &pctrl->irq_chip;
1269 girq->parent_handler = msm_gpio_irq_handler;
1270 girq->fwnode = pctrl->dev->fwnode;
1271 girq->num_parents = 1;
1272 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1273 GFP_KERNEL);
1274 if (!girq->parents)
1275 return -ENOMEM;
1276 girq->default_type = IRQ_TYPE_NONE;
1277 girq->handler = handle_bad_irq;
1278 girq->parents[0] = pctrl->irq;
1279
1280 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1281 if (ret) {
1282 dev_err(pctrl->dev, "Failed register gpiochip\n");
1283 return ret;
1284 }
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1297 ret = gpiochip_add_pin_range(&pctrl->chip,
1298 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1299 if (ret) {
1300 dev_err(pctrl->dev, "Failed to add pin range\n");
1301 gpiochip_remove(&pctrl->chip);
1302 return ret;
1303 }
1304 }
1305
1306 return 0;
1307}
1308
1309static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1310 void *data)
1311{
1312 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1313
1314 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1315 mdelay(1000);
1316 return NOTIFY_DONE;
1317}
1318
1319static struct msm_pinctrl *poweroff_pctrl;
1320
1321static void msm_ps_hold_poweroff(void)
1322{
1323 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1324}
1325
1326static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1327{
1328 int i;
1329 const struct msm_function *func = pctrl->soc->functions;
1330
1331 for (i = 0; i < pctrl->soc->nfunctions; i++)
1332 if (!strcmp(func[i].name, "ps_hold")) {
1333 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1334 pctrl->restart_nb.priority = 128;
1335 if (register_restart_handler(&pctrl->restart_nb))
1336 dev_err(pctrl->dev,
1337 "failed to setup restart handler.\n");
1338 poweroff_pctrl = pctrl;
1339 pm_power_off = msm_ps_hold_poweroff;
1340 break;
1341 }
1342}
1343
1344static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1345{
1346 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1347
1348 return pinctrl_force_sleep(pctrl->pctrl);
1349}
1350
1351static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1352{
1353 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1354
1355 return pinctrl_force_default(pctrl->pctrl);
1356}
1357
1358SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1359 msm_pinctrl_resume);
1360
1361EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1362
1363int msm_pinctrl_probe(struct platform_device *pdev,
1364 const struct msm_pinctrl_soc_data *soc_data)
1365{
1366 struct msm_pinctrl *pctrl;
1367 struct resource *res;
1368 int ret;
1369 int i;
1370
1371 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1372 if (!pctrl)
1373 return -ENOMEM;
1374
1375 pctrl->dev = &pdev->dev;
1376 pctrl->soc = soc_data;
1377 pctrl->chip = msm_gpio_template;
1378 pctrl->intr_target_use_scm = of_device_is_compatible(
1379 pctrl->dev->of_node,
1380 "qcom,ipq8064-pinctrl");
1381
1382 raw_spin_lock_init(&pctrl->lock);
1383
1384 if (soc_data->tiles) {
1385 for (i = 0; i < soc_data->ntiles; i++) {
1386 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1387 soc_data->tiles[i]);
1388 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1389 if (IS_ERR(pctrl->regs[i]))
1390 return PTR_ERR(pctrl->regs[i]);
1391 }
1392 } else {
1393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1394 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1395 if (IS_ERR(pctrl->regs[0]))
1396 return PTR_ERR(pctrl->regs[0]);
1397
1398 pctrl->phys_base[0] = res->start;
1399 }
1400
1401 msm_pinctrl_setup_pm_reset(pctrl);
1402
1403 pctrl->irq = platform_get_irq(pdev, 0);
1404 if (pctrl->irq < 0)
1405 return pctrl->irq;
1406
1407 pctrl->desc.owner = THIS_MODULE;
1408 pctrl->desc.pctlops = &msm_pinctrl_ops;
1409 pctrl->desc.pmxops = &msm_pinmux_ops;
1410 pctrl->desc.confops = &msm_pinconf_ops;
1411 pctrl->desc.name = dev_name(&pdev->dev);
1412 pctrl->desc.pins = pctrl->soc->pins;
1413 pctrl->desc.npins = pctrl->soc->npins;
1414
1415 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1416 if (IS_ERR(pctrl->pctrl)) {
1417 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1418 return PTR_ERR(pctrl->pctrl);
1419 }
1420
1421 ret = msm_gpio_init(pctrl);
1422 if (ret)
1423 return ret;
1424
1425 platform_set_drvdata(pdev, pctrl);
1426
1427 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1428
1429 return 0;
1430}
1431EXPORT_SYMBOL(msm_pinctrl_probe);
1432
1433int msm_pinctrl_remove(struct platform_device *pdev)
1434{
1435 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1436
1437 gpiochip_remove(&pctrl->chip);
1438
1439 unregister_restart_handler(&pctrl->restart_nb);
1440
1441 return 0;
1442}
1443EXPORT_SYMBOL(msm_pinctrl_remove);
1444
1445