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8#include <linux/firmware.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/delay.h>
13#include <linux/jiffies.h>
14#include <linux/kernel.h>
15#include <linux/timekeeping.h>
16#include <linux/string.h>
17
18#include "ptp_private.h"
19#include "ptp_clockmatrix.h"
20
21MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
22MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
23MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
24MODULE_VERSION("1.0");
25MODULE_LICENSE("GPL");
26
27
28
29
30
31static char *firmware;
32module_param(firmware, charp, 0);
33
34#define SETTIME_CORRECTION (0)
35
36static long set_write_phase_ready(struct ptp_clock_info *ptp)
37{
38 struct idtcm_channel *channel =
39 container_of(ptp, struct idtcm_channel, caps);
40
41 channel->write_phase_ready = 1;
42
43 return 0;
44}
45
46static int char_array_to_timespec(u8 *buf,
47 u8 count,
48 struct timespec64 *ts)
49{
50 u8 i;
51 u64 nsec;
52 time64_t sec;
53
54 if (count < TOD_BYTE_COUNT)
55 return 1;
56
57
58 nsec = buf[4];
59 for (i = 0; i < 3; i++) {
60 nsec <<= 8;
61 nsec |= buf[3 - i];
62 }
63
64 sec = buf[10];
65 for (i = 0; i < 5; i++) {
66 sec <<= 8;
67 sec |= buf[9 - i];
68 }
69
70 ts->tv_sec = sec;
71 ts->tv_nsec = nsec;
72
73 return 0;
74}
75
76static int timespec_to_char_array(struct timespec64 const *ts,
77 u8 *buf,
78 u8 count)
79{
80 u8 i;
81 s32 nsec;
82 time64_t sec;
83
84 if (count < TOD_BYTE_COUNT)
85 return 1;
86
87 nsec = ts->tv_nsec;
88 sec = ts->tv_sec;
89
90
91 buf[0] = 0;
92 for (i = 1; i < 5; i++) {
93 buf[i] = nsec & 0xff;
94 nsec >>= 8;
95 }
96
97 for (i = 5; i < TOD_BYTE_COUNT; i++) {
98
99 buf[i] = sec & 0xff;
100 sec >>= 8;
101 }
102
103 return 0;
104}
105
106static int idtcm_strverscmp(const char *ver1, const char *ver2)
107{
108 u8 num1;
109 u8 num2;
110 int result = 0;
111
112
113 while (result == 0) {
114
115 if (kstrtou8(ver1, 10, &num1) < 0)
116 return -1;
117
118 if (kstrtou8(ver2, 10, &num2) < 0)
119 return -1;
120
121
122 if (num1 < num2)
123 result = -1;
124 else if (num1 > num2)
125 result = 1;
126 else {
127
128 ver1 = strchr(ver1, '.');
129 ver2 = strchr(ver2, '.');
130 if (!ver1 && !ver2)
131 break;
132 else if (!ver1)
133 result = -1;
134 else if (!ver2)
135 result = 1;
136 else {
137 ver1++;
138 ver2++;
139 }
140 }
141 }
142 return result;
143}
144
145static int idtcm_xfer_read(struct idtcm *idtcm,
146 u8 regaddr,
147 u8 *buf,
148 u16 count)
149{
150 struct i2c_client *client = idtcm->client;
151 struct i2c_msg msg[2];
152 int cnt;
153 char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
154
155 msg[0].addr = client->addr;
156 msg[0].flags = 0;
157 msg[0].len = 1;
158 msg[0].buf = ®addr;
159
160 msg[1].addr = client->addr;
161 msg[1].flags = I2C_M_RD;
162 msg[1].len = count;
163 msg[1].buf = buf;
164
165 cnt = i2c_transfer(client->adapter, msg, 2);
166
167 if (cnt < 0) {
168 dev_err(&client->dev,
169 fmt,
170 __LINE__,
171 __func__,
172 regaddr);
173 return cnt;
174 } else if (cnt != 2) {
175 dev_err(&client->dev,
176 "i2c_transfer sent only %d of %d messages\n", cnt, 2);
177 return -EIO;
178 }
179
180 return 0;
181}
182
183static int idtcm_xfer_write(struct idtcm *idtcm,
184 u8 regaddr,
185 u8 *buf,
186 u16 count)
187{
188 struct i2c_client *client = idtcm->client;
189
190 u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
191 int cnt;
192 char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
193
194 if (count > IDTCM_MAX_WRITE_COUNT)
195 return -EINVAL;
196
197 msg[0] = regaddr;
198 memcpy(&msg[1], buf, count);
199
200 cnt = i2c_master_send(client, msg, count + 1);
201
202 if (cnt < 0) {
203 dev_err(&client->dev,
204 fmt,
205 __LINE__,
206 __func__,
207 regaddr);
208 return cnt;
209 }
210
211 return 0;
212}
213
214static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
215{
216 u8 buf[4];
217 int err;
218
219 if (idtcm->page_offset == val)
220 return 0;
221
222 buf[0] = 0x0;
223 buf[1] = val;
224 buf[2] = 0x10;
225 buf[3] = 0x20;
226
227 err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
228
229 if (err) {
230 idtcm->page_offset = 0xff;
231 dev_err(&idtcm->client->dev, "failed to set page offset\n");
232 } else {
233 idtcm->page_offset = val;
234 }
235
236 return err;
237}
238
239static int _idtcm_rdwr(struct idtcm *idtcm,
240 u16 regaddr,
241 u8 *buf,
242 u16 count,
243 bool write)
244{
245 u8 hi;
246 u8 lo;
247 int err;
248
249 hi = (regaddr >> 8) & 0xff;
250 lo = regaddr & 0xff;
251
252 err = idtcm_page_offset(idtcm, hi);
253
254 if (err)
255 return err;
256
257 if (write)
258 return idtcm_xfer_write(idtcm, lo, buf, count);
259
260 return idtcm_xfer_read(idtcm, lo, buf, count);
261}
262
263static int idtcm_read(struct idtcm *idtcm,
264 u16 module,
265 u16 regaddr,
266 u8 *buf,
267 u16 count)
268{
269 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
270}
271
272static int idtcm_write(struct idtcm *idtcm,
273 u16 module,
274 u16 regaddr,
275 u8 *buf,
276 u16 count)
277{
278 return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
279}
280
281static int _idtcm_gettime(struct idtcm_channel *channel,
282 struct timespec64 *ts)
283{
284 struct idtcm *idtcm = channel->idtcm;
285 u8 buf[TOD_BYTE_COUNT];
286 u8 timeout = 10;
287 u8 trigger;
288 int err;
289
290 err = idtcm_read(idtcm, channel->tod_read_primary,
291 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
292 if (err)
293 return err;
294
295 trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
296 trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
297 trigger &= ~TOD_READ_TRIGGER_MODE;
298
299 err = idtcm_write(idtcm, channel->tod_read_primary,
300 TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
301 if (err)
302 return err;
303
304
305 while (trigger & TOD_READ_TRIGGER_MASK) {
306
307 if (idtcm->calculate_overhead_flag)
308 idtcm->start_time = ktime_get_raw();
309
310 err = idtcm_read(idtcm, channel->tod_read_primary,
311 TOD_READ_PRIMARY_CMD, &trigger,
312 sizeof(trigger));
313
314 if (err)
315 return err;
316
317 if (--timeout == 0)
318 return -EIO;
319 }
320
321 err = idtcm_read(idtcm, channel->tod_read_primary,
322 TOD_READ_PRIMARY, buf, sizeof(buf));
323
324 if (err)
325 return err;
326
327 err = char_array_to_timespec(buf, sizeof(buf), ts);
328
329 return err;
330}
331
332static int _sync_pll_output(struct idtcm *idtcm,
333 u8 pll,
334 u8 sync_src,
335 u8 qn,
336 u8 qn_plus_1)
337{
338 int err;
339 u8 val;
340 u16 sync_ctrl0;
341 u16 sync_ctrl1;
342 u8 temp;
343
344 if ((qn == 0) && (qn_plus_1 == 0))
345 return 0;
346
347 switch (pll) {
348 case 0:
349 sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
350 sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
351 break;
352 case 1:
353 sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
354 sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
355 break;
356 case 2:
357 sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
358 sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
359 break;
360 case 3:
361 sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
362 sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
363 break;
364 case 4:
365 sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
366 sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
367 break;
368 case 5:
369 sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
370 sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
371 break;
372 case 6:
373 sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
374 sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
375 break;
376 case 7:
377 sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
378 sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
379 break;
380 default:
381 return -EINVAL;
382 }
383
384 val = SYNCTRL1_MASTER_SYNC_RST;
385
386
387 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
388 if (err)
389 return err;
390
391 err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
392 if (err)
393 return err;
394
395
396 val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
397
398 if (qn)
399 val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
400
401 if (qn_plus_1)
402 val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
403
404 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
405 if (err)
406 return err;
407
408
409 if ((pll == 5) && (qn_plus_1 != 0)) {
410 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
411 &temp, sizeof(temp));
412 if (err)
413 return err;
414
415 temp &= ~(Q9_TO_Q8_SYNC_TRIG);
416
417 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
418 &temp, sizeof(temp));
419 if (err)
420 return err;
421
422 temp |= Q9_TO_Q8_SYNC_TRIG;
423
424 err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
425 &temp, sizeof(temp));
426 if (err)
427 return err;
428 }
429
430
431 if ((pll == 6) && (qn_plus_1 != 0)) {
432 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
433 &temp, sizeof(temp));
434 if (err)
435 return err;
436
437 temp &= ~(Q10_TO_Q11_SYNC_TRIG);
438
439 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
440 &temp, sizeof(temp));
441 if (err)
442 return err;
443
444 temp |= Q10_TO_Q11_SYNC_TRIG;
445
446 err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
447 &temp, sizeof(temp));
448 if (err)
449 return err;
450 }
451
452
453 val &= ~(SYNCTRL1_MASTER_SYNC_RST);
454 err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
455
456 return err;
457}
458
459static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
460{
461 int err = 0;
462
463 switch (tod_addr) {
464 case TOD_0:
465 *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
466 break;
467 case TOD_1:
468 *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
469 break;
470 case TOD_2:
471 *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
472 break;
473 case TOD_3:
474 *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
475 break;
476 default:
477 err = -EINVAL;
478 }
479
480 return err;
481}
482
483static int idtcm_sync_pps_output(struct idtcm_channel *channel)
484{
485 struct idtcm *idtcm = channel->idtcm;
486
487 u8 pll;
488 u8 sync_src;
489 u8 qn;
490 u8 qn_plus_1;
491 int err = 0;
492 u8 out8_mux = 0;
493 u8 out11_mux = 0;
494 u8 temp;
495
496 u16 output_mask = channel->output_mask;
497
498 err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
499 if (err)
500 return err;
501
502 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
503 &temp, sizeof(temp));
504 if (err)
505 return err;
506
507 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
508 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
509 out8_mux = 1;
510
511 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
512 &temp, sizeof(temp));
513 if (err)
514 return err;
515
516 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
517 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
518 out11_mux = 1;
519
520 for (pll = 0; pll < 8; pll++) {
521 qn = 0;
522 qn_plus_1 = 0;
523
524 if (pll < 4) {
525
526 qn = output_mask & 0x1;
527 output_mask = output_mask >> 1;
528 qn_plus_1 = output_mask & 0x1;
529 output_mask = output_mask >> 1;
530 } else if (pll == 4) {
531 if (out8_mux == 0) {
532 qn = output_mask & 0x1;
533 output_mask = output_mask >> 1;
534 }
535 } else if (pll == 5) {
536 if (out8_mux) {
537 qn_plus_1 = output_mask & 0x1;
538 output_mask = output_mask >> 1;
539 }
540 qn = output_mask & 0x1;
541 output_mask = output_mask >> 1;
542 } else if (pll == 6) {
543 qn = output_mask & 0x1;
544 output_mask = output_mask >> 1;
545 if (out11_mux) {
546 qn_plus_1 = output_mask & 0x1;
547 output_mask = output_mask >> 1;
548 }
549 } else if (pll == 7) {
550 if (out11_mux == 0) {
551 qn = output_mask & 0x1;
552 output_mask = output_mask >> 1;
553 }
554 }
555
556 if ((qn != 0) || (qn_plus_1 != 0))
557 err = _sync_pll_output(idtcm, pll, sync_src, qn,
558 qn_plus_1);
559
560 if (err)
561 return err;
562 }
563
564 return err;
565}
566
567static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
568 struct timespec64 const *ts,
569 enum hw_tod_write_trig_sel wr_trig)
570{
571 struct idtcm *idtcm = channel->idtcm;
572
573 u8 buf[TOD_BYTE_COUNT];
574 u8 cmd;
575 int err;
576 struct timespec64 local_ts = *ts;
577 s64 total_overhead_ns;
578
579
580 err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
581 &cmd, sizeof(cmd));
582
583 if (err)
584 return err;
585
586 cmd &= ~(0x0f);
587 cmd |= wr_trig | 0x08;
588
589 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
590 &cmd, sizeof(cmd));
591
592 if (err)
593 return err;
594
595 if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
596
597 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
598
599 if (err)
600 return err;
601
602 err = idtcm_write(idtcm, channel->hw_dpll_n,
603 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
604
605 if (err)
606 return err;
607 }
608
609
610 cmd &= ~(0x08);
611
612 err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
613 &cmd, sizeof(cmd));
614
615 if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
616
617 if (idtcm->calculate_overhead_flag) {
618
619 total_overhead_ns = ktime_to_ns(ktime_get_raw()
620 - idtcm->start_time)
621 + idtcm->tod_write_overhead_ns
622 + SETTIME_CORRECTION;
623
624 timespec64_add_ns(&local_ts, total_overhead_ns);
625
626 idtcm->calculate_overhead_flag = 0;
627 }
628
629 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
630
631 if (err)
632 return err;
633
634 err = idtcm_write(idtcm, channel->hw_dpll_n,
635 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
636 }
637
638 return err;
639}
640
641static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
642 struct timespec64 const *ts,
643 enum scsr_tod_write_trig_sel wr_trig,
644 enum scsr_tod_write_type_sel wr_type)
645{
646 struct idtcm *idtcm = channel->idtcm;
647 unsigned char buf[TOD_BYTE_COUNT], cmd;
648 struct timespec64 local_ts = *ts;
649 int err, count = 0;
650
651 timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
652
653 err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
654
655 if (err)
656 return err;
657
658 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
659 buf, sizeof(buf));
660 if (err)
661 return err;
662
663
664 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
665 &cmd, sizeof(cmd));
666 if (err)
667 return err;
668
669 cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
670 cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
671 cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
672 cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
673
674 err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
675 &cmd, sizeof(cmd));
676 if (err)
677 return err;
678
679
680 while (1) {
681
682 if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
683 msleep(50);
684
685 err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
686 &cmd, sizeof(cmd));
687 if (err)
688 return err;
689
690 if (cmd == 0)
691 break;
692
693 if (++count > 20) {
694 dev_err(&idtcm->client->dev,
695 "Timed out waiting for the write counter\n");
696 return -EIO;
697 }
698 }
699
700 return 0;
701}
702
703static int _idtcm_settime(struct idtcm_channel *channel,
704 struct timespec64 const *ts,
705 enum hw_tod_write_trig_sel wr_trig)
706{
707 struct idtcm *idtcm = channel->idtcm;
708 int err;
709 int i;
710 u8 trig_sel;
711
712 err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
713
714 if (err)
715 return err;
716
717
718 for (i = 0; i < 10000; i++) {
719 err = idtcm_read(idtcm, channel->hw_dpll_n,
720 HW_DPLL_TOD_CTRL_1, &trig_sel,
721 sizeof(trig_sel));
722
723 if (err)
724 return err;
725
726 if (trig_sel == 0x4a)
727 break;
728
729 err = 1;
730 }
731
732 if (err) {
733 dev_err(&idtcm->client->dev,
734 "Failed at line %d in func %s!\n",
735 __LINE__,
736 __func__);
737 return err;
738 }
739
740 return idtcm_sync_pps_output(channel);
741}
742
743static int _idtcm_settime_v487(struct idtcm_channel *channel,
744 struct timespec64 const *ts,
745 enum scsr_tod_write_type_sel wr_type)
746{
747 return _idtcm_set_dpll_scsr_tod(channel, ts,
748 SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
749 wr_type);
750}
751
752static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
753 s32 offset_ns)
754{
755 int err;
756 int i;
757 struct idtcm *idtcm = channel->idtcm;
758
759 u8 buf[4];
760
761 for (i = 0; i < 4; i++) {
762 buf[i] = 0xff & (offset_ns);
763 offset_ns >>= 8;
764 }
765
766 err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
767 buf, sizeof(buf));
768
769 return err;
770}
771
772static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
773 u32 max_ffo_ppb)
774{
775 int err;
776 u8 i;
777 struct idtcm *idtcm = channel->idtcm;
778
779 u8 buf[3];
780
781 if (max_ffo_ppb & 0xff000000)
782 max_ffo_ppb = 0;
783
784 for (i = 0; i < 3; i++) {
785 buf[i] = 0xff & (max_ffo_ppb);
786 max_ffo_ppb >>= 8;
787 }
788
789 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
790 PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
791
792 return err;
793}
794
795static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
796{
797 int err;
798 struct idtcm *idtcm = channel->idtcm;
799
800 u8 buf;
801
802 err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
803 &buf, sizeof(buf));
804
805 if (err)
806 return err;
807
808 if (buf == 0) {
809 buf = 0x01;
810 err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
811 PULL_IN_CTRL, &buf, sizeof(buf));
812 } else {
813 err = -EBUSY;
814 }
815
816 return err;
817}
818
819static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
820 s32 offset_ns,
821 u32 max_ffo_ppb)
822{
823 int err;
824
825 err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
826
827 if (err)
828 return err;
829
830 err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
831
832 if (err)
833 return err;
834
835 err = idtcm_start_phase_pull_in(channel);
836
837 return err;
838}
839
840static int set_tod_write_overhead(struct idtcm_channel *channel)
841{
842 struct idtcm *idtcm = channel->idtcm;
843 s64 current_ns = 0;
844 s64 lowest_ns = 0;
845 int err;
846 u8 i;
847
848 ktime_t start;
849 ktime_t stop;
850
851 char buf[TOD_BYTE_COUNT] = {0};
852
853
854 idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
855 buf, sizeof(buf));
856
857 for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
858
859 start = ktime_get_raw();
860
861 err = idtcm_write(idtcm, channel->hw_dpll_n,
862 HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
863
864 if (err)
865 return err;
866
867 stop = ktime_get_raw();
868
869 current_ns = ktime_to_ns(stop - start);
870
871 if (i == 0) {
872 lowest_ns = current_ns;
873 } else {
874 if (current_ns < lowest_ns)
875 lowest_ns = current_ns;
876 }
877 }
878
879 idtcm->tod_write_overhead_ns = lowest_ns;
880
881 return err;
882}
883
884static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
885{
886 int err;
887 struct idtcm *idtcm = channel->idtcm;
888 struct timespec64 ts;
889 s64 now;
890
891 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
892 err = idtcm_do_phase_pull_in(channel, delta, 0);
893 } else {
894 idtcm->calculate_overhead_flag = 1;
895
896 err = set_tod_write_overhead(channel);
897
898 if (err)
899 return err;
900
901 err = _idtcm_gettime(channel, &ts);
902
903 if (err)
904 return err;
905
906 now = timespec64_to_ns(&ts);
907 now += delta;
908
909 ts = ns_to_timespec64(now);
910
911 err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
912 }
913
914 return err;
915}
916
917static int idtcm_state_machine_reset(struct idtcm *idtcm)
918{
919 int err;
920 u8 byte = SM_RESET_CMD;
921
922 err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
923
924 if (!err)
925 msleep_interruptible(POST_SM_RESET_DELAY_MS);
926
927 return err;
928}
929
930static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
931{
932 return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
933}
934
935static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
936{
937 int err;
938 u8 buf[2] = {0};
939
940 err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
941
942 *product_id = (buf[1] << 8) | buf[0];
943
944 return err;
945}
946
947static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
948{
949 int err;
950 u8 buf = 0;
951
952 err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
953
954 *major = buf >> 1;
955
956 return err;
957}
958
959static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
960{
961 return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
962}
963
964static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
965{
966 return idtcm_read(idtcm,
967 GENERAL_STATUS,
968 HOTFIX_REL,
969 hotfix,
970 sizeof(u8));
971}
972
973static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
974 u8 *config_select)
975{
976 return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
977 config_select, sizeof(u8));
978}
979
980static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
981{
982 int err = 0;
983
984 switch (addr) {
985 case TOD0_OUT_ALIGN_MASK_ADDR:
986 SET_U16_LSB(idtcm->channel[0].output_mask, val);
987 break;
988 case TOD0_OUT_ALIGN_MASK_ADDR + 1:
989 SET_U16_MSB(idtcm->channel[0].output_mask, val);
990 break;
991 case TOD1_OUT_ALIGN_MASK_ADDR:
992 SET_U16_LSB(idtcm->channel[1].output_mask, val);
993 break;
994 case TOD1_OUT_ALIGN_MASK_ADDR + 1:
995 SET_U16_MSB(idtcm->channel[1].output_mask, val);
996 break;
997 case TOD2_OUT_ALIGN_MASK_ADDR:
998 SET_U16_LSB(idtcm->channel[2].output_mask, val);
999 break;
1000 case TOD2_OUT_ALIGN_MASK_ADDR + 1:
1001 SET_U16_MSB(idtcm->channel[2].output_mask, val);
1002 break;
1003 case TOD3_OUT_ALIGN_MASK_ADDR:
1004 SET_U16_LSB(idtcm->channel[3].output_mask, val);
1005 break;
1006 case TOD3_OUT_ALIGN_MASK_ADDR + 1:
1007 SET_U16_MSB(idtcm->channel[3].output_mask, val);
1008 break;
1009 default:
1010 err = -EFAULT; ;
1011 break;
1012 }
1013
1014 return err;
1015}
1016
1017static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
1018{
1019 if (index >= MAX_TOD) {
1020 dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
1021 return -EINVAL;
1022 }
1023
1024 if (pll >= MAX_PLL) {
1025 dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
1026 return -EINVAL;
1027 }
1028
1029 idtcm->channel[index].pll = pll;
1030
1031 return 0;
1032}
1033
1034static int check_and_set_masks(struct idtcm *idtcm,
1035 u16 regaddr,
1036 u8 val)
1037{
1038 int err = 0;
1039
1040 switch (regaddr) {
1041 case TOD_MASK_ADDR:
1042 if ((val & 0xf0) || !(val & 0x0f)) {
1043 dev_err(&idtcm->client->dev,
1044 "Invalid TOD mask 0x%hhx\n", val);
1045 err = -EINVAL;
1046 } else {
1047 idtcm->tod_mask = val;
1048 }
1049 break;
1050 case TOD0_PTP_PLL_ADDR:
1051 err = set_tod_ptp_pll(idtcm, 0, val);
1052 break;
1053 case TOD1_PTP_PLL_ADDR:
1054 err = set_tod_ptp_pll(idtcm, 1, val);
1055 break;
1056 case TOD2_PTP_PLL_ADDR:
1057 err = set_tod_ptp_pll(idtcm, 2, val);
1058 break;
1059 case TOD3_PTP_PLL_ADDR:
1060 err = set_tod_ptp_pll(idtcm, 3, val);
1061 break;
1062 default:
1063 err = set_pll_output_mask(idtcm, regaddr, val);
1064 break;
1065 }
1066
1067 return err;
1068}
1069
1070static void display_pll_and_masks(struct idtcm *idtcm)
1071{
1072 u8 i;
1073 u8 mask;
1074
1075 dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
1076
1077 for (i = 0; i < MAX_TOD; i++) {
1078 mask = 1 << i;
1079
1080 if (mask & idtcm->tod_mask)
1081 dev_dbg(&idtcm->client->dev,
1082 "TOD%d pll = %d output_mask = 0x%04x\n",
1083 i, idtcm->channel[i].pll,
1084 idtcm->channel[i].output_mask);
1085 }
1086}
1087
1088static int idtcm_load_firmware(struct idtcm *idtcm,
1089 struct device *dev)
1090{
1091 char fname[128] = FW_FILENAME;
1092 const struct firmware *fw;
1093 struct idtcm_fwrc *rec;
1094 u32 regaddr;
1095 int err;
1096 s32 len;
1097 u8 val;
1098 u8 loaddr;
1099
1100 if (firmware)
1101 snprintf(fname, sizeof(fname), "%s", firmware);
1102
1103 dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
1104
1105 err = request_firmware(&fw, fname, dev);
1106
1107 if (err) {
1108 dev_err(&idtcm->client->dev,
1109 "Failed at line %d in func %s!\n",
1110 __LINE__,
1111 __func__);
1112 return err;
1113 }
1114
1115 dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
1116
1117 rec = (struct idtcm_fwrc *) fw->data;
1118
1119 if (fw->size > 0)
1120 idtcm_state_machine_reset(idtcm);
1121
1122 for (len = fw->size; len > 0; len -= sizeof(*rec)) {
1123
1124 if (rec->reserved) {
1125 dev_err(&idtcm->client->dev,
1126 "bad firmware, reserved field non-zero\n");
1127 err = -EINVAL;
1128 } else {
1129 regaddr = rec->hiaddr << 8;
1130 regaddr |= rec->loaddr;
1131
1132 val = rec->value;
1133 loaddr = rec->loaddr;
1134
1135 rec++;
1136
1137 err = check_and_set_masks(idtcm, regaddr, val);
1138 }
1139
1140 if (err != -EINVAL) {
1141 err = 0;
1142
1143
1144 if ((regaddr < GPIO_USER_CONTROL)
1145 || (regaddr >= SCRATCH))
1146 continue;
1147
1148
1149 if (((loaddr > 0x7b) && (loaddr <= 0x7f))
1150 || loaddr > 0xfb)
1151 continue;
1152
1153 err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
1154 }
1155
1156 if (err)
1157 goto out;
1158 }
1159
1160 display_pll_and_masks(idtcm);
1161
1162out:
1163 release_firmware(fw);
1164 return err;
1165}
1166
1167static int idtcm_output_enable(struct idtcm_channel *channel,
1168 bool enable, unsigned int outn)
1169{
1170 struct idtcm *idtcm = channel->idtcm;
1171 int err;
1172 u8 val;
1173
1174 err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1175 OUT_CTRL_1, &val, sizeof(val));
1176
1177 if (err)
1178 return err;
1179
1180 if (enable)
1181 val |= SQUELCH_DISABLE;
1182 else
1183 val &= ~SQUELCH_DISABLE;
1184
1185 return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
1186 OUT_CTRL_1, &val, sizeof(val));
1187}
1188
1189static int idtcm_output_mask_enable(struct idtcm_channel *channel,
1190 bool enable)
1191{
1192 u16 mask;
1193 int err;
1194 u8 outn;
1195
1196 mask = channel->output_mask;
1197 outn = 0;
1198
1199 while (mask) {
1200
1201 if (mask & 0x1) {
1202
1203 err = idtcm_output_enable(channel, enable, outn);
1204
1205 if (err)
1206 return err;
1207 }
1208
1209 mask >>= 0x1;
1210 outn++;
1211 }
1212
1213 return 0;
1214}
1215
1216static int idtcm_perout_enable(struct idtcm_channel *channel,
1217 bool enable,
1218 struct ptp_perout_request *perout)
1219{
1220 unsigned int flags = perout->flags;
1221
1222 if (flags == PEROUT_ENABLE_OUTPUT_MASK)
1223 return idtcm_output_mask_enable(channel, enable);
1224
1225
1226 return idtcm_output_enable(channel, enable, perout->index);
1227}
1228
1229static int idtcm_set_pll_mode(struct idtcm_channel *channel,
1230 enum pll_mode pll_mode)
1231{
1232 struct idtcm *idtcm = channel->idtcm;
1233 int err;
1234 u8 dpll_mode;
1235
1236 err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
1237 &dpll_mode, sizeof(dpll_mode));
1238 if (err)
1239 return err;
1240
1241 dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
1242
1243 dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
1244
1245 channel->pll_mode = pll_mode;
1246
1247 err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
1248 &dpll_mode, sizeof(dpll_mode));
1249 if (err)
1250 return err;
1251
1252 return 0;
1253}
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
1265{
1266 struct idtcm *idtcm = channel->idtcm;
1267
1268 int err;
1269 u8 i;
1270 u8 buf[4] = {0};
1271 s32 phase_50ps;
1272 s64 offset_ps;
1273
1274 if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
1275
1276 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
1277
1278 if (err)
1279 return err;
1280
1281 channel->write_phase_ready = 0;
1282
1283 ptp_schedule_worker(channel->ptp_clock,
1284 msecs_to_jiffies(WR_PHASE_SETUP_MS));
1285 }
1286
1287 if (!channel->write_phase_ready)
1288 delta_ns = 0;
1289
1290 offset_ps = (s64)delta_ns * 1000;
1291
1292
1293
1294
1295
1296
1297 if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
1298 offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
1299 else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
1300 offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
1301
1302 phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1);
1303
1304 for (i = 0; i < 4; i++) {
1305 buf[i] = phase_50ps & 0xff;
1306 phase_50ps >>= 8;
1307 }
1308
1309 err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
1310 buf, sizeof(buf));
1311
1312 return err;
1313}
1314
1315static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
1316{
1317 struct idtcm *idtcm = channel->idtcm;
1318 u8 i;
1319 bool neg_adj = 0;
1320 int err;
1321 u8 buf[6] = {0};
1322 s64 fcw;
1323
1324 if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
1325 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
1326 if (err)
1327 return err;
1328 }
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343 if (scaled_ppm < 0) {
1344 neg_adj = 1;
1345 scaled_ppm = -scaled_ppm;
1346 }
1347
1348
1349 fcw = scaled_ppm * 244140625ULL;
1350
1351 fcw = div_u64(fcw, 1776);
1352
1353 if (neg_adj)
1354 fcw = -fcw;
1355
1356 for (i = 0; i < 6; i++) {
1357 buf[i] = fcw & 0xff;
1358 fcw >>= 8;
1359 }
1360
1361 err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
1362 buf, sizeof(buf));
1363
1364 return err;
1365}
1366
1367static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
1368{
1369 struct idtcm_channel *channel =
1370 container_of(ptp, struct idtcm_channel, caps);
1371 struct idtcm *idtcm = channel->idtcm;
1372 int err;
1373
1374 mutex_lock(&idtcm->reg_lock);
1375
1376 err = _idtcm_gettime(channel, ts);
1377
1378 if (err)
1379 dev_err(&idtcm->client->dev,
1380 "Failed at line %d in func %s!\n",
1381 __LINE__,
1382 __func__);
1383
1384 mutex_unlock(&idtcm->reg_lock);
1385
1386 return err;
1387}
1388
1389static int idtcm_settime(struct ptp_clock_info *ptp,
1390 const struct timespec64 *ts)
1391{
1392 struct idtcm_channel *channel =
1393 container_of(ptp, struct idtcm_channel, caps);
1394 struct idtcm *idtcm = channel->idtcm;
1395 int err;
1396
1397 mutex_lock(&idtcm->reg_lock);
1398
1399 err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
1400
1401 if (err)
1402 dev_err(&idtcm->client->dev,
1403 "Failed at line %d in func %s!\n",
1404 __LINE__,
1405 __func__);
1406
1407 mutex_unlock(&idtcm->reg_lock);
1408
1409 return err;
1410}
1411
1412static int idtcm_settime_v487(struct ptp_clock_info *ptp,
1413 const struct timespec64 *ts)
1414{
1415 struct idtcm_channel *channel =
1416 container_of(ptp, struct idtcm_channel, caps);
1417 struct idtcm *idtcm = channel->idtcm;
1418 int err;
1419
1420 mutex_lock(&idtcm->reg_lock);
1421
1422 err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
1423
1424 if (err)
1425 dev_err(&idtcm->client->dev,
1426 "Failed at line %d in func %s!\n",
1427 __LINE__,
1428 __func__);
1429
1430 mutex_unlock(&idtcm->reg_lock);
1431
1432 return err;
1433}
1434
1435static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
1436{
1437 struct idtcm_channel *channel =
1438 container_of(ptp, struct idtcm_channel, caps);
1439 struct idtcm *idtcm = channel->idtcm;
1440 int err;
1441
1442 mutex_lock(&idtcm->reg_lock);
1443
1444 err = _idtcm_adjtime(channel, delta);
1445
1446 if (err)
1447 dev_err(&idtcm->client->dev,
1448 "Failed at line %d in func %s!\n",
1449 __LINE__,
1450 __func__);
1451
1452 mutex_unlock(&idtcm->reg_lock);
1453
1454 return err;
1455}
1456
1457static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta)
1458{
1459 struct idtcm_channel *channel =
1460 container_of(ptp, struct idtcm_channel, caps);
1461 struct idtcm *idtcm = channel->idtcm;
1462 struct timespec64 ts;
1463 enum scsr_tod_write_type_sel type;
1464 int err;
1465
1466 if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) {
1467 err = idtcm_do_phase_pull_in(channel, delta, 0);
1468 if (err)
1469 dev_err(&idtcm->client->dev,
1470 "Failed at line %d in func %s!\n",
1471 __LINE__,
1472 __func__);
1473 return err;
1474 }
1475
1476 if (delta >= 0) {
1477 ts = ns_to_timespec64(delta);
1478 type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
1479 } else {
1480 ts = ns_to_timespec64(-delta);
1481 type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
1482 }
1483
1484 mutex_lock(&idtcm->reg_lock);
1485
1486 err = _idtcm_settime_v487(channel, &ts, type);
1487
1488 if (err)
1489 dev_err(&idtcm->client->dev,
1490 "Failed at line %d in func %s!\n",
1491 __LINE__,
1492 __func__);
1493
1494 mutex_unlock(&idtcm->reg_lock);
1495
1496 return err;
1497}
1498
1499static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
1500{
1501 struct idtcm_channel *channel =
1502 container_of(ptp, struct idtcm_channel, caps);
1503
1504 struct idtcm *idtcm = channel->idtcm;
1505
1506 int err;
1507
1508 mutex_lock(&idtcm->reg_lock);
1509
1510 err = _idtcm_adjphase(channel, delta);
1511
1512 if (err)
1513 dev_err(&idtcm->client->dev,
1514 "Failed at line %d in func %s!\n",
1515 __LINE__,
1516 __func__);
1517
1518 mutex_unlock(&idtcm->reg_lock);
1519
1520 return err;
1521}
1522
1523static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
1524{
1525 struct idtcm_channel *channel =
1526 container_of(ptp, struct idtcm_channel, caps);
1527
1528 struct idtcm *idtcm = channel->idtcm;
1529
1530 int err;
1531
1532 mutex_lock(&idtcm->reg_lock);
1533
1534 err = _idtcm_adjfine(channel, scaled_ppm);
1535
1536 if (err)
1537 dev_err(&idtcm->client->dev,
1538 "Failed at line %d in func %s!\n",
1539 __LINE__,
1540 __func__);
1541
1542 mutex_unlock(&idtcm->reg_lock);
1543
1544 return err;
1545}
1546
1547static int idtcm_enable(struct ptp_clock_info *ptp,
1548 struct ptp_clock_request *rq, int on)
1549{
1550 int err;
1551
1552 struct idtcm_channel *channel =
1553 container_of(ptp, struct idtcm_channel, caps);
1554
1555 switch (rq->type) {
1556 case PTP_CLK_REQ_PEROUT:
1557 if (!on) {
1558 err = idtcm_perout_enable(channel, false, &rq->perout);
1559 if (err)
1560 dev_err(&channel->idtcm->client->dev,
1561 "Failed at line %d in func %s!\n",
1562 __LINE__,
1563 __func__);
1564 return err;
1565 }
1566
1567
1568 if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
1569 rq->perout.period.nsec)
1570 return -ERANGE;
1571
1572 err = idtcm_perout_enable(channel, true, &rq->perout);
1573 if (err)
1574 dev_err(&channel->idtcm->client->dev,
1575 "Failed at line %d in func %s!\n",
1576 __LINE__,
1577 __func__);
1578 return err;
1579 default:
1580 break;
1581 }
1582
1583 return -EOPNOTSUPP;
1584}
1585
1586static int _enable_pll_tod_sync(struct idtcm *idtcm,
1587 u8 pll,
1588 u8 sync_src,
1589 u8 qn,
1590 u8 qn_plus_1)
1591{
1592 int err;
1593 u8 val;
1594 u16 dpll;
1595 u16 out0 = 0, out1 = 0;
1596
1597 if ((qn == 0) && (qn_plus_1 == 0))
1598 return 0;
1599
1600 switch (pll) {
1601 case 0:
1602 dpll = DPLL_0;
1603 if (qn)
1604 out0 = OUTPUT_0;
1605 if (qn_plus_1)
1606 out1 = OUTPUT_1;
1607 break;
1608 case 1:
1609 dpll = DPLL_1;
1610 if (qn)
1611 out0 = OUTPUT_2;
1612 if (qn_plus_1)
1613 out1 = OUTPUT_3;
1614 break;
1615 case 2:
1616 dpll = DPLL_2;
1617 if (qn)
1618 out0 = OUTPUT_4;
1619 if (qn_plus_1)
1620 out1 = OUTPUT_5;
1621 break;
1622 case 3:
1623 dpll = DPLL_3;
1624 if (qn)
1625 out0 = OUTPUT_6;
1626 if (qn_plus_1)
1627 out1 = OUTPUT_7;
1628 break;
1629 case 4:
1630 dpll = DPLL_4;
1631 if (qn)
1632 out0 = OUTPUT_8;
1633 break;
1634 case 5:
1635 dpll = DPLL_5;
1636 if (qn)
1637 out0 = OUTPUT_9;
1638 if (qn_plus_1)
1639 out1 = OUTPUT_8;
1640 break;
1641 case 6:
1642 dpll = DPLL_6;
1643 if (qn)
1644 out0 = OUTPUT_10;
1645 if (qn_plus_1)
1646 out1 = OUTPUT_11;
1647 break;
1648 case 7:
1649 dpll = DPLL_7;
1650 if (qn)
1651 out0 = OUTPUT_11;
1652 break;
1653 default:
1654 return -EINVAL;
1655 }
1656
1657
1658
1659
1660 if (out0) {
1661 err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1662
1663 if (err)
1664 return err;
1665
1666 val &= ~OUT_SYNC_DISABLE;
1667
1668 err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
1669
1670 if (err)
1671 return err;
1672 }
1673
1674 if (out1) {
1675 err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1676
1677 if (err)
1678 return err;
1679
1680 val &= ~OUT_SYNC_DISABLE;
1681
1682 err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
1683
1684 if (err)
1685 return err;
1686 }
1687
1688
1689 err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1690 if (err)
1691 return err;
1692
1693 val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
1694 val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
1695 val |= TOD_SYNC_EN;
1696
1697 return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
1698}
1699
1700static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
1701{
1702 struct idtcm *idtcm = channel->idtcm;
1703
1704 u8 pll;
1705 u8 sync_src;
1706 u8 qn;
1707 u8 qn_plus_1;
1708 u8 cfg;
1709 int err = 0;
1710 u16 output_mask = channel->output_mask;
1711 u8 out8_mux = 0;
1712 u8 out11_mux = 0;
1713 u8 temp;
1714
1715
1716
1717
1718 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1719 if (err)
1720 return err;
1721
1722 cfg &= ~TOD_OUT_SYNC_ENABLE;
1723
1724 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1725 if (err)
1726 return err;
1727
1728 switch (channel->tod_n) {
1729 case TOD_0:
1730 sync_src = 0;
1731 break;
1732 case TOD_1:
1733 sync_src = 1;
1734 break;
1735 case TOD_2:
1736 sync_src = 2;
1737 break;
1738 case TOD_3:
1739 sync_src = 3;
1740 break;
1741 default:
1742 return -EINVAL;
1743 }
1744
1745 err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
1746 &temp, sizeof(temp));
1747 if (err)
1748 return err;
1749
1750 if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1751 Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1752 out8_mux = 1;
1753
1754 err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
1755 &temp, sizeof(temp));
1756 if (err)
1757 return err;
1758
1759 if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
1760 Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
1761 out11_mux = 1;
1762
1763 for (pll = 0; pll < 8; pll++) {
1764 qn = 0;
1765 qn_plus_1 = 0;
1766
1767 if (pll < 4) {
1768
1769 qn = output_mask & 0x1;
1770 output_mask = output_mask >> 1;
1771 qn_plus_1 = output_mask & 0x1;
1772 output_mask = output_mask >> 1;
1773 } else if (pll == 4) {
1774 if (out8_mux == 0) {
1775 qn = output_mask & 0x1;
1776 output_mask = output_mask >> 1;
1777 }
1778 } else if (pll == 5) {
1779 if (out8_mux) {
1780 qn_plus_1 = output_mask & 0x1;
1781 output_mask = output_mask >> 1;
1782 }
1783 qn = output_mask & 0x1;
1784 output_mask = output_mask >> 1;
1785 } else if (pll == 6) {
1786 qn = output_mask & 0x1;
1787 output_mask = output_mask >> 1;
1788 if (out11_mux) {
1789 qn_plus_1 = output_mask & 0x1;
1790 output_mask = output_mask >> 1;
1791 }
1792 } else if (pll == 7) {
1793 if (out11_mux == 0) {
1794 qn = output_mask & 0x1;
1795 output_mask = output_mask >> 1;
1796 }
1797 }
1798
1799 if ((qn != 0) || (qn_plus_1 != 0))
1800 err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
1801 qn_plus_1);
1802
1803 if (err)
1804 return err;
1805 }
1806
1807 return err;
1808}
1809
1810static int idtcm_enable_tod(struct idtcm_channel *channel)
1811{
1812 struct idtcm *idtcm = channel->idtcm;
1813 struct timespec64 ts = {0, 0};
1814 u8 cfg;
1815 int err;
1816
1817
1818
1819
1820 err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1821 if (err)
1822 return err;
1823
1824 cfg |= TOD_ENABLE;
1825
1826 err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
1827 if (err)
1828 return err;
1829
1830 return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
1831}
1832
1833static void idtcm_display_version_info(struct idtcm *idtcm)
1834{
1835 u8 major;
1836 u8 minor;
1837 u8 hotfix;
1838 u16 product_id;
1839 u8 hw_rev_id;
1840 u8 config_select;
1841 char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
1842
1843 idtcm_read_major_release(idtcm, &major);
1844 idtcm_read_minor_release(idtcm, &minor);
1845 idtcm_read_hotfix_release(idtcm, &hotfix);
1846
1847 idtcm_read_product_id(idtcm, &product_id);
1848 idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
1849
1850 idtcm_read_otp_scsr_config_select(idtcm, &config_select);
1851
1852 snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
1853 major, minor, hotfix);
1854
1855 dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
1856 product_id, hw_rev_id, config_select);
1857}
1858
1859static const struct ptp_clock_info idtcm_caps_v487 = {
1860 .owner = THIS_MODULE,
1861 .max_adj = 244000,
1862 .n_per_out = 12,
1863 .adjphase = &idtcm_adjphase,
1864 .adjfine = &idtcm_adjfine,
1865 .adjtime = &idtcm_adjtime_v487,
1866 .gettime64 = &idtcm_gettime,
1867 .settime64 = &idtcm_settime_v487,
1868 .enable = &idtcm_enable,
1869 .do_aux_work = &set_write_phase_ready,
1870};
1871
1872static const struct ptp_clock_info idtcm_caps = {
1873 .owner = THIS_MODULE,
1874 .max_adj = 244000,
1875 .n_per_out = 12,
1876 .adjphase = &idtcm_adjphase,
1877 .adjfine = &idtcm_adjfine,
1878 .adjtime = &idtcm_adjtime,
1879 .gettime64 = &idtcm_gettime,
1880 .settime64 = &idtcm_settime,
1881 .enable = &idtcm_enable,
1882 .do_aux_work = &set_write_phase_ready,
1883};
1884
1885static int configure_channel_pll(struct idtcm_channel *channel)
1886{
1887 int err = 0;
1888
1889 switch (channel->pll) {
1890 case 0:
1891 channel->dpll_freq = DPLL_FREQ_0;
1892 channel->dpll_n = DPLL_0;
1893 channel->hw_dpll_n = HW_DPLL_0;
1894 channel->dpll_phase = DPLL_PHASE_0;
1895 channel->dpll_ctrl_n = DPLL_CTRL_0;
1896 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
1897 break;
1898 case 1:
1899 channel->dpll_freq = DPLL_FREQ_1;
1900 channel->dpll_n = DPLL_1;
1901 channel->hw_dpll_n = HW_DPLL_1;
1902 channel->dpll_phase = DPLL_PHASE_1;
1903 channel->dpll_ctrl_n = DPLL_CTRL_1;
1904 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
1905 break;
1906 case 2:
1907 channel->dpll_freq = DPLL_FREQ_2;
1908 channel->dpll_n = DPLL_2;
1909 channel->hw_dpll_n = HW_DPLL_2;
1910 channel->dpll_phase = DPLL_PHASE_2;
1911 channel->dpll_ctrl_n = DPLL_CTRL_2;
1912 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
1913 break;
1914 case 3:
1915 channel->dpll_freq = DPLL_FREQ_3;
1916 channel->dpll_n = DPLL_3;
1917 channel->hw_dpll_n = HW_DPLL_3;
1918 channel->dpll_phase = DPLL_PHASE_3;
1919 channel->dpll_ctrl_n = DPLL_CTRL_3;
1920 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
1921 break;
1922 case 4:
1923 channel->dpll_freq = DPLL_FREQ_4;
1924 channel->dpll_n = DPLL_4;
1925 channel->hw_dpll_n = HW_DPLL_4;
1926 channel->dpll_phase = DPLL_PHASE_4;
1927 channel->dpll_ctrl_n = DPLL_CTRL_4;
1928 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
1929 break;
1930 case 5:
1931 channel->dpll_freq = DPLL_FREQ_5;
1932 channel->dpll_n = DPLL_5;
1933 channel->hw_dpll_n = HW_DPLL_5;
1934 channel->dpll_phase = DPLL_PHASE_5;
1935 channel->dpll_ctrl_n = DPLL_CTRL_5;
1936 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
1937 break;
1938 case 6:
1939 channel->dpll_freq = DPLL_FREQ_6;
1940 channel->dpll_n = DPLL_6;
1941 channel->hw_dpll_n = HW_DPLL_6;
1942 channel->dpll_phase = DPLL_PHASE_6;
1943 channel->dpll_ctrl_n = DPLL_CTRL_6;
1944 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
1945 break;
1946 case 7:
1947 channel->dpll_freq = DPLL_FREQ_7;
1948 channel->dpll_n = DPLL_7;
1949 channel->hw_dpll_n = HW_DPLL_7;
1950 channel->dpll_phase = DPLL_PHASE_7;
1951 channel->dpll_ctrl_n = DPLL_CTRL_7;
1952 channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
1953 break;
1954 default:
1955 err = -EINVAL;
1956 }
1957
1958 return err;
1959}
1960
1961static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
1962{
1963 struct idtcm_channel *channel;
1964 int err;
1965
1966 if (!(index < MAX_TOD))
1967 return -EINVAL;
1968
1969 channel = &idtcm->channel[index];
1970
1971
1972 err = configure_channel_pll(channel);
1973 if (err)
1974 return err;
1975
1976
1977 switch (index) {
1978 case 0:
1979 channel->tod_read_primary = TOD_READ_PRIMARY_0;
1980 channel->tod_write = TOD_WRITE_0;
1981 channel->tod_n = TOD_0;
1982 break;
1983 case 1:
1984 channel->tod_read_primary = TOD_READ_PRIMARY_1;
1985 channel->tod_write = TOD_WRITE_1;
1986 channel->tod_n = TOD_1;
1987 break;
1988 case 2:
1989 channel->tod_read_primary = TOD_READ_PRIMARY_2;
1990 channel->tod_write = TOD_WRITE_2;
1991 channel->tod_n = TOD_2;
1992 break;
1993 case 3:
1994 channel->tod_read_primary = TOD_READ_PRIMARY_3;
1995 channel->tod_write = TOD_WRITE_3;
1996 channel->tod_n = TOD_3;
1997 break;
1998 default:
1999 return -EINVAL;
2000 }
2001
2002 channel->idtcm = idtcm;
2003
2004 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
2005 channel->caps = idtcm_caps_v487;
2006 else
2007 channel->caps = idtcm_caps;
2008
2009 snprintf(channel->caps.name, sizeof(channel->caps.name),
2010 "IDT CM TOD%u", index);
2011
2012 if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) {
2013 err = idtcm_enable_tod_sync(channel);
2014 if (err) {
2015 dev_err(&idtcm->client->dev,
2016 "Failed at line %d in func %s!\n",
2017 __LINE__,
2018 __func__);
2019 return err;
2020 }
2021 }
2022
2023 err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
2024 if (err) {
2025 dev_err(&idtcm->client->dev,
2026 "Failed at line %d in func %s!\n",
2027 __LINE__,
2028 __func__);
2029 return err;
2030 }
2031
2032 err = idtcm_enable_tod(channel);
2033 if (err) {
2034 dev_err(&idtcm->client->dev,
2035 "Failed at line %d in func %s!\n",
2036 __LINE__,
2037 __func__);
2038 return err;
2039 }
2040
2041 channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
2042
2043 if (IS_ERR(channel->ptp_clock)) {
2044 err = PTR_ERR(channel->ptp_clock);
2045 channel->ptp_clock = NULL;
2046 return err;
2047 }
2048
2049 if (!channel->ptp_clock)
2050 return -ENOTSUPP;
2051
2052 channel->write_phase_ready = 0;
2053
2054 dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
2055 index, channel->ptp_clock->index);
2056
2057 return 0;
2058}
2059
2060static void ptp_clock_unregister_all(struct idtcm *idtcm)
2061{
2062 u8 i;
2063 struct idtcm_channel *channel;
2064
2065 for (i = 0; i < MAX_TOD; i++) {
2066
2067 channel = &idtcm->channel[i];
2068
2069 if (channel->ptp_clock)
2070 ptp_clock_unregister(channel->ptp_clock);
2071 }
2072}
2073
2074static void set_default_masks(struct idtcm *idtcm)
2075{
2076 idtcm->tod_mask = DEFAULT_TOD_MASK;
2077
2078 idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
2079 idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
2080 idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
2081 idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
2082
2083 idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
2084 idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
2085 idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
2086 idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
2087}
2088
2089static int idtcm_probe(struct i2c_client *client,
2090 const struct i2c_device_id *id)
2091{
2092 struct idtcm *idtcm;
2093 int err;
2094 u8 i;
2095 char *fmt = "Failed at %d in line %s with channel output %d!\n";
2096
2097
2098 (void)id;
2099
2100 idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
2101
2102 if (!idtcm)
2103 return -ENOMEM;
2104
2105 idtcm->client = client;
2106 idtcm->page_offset = 0xff;
2107 idtcm->calculate_overhead_flag = 0;
2108
2109 set_default_masks(idtcm);
2110
2111 mutex_init(&idtcm->reg_lock);
2112 mutex_lock(&idtcm->reg_lock);
2113
2114 idtcm_display_version_info(idtcm);
2115
2116 err = idtcm_load_firmware(idtcm, &client->dev);
2117
2118 if (err)
2119 dev_warn(&idtcm->client->dev,
2120 "loading firmware failed with %d\n", err);
2121
2122 if (idtcm->tod_mask) {
2123 for (i = 0; i < MAX_TOD; i++) {
2124 if (idtcm->tod_mask & (1 << i)) {
2125 err = idtcm_enable_channel(idtcm, i);
2126 if (err) {
2127 dev_err(&idtcm->client->dev,
2128 fmt,
2129 __LINE__,
2130 __func__,
2131 i);
2132 break;
2133 }
2134 }
2135 }
2136 } else {
2137 dev_err(&idtcm->client->dev,
2138 "no PLLs flagged as PHCs, nothing to do\n");
2139 err = -ENODEV;
2140 }
2141
2142 mutex_unlock(&idtcm->reg_lock);
2143
2144 if (err) {
2145 ptp_clock_unregister_all(idtcm);
2146 return err;
2147 }
2148
2149 i2c_set_clientdata(client, idtcm);
2150
2151 return 0;
2152}
2153
2154static int idtcm_remove(struct i2c_client *client)
2155{
2156 struct idtcm *idtcm = i2c_get_clientdata(client);
2157
2158 ptp_clock_unregister_all(idtcm);
2159
2160 mutex_destroy(&idtcm->reg_lock);
2161
2162 return 0;
2163}
2164
2165#ifdef CONFIG_OF
2166static const struct of_device_id idtcm_dt_id[] = {
2167 { .compatible = "idt,8a34000" },
2168 { .compatible = "idt,8a34001" },
2169 { .compatible = "idt,8a34002" },
2170 { .compatible = "idt,8a34003" },
2171 { .compatible = "idt,8a34004" },
2172 { .compatible = "idt,8a34005" },
2173 { .compatible = "idt,8a34006" },
2174 { .compatible = "idt,8a34007" },
2175 { .compatible = "idt,8a34008" },
2176 { .compatible = "idt,8a34009" },
2177 { .compatible = "idt,8a34010" },
2178 { .compatible = "idt,8a34011" },
2179 { .compatible = "idt,8a34012" },
2180 { .compatible = "idt,8a34013" },
2181 { .compatible = "idt,8a34014" },
2182 { .compatible = "idt,8a34015" },
2183 { .compatible = "idt,8a34016" },
2184 { .compatible = "idt,8a34017" },
2185 { .compatible = "idt,8a34018" },
2186 { .compatible = "idt,8a34019" },
2187 { .compatible = "idt,8a34040" },
2188 { .compatible = "idt,8a34041" },
2189 { .compatible = "idt,8a34042" },
2190 { .compatible = "idt,8a34043" },
2191 { .compatible = "idt,8a34044" },
2192 { .compatible = "idt,8a34045" },
2193 { .compatible = "idt,8a34046" },
2194 { .compatible = "idt,8a34047" },
2195 { .compatible = "idt,8a34048" },
2196 { .compatible = "idt,8a34049" },
2197 {},
2198};
2199MODULE_DEVICE_TABLE(of, idtcm_dt_id);
2200#endif
2201
2202static const struct i2c_device_id idtcm_i2c_id[] = {
2203 { "8a34000" },
2204 { "8a34001" },
2205 { "8a34002" },
2206 { "8a34003" },
2207 { "8a34004" },
2208 { "8a34005" },
2209 { "8a34006" },
2210 { "8a34007" },
2211 { "8a34008" },
2212 { "8a34009" },
2213 { "8a34010" },
2214 { "8a34011" },
2215 { "8a34012" },
2216 { "8a34013" },
2217 { "8a34014" },
2218 { "8a34015" },
2219 { "8a34016" },
2220 { "8a34017" },
2221 { "8a34018" },
2222 { "8a34019" },
2223 { "8a34040" },
2224 { "8a34041" },
2225 { "8a34042" },
2226 { "8a34043" },
2227 { "8a34044" },
2228 { "8a34045" },
2229 { "8a34046" },
2230 { "8a34047" },
2231 { "8a34048" },
2232 { "8a34049" },
2233 {},
2234};
2235MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
2236
2237static struct i2c_driver idtcm_driver = {
2238 .driver = {
2239 .of_match_table = of_match_ptr(idtcm_dt_id),
2240 .name = "idtcm",
2241 },
2242 .probe = idtcm_probe,
2243 .remove = idtcm_remove,
2244 .id_table = idtcm_i2c_id,
2245};
2246
2247module_i2c_driver(idtcm_driver);
2248
