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34#include "csio_hw.h"
35#include "csio_init.h"
36
37static int
38csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
39{
40 u32 mem_win_base;
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50
51
52 mem_win_base = MEMWIN_BASE;
53
54
55
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57
58
59 csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
62 csio_rd_reg32(hw,
63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
64
65 return 0;
66}
67
68
69
70
71static void
72csio_t5_pcie_intr_handler(struct csio_hw *hw)
73{
74 static struct intr_info pcie_intr_info[] = {
75 { MSTGRPPERR_F, "Master Response Read Queue parity error",
76 -1, 1 },
77 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
78 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
79 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
80 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
81 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
82 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
83 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
84 -1, 1 },
85 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
86 -1, 1 },
87 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
88 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
89 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
90 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
91 { DREQWRPERR_F, "PCI DMA channel write request parity error",
92 -1, 1 },
93 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
94 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
95 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
96 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
97 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
98 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
99 { FIDPERR_F, "PCI FID parity error", -1, 1 },
100 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
101 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
102 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
103 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
104 -1, 1 },
105 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
106 -1, 1 },
107 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
108 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
109 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
110 { READRSPERR_F, "Outbound read error", -1, 0 },
111 { 0, NULL, 0, 0 }
112 };
113
114 int fat;
115 fat = csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
116 if (fat)
117 csio_hw_fatal_err(hw);
118}
119
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126
127static unsigned int
128csio_t5_flash_cfg_addr(struct csio_hw *hw)
129{
130 return FLASH_CFG_START;
131}
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144
145static int
146csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
147 uint64_t *ecc)
148{
149 int i;
150 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
151 uint32_t mc_bist_data_pattern_reg;
152
153 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
154 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
155 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
156 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
157
158 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
159 return -EBUSY;
160 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
161 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
162 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
163 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
164 mc_bist_cmd_reg);
165 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
166 0, 10, 1, NULL);
167 if (i)
168 return i;
169
170#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
171
172 for (i = 15; i >= 0; i--)
173 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
174 if (ecc)
175 *ecc = csio_rd_reg64(hw, MC_DATA(16));
176#undef MC_DATA
177 return 0;
178}
179
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190
191
192static int
193csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
194 uint64_t *ecc)
195{
196 int i;
197 uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
198 uint32_t edc_bist_cmd_data_pattern;
199
200
201
202
203#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
204#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
205
206 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
207 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
208 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
209 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
210#undef EDC_REG_T5
211#undef EDC_STRIDE_T5
212
213 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
214 return -EBUSY;
215 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
216 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
217 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
218 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
219 edc_bist_cmd_reg);
220 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
221 0, 10, 1, NULL);
222 if (i)
223 return i;
224
225#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
226
227 for (i = 15; i >= 0; i--)
228 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
229 if (ecc)
230 *ecc = csio_rd_reg64(hw, EDC_DATA(16));
231#undef EDC_DATA
232 return 0;
233}
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251
252static int
253csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
254 u32 len, uint32_t *buf, int dir)
255{
256 u32 pos, start, offset, memoffset;
257 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
258
259
260
261
262 if ((addr & 0x3) || (len & 0x3))
263 return -EINVAL;
264
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270
271
272 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
273 if (mtype != MEM_MC1)
274 memoffset = (mtype * (edc_size * 1024 * 1024));
275 else {
276 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
277 MA_EXT_MEMORY_BAR_A));
278 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
279 }
280
281
282 addr = addr + memoffset;
283
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289
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291
292
293 mem_reg = csio_rd_reg32(hw,
294 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
295 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
296 mem_base = PCIEOFST_G(mem_reg) << 10;
297
298 start = addr & ~(mem_aperture-1);
299 offset = addr - start;
300 win_pf = PFNUM_V(hw->pfn);
301
302 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
303 mem_reg, mem_aperture);
304 csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
305 mem_base, memoffset);
306 csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n",
307 start, offset, win_pf);
308 csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
309 mtype, addr, len);
310
311 for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
312
313
314
315
316
317 csio_wr_reg32(hw, pos | win_pf,
318 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
319 csio_rd_reg32(hw,
320 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
321
322 while (offset < mem_aperture && len > 0) {
323 if (dir)
324 *buf++ = csio_rd_reg32(hw, mem_base + offset);
325 else
326 csio_wr_reg32(hw, *buf++, mem_base + offset);
327
328 offset += sizeof(__be32);
329 len -= sizeof(__be32);
330 }
331 }
332 return 0;
333}
334
335
336
337
338
339
340
341
342static void
343csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
344{
345 u32 size;
346 int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
347
348 if (i & EXT_MEM_ENABLE_F) {
349 size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
350 csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
351 EXT_MEM_SIZE_G(size));
352 }
353 if (i & EXT_MEM1_ENABLE_F) {
354 size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
355 csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
356 EXT_MEM_SIZE_G(size));
357 }
358}
359
360
361struct csio_hw_chip_ops t5_ops = {
362 .chip_set_mem_win = csio_t5_set_mem_win,
363 .chip_pcie_intr_handler = csio_t5_pcie_intr_handler,
364 .chip_flash_cfg_addr = csio_t5_flash_cfg_addr,
365 .chip_mc_read = csio_t5_mc_read,
366 .chip_edc_read = csio_t5_edc_read,
367 .chip_memory_rw = csio_t5_memory_rw,
368 .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem,
369};
370