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40
41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44#include "pm80xx_hwi.h"
45
46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47module_param(logging_level, ulong, 0644);
48MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49
50static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51module_param(link_rate, ulong, 0644);
52MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
57
58static struct scsi_transport_template *pm8001_stt;
59
60
61
62
63
64static const struct pm8001_chip_info pm8001_chips[] = {
65 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
66 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
67 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
68 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
69 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
70 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
71 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
72 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
75 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
76};
77static int pm8001_id;
78
79LIST_HEAD(hba_list);
80
81struct workqueue_struct *pm8001_wq;
82
83
84
85
86static struct scsi_host_template pm8001_sht = {
87 .module = THIS_MODULE,
88 .name = DRV_NAME,
89 .queuecommand = sas_queuecommand,
90 .dma_need_drain = ata_scsi_dma_need_drain,
91 .target_alloc = sas_target_alloc,
92 .slave_configure = sas_slave_configure,
93 .scan_finished = pm8001_scan_finished,
94 .scan_start = pm8001_scan_start,
95 .change_queue_depth = sas_change_queue_depth,
96 .bios_param = sas_bios_param,
97 .can_queue = 1,
98 .this_id = -1,
99 .sg_tablesize = PM8001_MAX_DMA_SG,
100 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
101 .eh_device_reset_handler = sas_eh_device_reset_handler,
102 .eh_target_reset_handler = sas_eh_target_reset_handler,
103 .target_destroy = sas_target_destroy,
104 .ioctl = sas_ioctl,
105#ifdef CONFIG_COMPAT
106 .compat_ioctl = sas_ioctl,
107#endif
108 .shost_attrs = pm8001_host_attrs,
109 .track_queue_depth = 1,
110};
111
112
113
114
115static struct sas_domain_function_template pm8001_transport_ops = {
116 .lldd_dev_found = pm8001_dev_found,
117 .lldd_dev_gone = pm8001_dev_gone,
118
119 .lldd_execute_task = pm8001_queue_command,
120 .lldd_control_phy = pm8001_phy_control,
121
122 .lldd_abort_task = pm8001_abort_task,
123 .lldd_abort_task_set = pm8001_abort_task_set,
124 .lldd_clear_aca = pm8001_clear_aca,
125 .lldd_clear_task_set = pm8001_clear_task_set,
126 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
127 .lldd_lu_reset = pm8001_lu_reset,
128 .lldd_query_task = pm8001_query_task,
129};
130
131
132
133
134
135
136static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
137{
138 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
139 struct asd_sas_phy *sas_phy = &phy->sas_phy;
140 phy->phy_state = PHY_LINK_DISABLE;
141 phy->pm8001_ha = pm8001_ha;
142 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
143 sas_phy->class = SAS;
144 sas_phy->iproto = SAS_PROTOCOL_ALL;
145 sas_phy->tproto = 0;
146 sas_phy->type = PHY_TYPE_PHYSICAL;
147 sas_phy->role = PHY_ROLE_INITIATOR;
148 sas_phy->oob_mode = OOB_NOT_CONNECTED;
149 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
150 sas_phy->id = phy_id;
151 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
152 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
153 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
154 sas_phy->lldd_phy = phy;
155}
156
157
158
159
160
161static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
162{
163 int i;
164
165 if (!pm8001_ha)
166 return;
167
168 for (i = 0; i < USI_MAX_MEMCNT; i++) {
169 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
170 dma_free_coherent(&pm8001_ha->pdev->dev,
171 (pm8001_ha->memoryMap.region[i].total_len +
172 pm8001_ha->memoryMap.region[i].alignment),
173 pm8001_ha->memoryMap.region[i].virt_ptr,
174 pm8001_ha->memoryMap.region[i].phys_addr);
175 }
176 }
177 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
178 flush_workqueue(pm8001_wq);
179 kfree(pm8001_ha->tags);
180 kfree(pm8001_ha);
181}
182
183#ifdef PM8001_USE_TASKLET
184
185
186
187
188
189
190static void pm8001_tasklet(unsigned long opaque)
191{
192 struct pm8001_hba_info *pm8001_ha;
193 struct isr_param *irq_vector;
194
195 irq_vector = (struct isr_param *)opaque;
196 pm8001_ha = irq_vector->drv_inst;
197 if (unlikely(!pm8001_ha))
198 BUG_ON(1);
199 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
200}
201#endif
202
203
204
205
206
207
208
209
210
211static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
212{
213 struct isr_param *irq_vector;
214 struct pm8001_hba_info *pm8001_ha;
215 irqreturn_t ret = IRQ_HANDLED;
216 irq_vector = (struct isr_param *)opaque;
217 pm8001_ha = irq_vector->drv_inst;
218
219 if (unlikely(!pm8001_ha))
220 return IRQ_NONE;
221 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
222 return IRQ_NONE;
223#ifdef PM8001_USE_TASKLET
224 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
225#else
226 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
227#endif
228 return ret;
229}
230
231
232
233
234
235
236
237static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
238{
239 struct pm8001_hba_info *pm8001_ha;
240 irqreturn_t ret = IRQ_HANDLED;
241 struct sas_ha_struct *sha = dev_id;
242 pm8001_ha = sha->lldd_ha;
243 if (unlikely(!pm8001_ha))
244 return IRQ_NONE;
245 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
246 return IRQ_NONE;
247
248#ifdef PM8001_USE_TASKLET
249 tasklet_schedule(&pm8001_ha->tasklet[0]);
250#else
251 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
252#endif
253 return ret;
254}
255
256static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
257static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
258
259
260
261
262
263
264static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
265 const struct pci_device_id *ent)
266{
267 int i;
268 spin_lock_init(&pm8001_ha->lock);
269 spin_lock_init(&pm8001_ha->bitmap_lock);
270 PM8001_INIT_DBG(pm8001_ha,
271 pm8001_printk("pm8001_alloc: PHY:%x\n",
272 pm8001_ha->chip->n_phy));
273 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
274 pm8001_phy_init(pm8001_ha, i);
275 pm8001_ha->port[i].wide_port_phymap = 0;
276 pm8001_ha->port[i].port_attached = 0;
277 pm8001_ha->port[i].port_state = 0;
278 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
279 }
280
281 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
282 if (!pm8001_ha->tags)
283 goto err_out;
284
285 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
286 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
287 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
288 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
289
290
291 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
292 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
293 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
294 pm8001_ha->memoryMap.region[IOP].alignment = 32;
295
296 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
297
298 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
299 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
300 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
301 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
302
303 if ((ent->driver_data) != chip_8001) {
304
305 pm8001_ha->memoryMap.region[IB+i].num_elements =
306 PM8001_MPI_QUEUE;
307 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
308 pm8001_ha->memoryMap.region[IB+i].total_len =
309 PM8001_MPI_QUEUE * 128;
310 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
311 } else {
312 pm8001_ha->memoryMap.region[IB+i].num_elements =
313 PM8001_MPI_QUEUE;
314 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
315 pm8001_ha->memoryMap.region[IB+i].total_len =
316 PM8001_MPI_QUEUE * 64;
317 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
318 }
319 }
320
321 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
322
323 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
324 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
325 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
326 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
327
328 if (ent->driver_data != chip_8001) {
329
330 pm8001_ha->memoryMap.region[OB+i].num_elements =
331 PM8001_MPI_QUEUE;
332 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
333 pm8001_ha->memoryMap.region[OB+i].total_len =
334 PM8001_MPI_QUEUE * 128;
335 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
336 } else {
337
338 pm8001_ha->memoryMap.region[OB+i].num_elements =
339 PM8001_MPI_QUEUE;
340 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
341 pm8001_ha->memoryMap.region[OB+i].total_len =
342 PM8001_MPI_QUEUE * 64;
343 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
344 }
345
346 }
347
348 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
349 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
350 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
351
352 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
353 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
354 sizeof(struct pm8001_device);
355 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
356 sizeof(struct pm8001_device);
357
358
359 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
360 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
361 sizeof(struct pm8001_ccb_info);
362 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
363 sizeof(struct pm8001_ccb_info);
364
365
366 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
367
368 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
369 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
370 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
371 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
372 for (i = 0; i < USI_MAX_MEMCNT; i++) {
373 if (pm8001_mem_alloc(pm8001_ha->pdev,
374 &pm8001_ha->memoryMap.region[i].virt_ptr,
375 &pm8001_ha->memoryMap.region[i].phys_addr,
376 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
377 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
378 pm8001_ha->memoryMap.region[i].total_len,
379 pm8001_ha->memoryMap.region[i].alignment) != 0) {
380 PM8001_FAIL_DBG(pm8001_ha,
381 pm8001_printk("Mem%d alloc failed\n",
382 i));
383 goto err_out;
384 }
385 }
386
387 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
388 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
389 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
390 pm8001_ha->devices[i].id = i;
391 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
392 pm8001_ha->devices[i].running_req = 0;
393 }
394 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
395 for (i = 0; i < PM8001_MAX_CCB; i++) {
396 pm8001_ha->ccb_info[i].ccb_dma_handle =
397 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
398 i * sizeof(struct pm8001_ccb_info);
399 pm8001_ha->ccb_info[i].task = NULL;
400 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
401 pm8001_ha->ccb_info[i].device = NULL;
402 ++pm8001_ha->tags_num;
403 }
404 pm8001_ha->flags = PM8001F_INIT_TIME;
405
406 pm8001_tag_init(pm8001_ha);
407 return 0;
408err_out:
409 return 1;
410}
411
412
413
414
415
416
417static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
418{
419 u32 bar;
420 u32 logicalBar = 0;
421 struct pci_dev *pdev;
422
423 pdev = pm8001_ha->pdev;
424
425 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
426
427
428
429
430
431
432
433
434 if ((bar == 1) || (bar == 3))
435 continue;
436 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
437 pm8001_ha->io_mem[logicalBar].membase =
438 pci_resource_start(pdev, bar);
439 pm8001_ha->io_mem[logicalBar].memsize =
440 pci_resource_len(pdev, bar);
441 pm8001_ha->io_mem[logicalBar].memvirtaddr =
442 ioremap(pm8001_ha->io_mem[logicalBar].membase,
443 pm8001_ha->io_mem[logicalBar].memsize);
444 PM8001_INIT_DBG(pm8001_ha,
445 pm8001_printk("PCI: bar %d, logicalBar %d ",
446 bar, logicalBar));
447 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
448 "base addr %llx virt_addr=%llx len=%d\n",
449 (u64)pm8001_ha->io_mem[logicalBar].membase,
450 (u64)(unsigned long)
451 pm8001_ha->io_mem[logicalBar].memvirtaddr,
452 pm8001_ha->io_mem[logicalBar].memsize));
453 } else {
454 pm8001_ha->io_mem[logicalBar].membase = 0;
455 pm8001_ha->io_mem[logicalBar].memsize = 0;
456 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
457 }
458 logicalBar++;
459 }
460 return 0;
461}
462
463
464
465
466
467
468
469static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
470 const struct pci_device_id *ent,
471 struct Scsi_Host *shost)
472
473{
474 struct pm8001_hba_info *pm8001_ha;
475 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
476 int j;
477
478 pm8001_ha = sha->lldd_ha;
479 if (!pm8001_ha)
480 return NULL;
481
482 pm8001_ha->pdev = pdev;
483 pm8001_ha->dev = &pdev->dev;
484 pm8001_ha->chip_id = ent->driver_data;
485 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
486 pm8001_ha->irq = pdev->irq;
487 pm8001_ha->sas = sha;
488 pm8001_ha->shost = shost;
489 pm8001_ha->id = pm8001_id++;
490 pm8001_ha->logging_level = logging_level;
491 pm8001_ha->non_fatal_count = 0;
492 if (link_rate >= 1 && link_rate <= 15)
493 pm8001_ha->link_rate = (link_rate << 8);
494 else {
495 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
496 LINKRATE_60 | LINKRATE_120;
497 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
498 "Setting link rate to default value\n"));
499 }
500 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
501
502 if (pm8001_ha->chip_id != chip_8001)
503 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
504 else
505 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
506
507#ifdef PM8001_USE_TASKLET
508
509 if ((!pdev->msix_cap || !pci_msi_enabled())
510 || (pm8001_ha->chip_id == chip_8001))
511 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
512 (unsigned long)&(pm8001_ha->irq_vector[0]));
513 else
514 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
515 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
516 (unsigned long)&(pm8001_ha->irq_vector[j]));
517#endif
518 pm8001_ioremap(pm8001_ha);
519 if (!pm8001_alloc(pm8001_ha, ent))
520 return pm8001_ha;
521 pm8001_free(pm8001_ha);
522 return NULL;
523}
524
525
526
527
528
529static int pci_go_44(struct pci_dev *pdev)
530{
531 int rc;
532
533 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
534 if (rc) {
535 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
536 if (rc)
537 dev_printk(KERN_ERR, &pdev->dev,
538 "32-bit DMA enable failed\n");
539 }
540 return rc;
541}
542
543
544
545
546
547
548static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
549 const struct pm8001_chip_info *chip_info)
550{
551 int phy_nr, port_nr;
552 struct asd_sas_phy **arr_phy;
553 struct asd_sas_port **arr_port;
554 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
555
556 phy_nr = chip_info->n_phy;
557 port_nr = phy_nr;
558 memset(sha, 0x00, sizeof(*sha));
559 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
560 if (!arr_phy)
561 goto exit;
562 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
563 if (!arr_port)
564 goto exit_free2;
565
566 sha->sas_phy = arr_phy;
567 sha->sas_port = arr_port;
568 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
569 if (!sha->lldd_ha)
570 goto exit_free1;
571
572 shost->transportt = pm8001_stt;
573 shost->max_id = PM8001_MAX_DEVICES;
574 shost->max_lun = 8;
575 shost->max_channel = 0;
576 shost->unique_id = pm8001_id;
577 shost->max_cmd_len = 16;
578 shost->can_queue = PM8001_CAN_QUEUE;
579 shost->cmd_per_lun = 32;
580 return 0;
581exit_free1:
582 kfree(arr_port);
583exit_free2:
584 kfree(arr_phy);
585exit:
586 return -1;
587}
588
589
590
591
592
593
594static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
595 const struct pm8001_chip_info *chip_info)
596{
597 int i = 0;
598 struct pm8001_hba_info *pm8001_ha;
599 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
600
601 pm8001_ha = sha->lldd_ha;
602 for (i = 0; i < chip_info->n_phy; i++) {
603 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
604 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
605 sha->sas_phy[i]->sas_addr =
606 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
607 }
608 sha->sas_ha_name = DRV_NAME;
609 sha->dev = pm8001_ha->dev;
610 sha->strict_wide_ports = 1;
611 sha->lldd_module = THIS_MODULE;
612 sha->sas_addr = &pm8001_ha->sas_addr[0];
613 sha->num_phys = chip_info->n_phy;
614 sha->core.shost = shost;
615}
616
617
618
619
620
621
622
623
624static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
625{
626 u8 i, j;
627 u8 sas_add[8];
628#ifdef PM8001_READ_VPD
629
630
631
632
633 DECLARE_COMPLETION_ONSTACK(completion);
634 struct pm8001_ioctl_payload payload;
635 u16 deviceid;
636 int rc;
637
638 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
639 pm8001_ha->nvmd_completion = &completion;
640
641 if (pm8001_ha->chip_id == chip_8001) {
642 if (deviceid == 0x8081 || deviceid == 0x0042) {
643 payload.minor_function = 4;
644 payload.rd_length = 4096;
645 } else {
646 payload.minor_function = 0;
647 payload.rd_length = 128;
648 }
649 } else if ((pm8001_ha->chip_id == chip_8070 ||
650 pm8001_ha->chip_id == chip_8072) &&
651 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
652 payload.minor_function = 4;
653 payload.rd_length = 4096;
654 } else {
655 payload.minor_function = 1;
656 payload.rd_length = 4096;
657 }
658 payload.offset = 0;
659 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
660 if (!payload.func_specific) {
661 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
662 return;
663 }
664 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
665 if (rc) {
666 kfree(payload.func_specific);
667 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
668 return;
669 }
670 wait_for_completion(&completion);
671
672 for (i = 0, j = 0; i <= 7; i++, j++) {
673 if (pm8001_ha->chip_id == chip_8001) {
674 if (deviceid == 0x8081)
675 pm8001_ha->sas_addr[j] =
676 payload.func_specific[0x704 + i];
677 else if (deviceid == 0x0042)
678 pm8001_ha->sas_addr[j] =
679 payload.func_specific[0x010 + i];
680 } else if ((pm8001_ha->chip_id == chip_8070 ||
681 pm8001_ha->chip_id == chip_8072) &&
682 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
683 pm8001_ha->sas_addr[j] =
684 payload.func_specific[0x010 + i];
685 } else
686 pm8001_ha->sas_addr[j] =
687 payload.func_specific[0x804 + i];
688 }
689 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
690 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
691 if (i && ((i % 4) == 0))
692 sas_add[7] = sas_add[7] + 4;
693 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
694 sas_add, SAS_ADDR_SIZE);
695 PM8001_INIT_DBG(pm8001_ha,
696 pm8001_printk("phy %d sas_addr = %016llx\n", i,
697 pm8001_ha->phy[i].dev_sas_addr));
698 }
699 kfree(payload.func_specific);
700#else
701 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
702 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
703 pm8001_ha->phy[i].dev_sas_addr =
704 cpu_to_be64((u64)
705 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
706 }
707 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
708 SAS_ADDR_SIZE);
709#endif
710}
711
712
713
714
715
716static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
717{
718
719#ifdef PM8001_READ_VPD
720
721 DECLARE_COMPLETION_ONSTACK(completion);
722 struct pm8001_ioctl_payload payload;
723 int rc;
724
725 pm8001_ha->nvmd_completion = &completion;
726
727 payload.minor_function = 6;
728 payload.offset = 0;
729 payload.rd_length = 4096;
730 payload.func_specific = kzalloc(4096, GFP_KERNEL);
731 if (!payload.func_specific)
732 return -ENOMEM;
733
734 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
735 if (rc) {
736 kfree(payload.func_specific);
737 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
738 return -ENOMEM;
739 }
740 wait_for_completion(&completion);
741 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
742 kfree(payload.func_specific);
743#endif
744 return 0;
745}
746
747struct pm8001_mpi3_phy_pg_trx_config {
748 u32 LaneLosCfg;
749 u32 LanePgaCfg1;
750 u32 LanePisoCfg1;
751 u32 LanePisoCfg2;
752 u32 LanePisoCfg3;
753 u32 LanePisoCfg4;
754 u32 LanePisoCfg5;
755 u32 LanePisoCfg6;
756 u32 LaneBctCtrl;
757};
758
759
760
761
762
763
764static
765void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
766 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
767{
768 phycfg->LaneLosCfg = 0x00000132;
769 phycfg->LanePgaCfg1 = 0x00203949;
770 phycfg->LanePisoCfg1 = 0x000000FF;
771 phycfg->LanePisoCfg2 = 0xFF000001;
772 phycfg->LanePisoCfg3 = 0xE7011300;
773 phycfg->LanePisoCfg4 = 0x631C40C0;
774 phycfg->LanePisoCfg5 = 0xF8102036;
775 phycfg->LanePisoCfg6 = 0xF74A1000;
776 phycfg->LaneBctCtrl = 0x00FB33F8;
777}
778
779
780
781
782
783
784static
785void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
786 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
787{
788 phycfg->LaneLosCfg = 0x00000132;
789 phycfg->LanePgaCfg1 = 0x00203949;
790 phycfg->LanePisoCfg1 = 0x000000FF;
791 phycfg->LanePisoCfg2 = 0xFF000001;
792 phycfg->LanePisoCfg3 = 0xE7011300;
793 phycfg->LanePisoCfg4 = 0x63349140;
794 phycfg->LanePisoCfg5 = 0xF8102036;
795 phycfg->LanePisoCfg6 = 0xF80D9300;
796 phycfg->LaneBctCtrl = 0x00FB33F8;
797}
798
799
800
801
802
803
804static
805void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
806{
807 switch (pm8001_ha->pdev->subsystem_device) {
808 case 0x0070:
809 case 0x0072:
810 *phymask = 0x0000;
811 break;
812
813 case 0x0071:
814 case 0x0073:
815 *phymask = 0xFFFF;
816 break;
817
818 case 0x0080:
819 *phymask = 0x00F0;
820 break;
821
822 case 0x0081:
823 *phymask = 0x0FF0;
824 break;
825
826 case 0x0082:
827 *phymask = 0xFF00;
828 break;
829
830 default:
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("Unknown subsystem device=0x%.04x",
833 pm8001_ha->pdev->subsystem_device));
834 }
835}
836
837
838
839
840
841static
842int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
843{
844 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
845 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
846 int phymask = 0;
847 int i = 0;
848
849 memset(&phycfg_int, 0, sizeof(phycfg_int));
850 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
851
852 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
853 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
854 pm8001_get_phy_mask(pm8001_ha, &phymask);
855
856 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
857 if (phymask & (1 << i)) {
858 pm8001_set_phy_profile_single(pm8001_ha, i,
859 sizeof(phycfg_int) / sizeof(u32),
860 (u32 *)&phycfg_int);
861
862 } else {
863 pm8001_set_phy_profile_single(pm8001_ha, i,
864 sizeof(phycfg_ext) / sizeof(u32),
865 (u32 *)&phycfg_ext);
866 }
867 }
868
869 return 0;
870}
871
872
873
874
875
876static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
877{
878 switch (pm8001_ha->pdev->subsystem_vendor) {
879 case PCI_VENDOR_ID_ATTO:
880 if (pm8001_ha->pdev->device == 0x0042)
881 return 0;
882 else
883 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
884
885 case PCI_VENDOR_ID_ADAPTEC2:
886 case 0:
887 return 0;
888
889 default:
890 return pm8001_get_phy_settings_info(pm8001_ha);
891 }
892}
893
894#ifdef PM8001_USE_MSIX
895
896
897
898
899static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
900{
901 u32 number_of_intr;
902 int rc;
903
904
905 if (pm8001_ha->chip_id == chip_8001) {
906 number_of_intr = 1;
907 } else {
908 number_of_intr = PM8001_MAX_MSIX_VEC;
909 }
910
911 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
912 number_of_intr, PCI_IRQ_MSIX);
913 number_of_intr = rc;
914 if (rc < 0)
915 return rc;
916 pm8001_ha->number_of_intr = number_of_intr;
917
918 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
919 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
920 rc, pm8001_ha->number_of_intr));
921 return 0;
922}
923
924static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
925{
926 u32 i = 0, j = 0;
927 int flag = 0, rc = 0;
928
929 if (pm8001_ha->chip_id != chip_8001)
930 flag &= ~IRQF_SHARED;
931
932 PM8001_INIT_DBG(pm8001_ha,
933 pm8001_printk("pci_enable_msix request number of intr %d\n",
934 pm8001_ha->number_of_intr));
935
936 for (i = 0; i < pm8001_ha->number_of_intr; i++) {
937 snprintf(pm8001_ha->intr_drvname[i],
938 sizeof(pm8001_ha->intr_drvname[0]),
939 "%s-%d", pm8001_ha->name, i);
940 pm8001_ha->irq_vector[i].irq_id = i;
941 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
942
943 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
944 pm8001_interrupt_handler_msix, flag,
945 pm8001_ha->intr_drvname[i],
946 &(pm8001_ha->irq_vector[i]));
947 if (rc) {
948 for (j = 0; j < i; j++) {
949 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
950 &(pm8001_ha->irq_vector[i]));
951 }
952 pci_free_irq_vectors(pm8001_ha->pdev);
953 break;
954 }
955 }
956
957 return rc;
958}
959#endif
960
961static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
962{
963 struct pci_dev *pdev;
964
965 pdev = pm8001_ha->pdev;
966
967#ifdef PM8001_USE_MSIX
968 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
969 return pm8001_setup_msix(pm8001_ha);
970 PM8001_INIT_DBG(pm8001_ha,
971 pm8001_printk("MSIX not supported!!!\n"));
972#endif
973 return 0;
974}
975
976
977
978
979
980static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
981{
982 struct pci_dev *pdev;
983 int rc;
984
985 pdev = pm8001_ha->pdev;
986
987#ifdef PM8001_USE_MSIX
988 if (pdev->msix_cap && pci_msi_enabled())
989 return pm8001_request_msix(pm8001_ha);
990 else {
991 PM8001_INIT_DBG(pm8001_ha,
992 pm8001_printk("MSIX not supported!!!\n"));
993 goto intx;
994 }
995#endif
996
997intx:
998
999 pm8001_ha->irq_vector[0].irq_id = 0;
1000 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1001 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1002 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1003 return rc;
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015static int pm8001_pci_probe(struct pci_dev *pdev,
1016 const struct pci_device_id *ent)
1017{
1018 unsigned int rc;
1019 u32 pci_reg;
1020 u8 i = 0;
1021 struct pm8001_hba_info *pm8001_ha;
1022 struct Scsi_Host *shost = NULL;
1023 const struct pm8001_chip_info *chip;
1024 struct sas_ha_struct *sha;
1025
1026 dev_printk(KERN_INFO, &pdev->dev,
1027 "pm80xx: driver version %s\n", DRV_VERSION);
1028 rc = pci_enable_device(pdev);
1029 if (rc)
1030 goto err_out_enable;
1031 pci_set_master(pdev);
1032
1033
1034
1035
1036
1037 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1038 pci_reg |= 0x157;
1039 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1040 rc = pci_request_regions(pdev, DRV_NAME);
1041 if (rc)
1042 goto err_out_disable;
1043 rc = pci_go_44(pdev);
1044 if (rc)
1045 goto err_out_regions;
1046
1047 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1048 if (!shost) {
1049 rc = -ENOMEM;
1050 goto err_out_regions;
1051 }
1052 chip = &pm8001_chips[ent->driver_data];
1053 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1054 if (!sha) {
1055 rc = -ENOMEM;
1056 goto err_out_free_host;
1057 }
1058 SHOST_TO_SAS_HA(shost) = sha;
1059
1060 rc = pm8001_prep_sas_ha_init(shost, chip);
1061 if (rc) {
1062 rc = -ENOMEM;
1063 goto err_out_free;
1064 }
1065 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1066
1067 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1068 if (!pm8001_ha) {
1069 rc = -ENOMEM;
1070 goto err_out_free;
1071 }
1072
1073 rc = pm8001_setup_irq(pm8001_ha);
1074 if (rc) {
1075 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1076 "pm8001_setup_irq failed [ret: %d]\n", rc));
1077 goto err_out_shost;
1078 }
1079
1080 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1081 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1082 if (rc) {
1083 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1084 "chip_init failed [ret: %d]\n", rc));
1085 goto err_out_ha_free;
1086 }
1087
1088 rc = scsi_add_host(shost, &pdev->dev);
1089 if (rc)
1090 goto err_out_ha_free;
1091
1092 rc = pm8001_request_irq(pm8001_ha);
1093 if (rc) {
1094 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1095 "pm8001_request_irq failed [ret: %d]\n", rc));
1096 goto err_out_shost;
1097 }
1098
1099 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1100 if (pm8001_ha->chip_id != chip_8001) {
1101 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1102 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1103
1104 pm80xx_set_thermal_config(pm8001_ha);
1105 }
1106
1107 pm8001_init_sas_add(pm8001_ha);
1108
1109 if (pm8001_configure_phy_settings(pm8001_ha))
1110 goto err_out_shost;
1111
1112 pm8001_post_sas_ha_init(shost, chip);
1113 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1114 if (rc) {
1115 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1116 "sas_register_ha failed [ret: %d]\n", rc));
1117 goto err_out_shost;
1118 }
1119 list_add_tail(&pm8001_ha->list, &hba_list);
1120 scsi_scan_host(pm8001_ha->shost);
1121 pm8001_ha->flags = PM8001F_RUN_TIME;
1122 return 0;
1123
1124err_out_shost:
1125 scsi_remove_host(pm8001_ha->shost);
1126err_out_ha_free:
1127 pm8001_free(pm8001_ha);
1128err_out_free:
1129 kfree(sha);
1130err_out_free_host:
1131 scsi_host_put(shost);
1132err_out_regions:
1133 pci_release_regions(pdev);
1134err_out_disable:
1135 pci_disable_device(pdev);
1136err_out_enable:
1137 return rc;
1138}
1139
1140static void pm8001_pci_remove(struct pci_dev *pdev)
1141{
1142 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1143 struct pm8001_hba_info *pm8001_ha;
1144 int i, j;
1145 pm8001_ha = sha->lldd_ha;
1146 sas_unregister_ha(sha);
1147 sas_remove_host(pm8001_ha->shost);
1148 list_del(&pm8001_ha->list);
1149 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1150 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1151
1152#ifdef PM8001_USE_MSIX
1153 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1154 synchronize_irq(pci_irq_vector(pdev, i));
1155 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1156 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1157 pci_free_irq_vectors(pdev);
1158#else
1159 free_irq(pm8001_ha->irq, sha);
1160#endif
1161#ifdef PM8001_USE_TASKLET
1162
1163 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1164 (pm8001_ha->chip_id == chip_8001))
1165 tasklet_kill(&pm8001_ha->tasklet[0]);
1166 else
1167 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1168 tasklet_kill(&pm8001_ha->tasklet[j]);
1169#endif
1170 scsi_host_put(pm8001_ha->shost);
1171 pm8001_free(pm8001_ha);
1172 kfree(sha->sas_phy);
1173 kfree(sha->sas_port);
1174 kfree(sha);
1175 pci_release_regions(pdev);
1176 pci_disable_device(pdev);
1177}
1178
1179
1180
1181
1182
1183
1184
1185
1186static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1187{
1188 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1189 struct pm8001_hba_info *pm8001_ha;
1190 int i, j;
1191 u32 device_state;
1192 pm8001_ha = sha->lldd_ha;
1193 sas_suspend_ha(sha);
1194 flush_workqueue(pm8001_wq);
1195 scsi_block_requests(pm8001_ha->shost);
1196 if (!pdev->pm_cap) {
1197 dev_err(&pdev->dev, " PCI PM not supported\n");
1198 return -ENODEV;
1199 }
1200 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1201 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1202#ifdef PM8001_USE_MSIX
1203 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1204 synchronize_irq(pci_irq_vector(pdev, i));
1205 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1206 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1207 pci_free_irq_vectors(pdev);
1208#else
1209 free_irq(pm8001_ha->irq, sha);
1210#endif
1211#ifdef PM8001_USE_TASKLET
1212
1213 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1214 (pm8001_ha->chip_id == chip_8001))
1215 tasklet_kill(&pm8001_ha->tasklet[0]);
1216 else
1217 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1218 tasklet_kill(&pm8001_ha->tasklet[j]);
1219#endif
1220 device_state = pci_choose_state(pdev, state);
1221 pm8001_printk("pdev=0x%p, slot=%s, entering "
1222 "operating state [D%d]\n", pdev,
1223 pm8001_ha->name, device_state);
1224 pci_save_state(pdev);
1225 pci_disable_device(pdev);
1226 pci_set_power_state(pdev, device_state);
1227 return 0;
1228}
1229
1230
1231
1232
1233
1234
1235
1236static int pm8001_pci_resume(struct pci_dev *pdev)
1237{
1238 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1239 struct pm8001_hba_info *pm8001_ha;
1240 int rc;
1241 u8 i = 0, j;
1242 u32 device_state;
1243 DECLARE_COMPLETION_ONSTACK(completion);
1244 pm8001_ha = sha->lldd_ha;
1245 device_state = pdev->current_state;
1246
1247 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1248 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1249
1250 pci_set_power_state(pdev, PCI_D0);
1251 pci_enable_wake(pdev, PCI_D0, 0);
1252 pci_restore_state(pdev);
1253 rc = pci_enable_device(pdev);
1254 if (rc) {
1255 pm8001_printk("slot=%s Enable device failed during resume\n",
1256 pm8001_ha->name);
1257 goto err_out_enable;
1258 }
1259
1260 pci_set_master(pdev);
1261 rc = pci_go_44(pdev);
1262 if (rc)
1263 goto err_out_disable;
1264 sas_prep_resume_ha(sha);
1265
1266 if (pm8001_ha->chip_id == chip_8001) {
1267 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1268 PM8001_INIT_DBG(pm8001_ha,
1269 pm8001_printk("chip soft reset successful\n"));
1270 }
1271 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1272 if (rc)
1273 goto err_out_disable;
1274
1275
1276 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1277
1278 rc = pm8001_request_irq(pm8001_ha);
1279 if (rc)
1280 goto err_out_disable;
1281#ifdef PM8001_USE_TASKLET
1282
1283 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1284 (pm8001_ha->chip_id == chip_8001))
1285 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1286 (unsigned long)&(pm8001_ha->irq_vector[0]));
1287 else
1288 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1289 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1290 (unsigned long)&(pm8001_ha->irq_vector[j]));
1291#endif
1292 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1293 if (pm8001_ha->chip_id != chip_8001) {
1294 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1295 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1296 }
1297
1298
1299
1300
1301
1302
1303 if (pm8001_ha->chip_id == chip_8070 ||
1304 pm8001_ha->chip_id == chip_8072) {
1305 mdelay(500);
1306 }
1307
1308
1309
1310 pm8001_ha->flags = PM8001F_RUN_TIME;
1311 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1312 pm8001_ha->phy[i].enable_completion = &completion;
1313 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1314 wait_for_completion(&completion);
1315 }
1316 sas_resume_ha(sha);
1317 return 0;
1318
1319err_out_disable:
1320 scsi_remove_host(pm8001_ha->shost);
1321 pci_disable_device(pdev);
1322err_out_enable:
1323 return rc;
1324}
1325
1326
1327
1328
1329static struct pci_device_id pm8001_pci_table[] = {
1330 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1331 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1332 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1333 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1334
1335 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1336 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1337 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1338 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1339 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1340 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1341 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1342 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1343 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1344 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1345 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1346 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1347 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1348 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1349 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1350 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1351 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1352 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1353 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1354 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1355 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1356 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1357 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1358 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1359 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1360 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1361 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1362 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1363 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1364 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1365 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1366 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1367 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1368 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1369 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1370 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1371 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1372 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1373 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1374 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1375 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1376 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1377 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1378 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1379 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1380 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1381 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1382 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1383 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1384 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1385 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1386 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1387 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1388 { PCI_VENDOR_ID_ATTO, 0x8070,
1389 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1390 { PCI_VENDOR_ID_ATTO, 0x8070,
1391 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1392 { PCI_VENDOR_ID_ATTO, 0x8072,
1393 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1394 { PCI_VENDOR_ID_ATTO, 0x8072,
1395 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1396 { PCI_VENDOR_ID_ATTO, 0x8070,
1397 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1398 { PCI_VENDOR_ID_ATTO, 0x8072,
1399 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1400 { PCI_VENDOR_ID_ATTO, 0x8072,
1401 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1402 {}
1403};
1404
1405static struct pci_driver pm8001_pci_driver = {
1406 .name = DRV_NAME,
1407 .id_table = pm8001_pci_table,
1408 .probe = pm8001_pci_probe,
1409 .remove = pm8001_pci_remove,
1410 .suspend = pm8001_pci_suspend,
1411 .resume = pm8001_pci_resume,
1412};
1413
1414
1415
1416
1417static int __init pm8001_init(void)
1418{
1419 int rc = -ENOMEM;
1420
1421 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1422 if (!pm8001_wq)
1423 goto err;
1424
1425 pm8001_id = 0;
1426 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1427 if (!pm8001_stt)
1428 goto err_wq;
1429 rc = pci_register_driver(&pm8001_pci_driver);
1430 if (rc)
1431 goto err_tp;
1432 return 0;
1433
1434err_tp:
1435 sas_release_transport(pm8001_stt);
1436err_wq:
1437 destroy_workqueue(pm8001_wq);
1438err:
1439 return rc;
1440}
1441
1442static void __exit pm8001_exit(void)
1443{
1444 pci_unregister_driver(&pm8001_pci_driver);
1445 sas_release_transport(pm8001_stt);
1446 destroy_workqueue(pm8001_wq);
1447}
1448
1449module_init(pm8001_init);
1450module_exit(pm8001_exit);
1451
1452MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1453MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1454MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1455MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1456MODULE_DESCRIPTION(
1457 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1458 "SAS/SATA controller driver");
1459MODULE_VERSION(DRV_VERSION);
1460MODULE_LICENSE("GPL");
1461MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1462
1463
