LXR linux/drivers/spi/spi-bcm2835aux.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Driver for Broadcom BCM2835 auxiliary SPI Controllers
   4 *
   5 * the driver does not rely on the native chipselects at all
   6 * but only uses the gpio type chipselects
   7 *
   8 * Based on: spi-bcm2835.c
   9 *
  10 * Copyright (C) 2015 Martin Sperl
  11 */
  12
  13#include <linux/clk.h>
  14#include <linux/completion.h>
  15#include <linux/debugfs.h>
  16#include <linux/delay.h>
  17#include <linux/err.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/kernel.h>
  21#include <linux/module.h>
  22#include <linux/of.h>
  23#include <linux/of_address.h>
  24#include <linux/of_device.h>
  25#include <linux/of_gpio.h>
  26#include <linux/of_irq.h>
  27#include <linux/regmap.h>
  28#include <linux/spi/spi.h>
  29#include <linux/spinlock.h>
  30
  31/* define polling limits */
  32static unsigned int polling_limit_us = 30;
  33module_param(polling_limit_us, uint, 0664);
  34MODULE_PARM_DESC(polling_limit_us,
  35                 "time in us to run a transfer in polling mode - if zero no polling is used\n");
  36
  37/*
  38 * spi register defines
  39 *
  40 * note there is garbage in the "official" documentation,
  41 * so some data is taken from the file:
  42 *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
  43 * inside of:
  44 *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
  45 */
  46
  47/* SPI register offsets */
  48#define BCM2835_AUX_SPI_CNTL0   0x00
  49#define BCM2835_AUX_SPI_CNTL1   0x04
  50#define BCM2835_AUX_SPI_STAT    0x08
  51#define BCM2835_AUX_SPI_PEEK    0x0C
  52#define BCM2835_AUX_SPI_IO      0x20
  53#define BCM2835_AUX_SPI_TXHOLD  0x30
  54
  55/* Bitfields in CNTL0 */
  56#define BCM2835_AUX_SPI_CNTL0_SPEED     0xFFF00000
  57#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
  58#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT       20
  59#define BCM2835_AUX_SPI_CNTL0_CS        0x000E0000
  60#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
  61#define BCM2835_AUX_SPI_CNTL0_VAR_CS    0x00008000
  62#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
  63#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD  0x00003000
  64#define BCM2835_AUX_SPI_CNTL0_ENABLE    0x00000800
  65#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
  66#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
  67#define BCM2835_AUX_SPI_CNTL0_OUT_RISING        0x00000100
  68#define BCM2835_AUX_SPI_CNTL0_CPOL      0x00000080
  69#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT  0x00000040
  70#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN  0x0000003F
  71
  72/* Bitfields in CNTL1 */
  73#define BCM2835_AUX_SPI_CNTL1_CSHIGH    0x00000700
  74#define BCM2835_AUX_SPI_CNTL1_TXEMPTY   0x00000080
  75#define BCM2835_AUX_SPI_CNTL1_IDLE      0x00000040
  76#define BCM2835_AUX_SPI_CNTL1_MSBF_IN   0x00000002
  77#define BCM2835_AUX_SPI_CNTL1_KEEP_IN   0x00000001
  78
  79/* Bitfields in STAT */
  80#define BCM2835_AUX_SPI_STAT_TX_LVL     0xFF000000
  81#define BCM2835_AUX_SPI_STAT_RX_LVL     0x00FF0000
  82#define BCM2835_AUX_SPI_STAT_TX_FULL    0x00000400
  83#define BCM2835_AUX_SPI_STAT_TX_EMPTY   0x00000200
  84#define BCM2835_AUX_SPI_STAT_RX_FULL    0x00000100
  85#define BCM2835_AUX_SPI_STAT_RX_EMPTY   0x00000080
  86#define BCM2835_AUX_SPI_STAT_BUSY       0x00000040
  87#define BCM2835_AUX_SPI_STAT_BITCOUNT   0x0000003F
  88
  89struct bcm2835aux_spi {
  90        void __iomem *regs;
  91        struct clk *clk;
  92        int irq;
  93        u32 cntl[2];
  94        const u8 *tx_buf;
  95        u8 *rx_buf;
  96        int tx_len;
  97        int rx_len;
  98        int pending;
  99
 100        u64 count_transfer_polling;
 101        u64 count_transfer_irq;
 102        u64 count_transfer_irq_after_poll;
 103
 104        struct dentry *debugfs_dir;
 105};
 106
 107#if defined(CONFIG_DEBUG_FS)
 108static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
 109                                      const char *dname)
 110{
 111        char name[64];
 112        struct dentry *dir;
 113
 114        /* get full name */
 115        snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
 116
 117        /* the base directory */
 118        dir = debugfs_create_dir(name, NULL);
 119        bs->debugfs_dir = dir;
 120
 121        /* the counters */
 122        debugfs_create_u64("count_transfer_polling", 0444, dir,
 123                           &bs->count_transfer_polling);
 124        debugfs_create_u64("count_transfer_irq", 0444, dir,
 125                           &bs->count_transfer_irq);
 126        debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
 127                           &bs->count_transfer_irq_after_poll);
 128}
 129
 130static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
 131{
 132        debugfs_remove_recursive(bs->debugfs_dir);
 133        bs->debugfs_dir = NULL;
 134}
 135#else
 136static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
 137                                      const char *dname)
 138{
 139}
 140
 141static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
 142{
 143}
 144#endif /* CONFIG_DEBUG_FS */
 145
 146static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned reg)
 147{
 148        return readl(bs->regs + reg);
 149}
 150
 151static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned reg,
 152                                 u32 val)
 153{
 154        writel(val, bs->regs + reg);
 155}
 156
 157static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
 158{
 159        u32 data;
 160        int count = min(bs->rx_len, 3);
 161
 162        data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
 163        if (bs->rx_buf) {
 164                switch (count) {
 165                case 3:
 166                        *bs->rx_buf++ = (data >> 16) & 0xff;
 167                        fallthrough;
 168                case 2:
 169                        *bs->rx_buf++ = (data >> 8) & 0xff;
 170                        fallthrough;
 171                case 1:
 172                        *bs->rx_buf++ = (data >> 0) & 0xff;
 173                        /* fallthrough - no default */
 174                }
 175        }
 176        bs->rx_len -= count;
 177        bs->pending -= count;
 178}
 179
 180static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
 181{
 182        u32 data;
 183        u8 byte;
 184        int count;
 185        int i;
 186
 187        /* gather up to 3 bytes to write to the FIFO */
 188        count = min(bs->tx_len, 3);
 189        data = 0;
 190        for (i = 0; i < count; i++) {
 191                byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 192                data |= byte << (8 * (2 - i));
 193        }
 194
 195        /* and set the variable bit-length */
 196        data |= (count * 8) << 24;
 197
 198        /* and decrement length */
 199        bs->tx_len -= count;
 200        bs->pending += count;
 201
 202        /* write to the correct TX-register */
 203        if (bs->tx_len)
 204                bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
 205        else
 206                bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
 207}
 208
 209static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
 210{
 211        /* disable spi clearing fifo and interrupts */
 212        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
 213        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
 214                      BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
 215}
 216
 217static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
 218{
 219        u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
 220
 221        /* check if we have data to read */
 222        for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
 223             stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
 224                bcm2835aux_rd_fifo(bs);
 225
 226        /* check if we have data to write */
 227        while (bs->tx_len &&
 228               (bs->pending < 12) &&
 229               (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 230                  BCM2835_AUX_SPI_STAT_TX_FULL))) {
 231                bcm2835aux_wr_fifo(bs);
 232        }
 233}
 234
 235static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
 236{
 237        struct spi_master *master = dev_id;
 238        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 239
 240        /* IRQ may be shared, so return if our interrupts are disabled */
 241        if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
 242              (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
 243                return IRQ_NONE;
 244
 245        /* do common fifo handling */
 246        bcm2835aux_spi_transfer_helper(bs);
 247
 248        if (!bs->tx_len) {
 249                /* disable tx fifo empty interrupt */
 250                bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
 251                        BCM2835_AUX_SPI_CNTL1_IDLE);
 252        }
 253
 254        /* and if rx_len is 0 then disable interrupts and wake up completion */
 255        if (!bs->rx_len) {
 256                bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 257                complete(&master->xfer_completion);
 258        }
 259
 260        return IRQ_HANDLED;
 261}
 262
 263static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
 264                                             struct spi_device *spi,
 265                                             struct spi_transfer *tfr)
 266{
 267        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 268
 269        /* enable interrupts */
 270        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
 271                BCM2835_AUX_SPI_CNTL1_TXEMPTY |
 272                BCM2835_AUX_SPI_CNTL1_IDLE);
 273
 274        /* and wait for finish... */
 275        return 1;
 276}
 277
 278static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
 279                                           struct spi_device *spi,
 280                                           struct spi_transfer *tfr)
 281{
 282        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 283
 284        /* update statistics */
 285        bs->count_transfer_irq++;
 286
 287        /* fill in registers and fifos before enabling interrupts */
 288        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 289        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 290
 291        /* fill in tx fifo with data before enabling interrupts */
 292        while ((bs->tx_len) &&
 293               (bs->pending < 12) &&
 294               (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
 295                  BCM2835_AUX_SPI_STAT_TX_FULL))) {
 296                bcm2835aux_wr_fifo(bs);
 297        }
 298
 299        /* now run the interrupt mode */
 300        return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
 301}
 302
 303static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
 304                                            struct spi_device *spi,
 305                                        struct spi_transfer *tfr)
 306{
 307        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 308        unsigned long timeout;
 309
 310        /* update statistics */
 311        bs->count_transfer_polling++;
 312
 313        /* configure spi */
 314        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 315        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 316
 317        /* set the timeout to at least 2 jiffies */
 318        timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
 319
 320        /* loop until finished the transfer */
 321        while (bs->rx_len) {
 322
 323                /* do common fifo handling */
 324                bcm2835aux_spi_transfer_helper(bs);
 325
 326                /* there is still data pending to read check the timeout */
 327                if (bs->rx_len && time_after(jiffies, timeout)) {
 328                        dev_dbg_ratelimited(&spi->dev,
 329                                            "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
 330                                            jiffies - timeout,
 331                                            bs->tx_len, bs->rx_len);
 332                        /* forward to interrupt handler */
 333                        bs->count_transfer_irq_after_poll++;
 334                        return __bcm2835aux_spi_transfer_one_irq(master,
 335                                                               spi, tfr);
 336                }
 337        }
 338
 339        /* and return without waiting for completion */
 340        return 0;
 341}
 342
 343static int bcm2835aux_spi_transfer_one(struct spi_master *master,
 344                                       struct spi_device *spi,
 345                                       struct spi_transfer *tfr)
 346{
 347        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 348        unsigned long spi_hz, clk_hz, speed;
 349        unsigned long hz_per_byte, byte_limit;
 350
 351        /* calculate the registers to handle
 352         *
 353         * note that we use the variable data mode, which
 354         * is not optimal for longer transfers as we waste registers
 355         * resulting (potentially) in more interrupts when transferring
 356         * more than 12 bytes
 357         */
 358
 359        /* set clock */
 360        spi_hz = tfr->speed_hz;
 361        clk_hz = clk_get_rate(bs->clk);
 362
 363        if (spi_hz >= clk_hz / 2) {
 364                speed = 0;
 365        } else if (spi_hz) {
 366                speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
 367                if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
 368                        speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
 369        } else { /* the slowest we can go */
 370                speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
 371        }
 372        /* mask out old speed from previous spi_transfer */
 373        bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
 374        /* set the new speed */
 375        bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
 376
 377        tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));
 378
 379        /* set transmit buffers and length */
 380        bs->tx_buf = tfr->tx_buf;
 381        bs->rx_buf = tfr->rx_buf;
 382        bs->tx_len = tfr->len;
 383        bs->rx_len = tfr->len;
 384        bs->pending = 0;
 385
 386        /* Calculate the estimated time in us the transfer runs.  Note that
 387         * there are are 2 idle clocks cycles after each chunk getting
 388         * transferred - in our case the chunk size is 3 bytes, so we
 389         * approximate this by 9 cycles/byte.  This is used to find the number
 390         * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
 391         * 30 µs per 300,000 Hz of bus clock.
 392         */
 393        hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
 394        byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
 395
 396        /* run in polling mode for short transfers */
 397        if (tfr->len < byte_limit)
 398                return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
 399
 400        /* run in interrupt mode for all others */
 401        return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
 402}
 403
 404static int bcm2835aux_spi_prepare_message(struct spi_master *master,
 405                                          struct spi_message *msg)
 406{
 407        struct spi_device *spi = msg->spi;
 408        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 409
 410        bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
 411                      BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
 412                      BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
 413        bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 414
 415        /* handle all the modes */
 416        if (spi->mode & SPI_CPOL) {
 417                bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
 418                bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
 419        } else {
 420                bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
 421        }
 422        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 423        bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
 424
 425        return 0;
 426}
 427
 428static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
 429                                            struct spi_message *msg)
 430{
 431        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 432
 433        bcm2835aux_spi_reset_hw(bs);
 434
 435        return 0;
 436}
 437
 438static void bcm2835aux_spi_handle_err(struct spi_master *master,
 439                                      struct spi_message *msg)
 440{
 441        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 442
 443        bcm2835aux_spi_reset_hw(bs);
 444}
 445
 446static int bcm2835aux_spi_setup(struct spi_device *spi)
 447{
 448        int ret;
 449
 450        /* sanity check for native cs */
 451        if (spi->mode & SPI_NO_CS)
 452                return 0;
 453        if (gpio_is_valid(spi->cs_gpio)) {
 454                /* with gpio-cs set the GPIO to the correct level
 455                 * and as output (in case the dt has the gpio not configured
 456                 * as output but native cs)
 457                 */
 458                ret = gpio_direction_output(spi->cs_gpio,
 459                                            (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 460                if (ret)
 461                        dev_err(&spi->dev,
 462                                "could not set gpio %i as output: %i\n",
 463                                spi->cs_gpio, ret);
 464
 465                return ret;
 466        }
 467
 468        /* for dt-backwards compatibility: only support native on CS0
 469         * known things not supported with broken native CS:
 470         * * multiple chip-selects: cs0-cs2 are all
 471         *     simultaniously asserted whenever there is a transfer
 472         *     this even includes SPI_NO_CS
 473         * * SPI_CS_HIGH: cs are always asserted low
 474         * * cs_change: cs is deasserted after each spi_transfer
 475         * * cs_delay_usec: cs is always deasserted one SCK cycle
 476         *     after the last transfer
 477         * probably more...
 478         */
 479        dev_warn(&spi->dev,
 480                 "Native CS is not supported - please configure cs-gpio in device-tree\n");
 481
 482        if (spi->chip_select == 0)
 483                return 0;
 484
 485        dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
 486
 487        return -EINVAL;
 488}
 489
 490static int bcm2835aux_spi_probe(struct platform_device *pdev)
 491{
 492        struct spi_master *master;
 493        struct bcm2835aux_spi *bs;
 494        unsigned long clk_hz;
 495        int err;
 496
 497        master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 498        if (!master)
 499                return -ENOMEM;
 500
 501        platform_set_drvdata(pdev, master);
 502        master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
 503        master->bits_per_word_mask = SPI_BPW_MASK(8);
 504        /* even though the driver never officially supported native CS
 505         * allow a single native CS for legacy DT support purposes when
 506         * no cs-gpio is configured.
 507         * Known limitations for native cs are:
 508         * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
 509         *     whenever there is a transfer -  this even includes SPI_NO_CS
 510         * * SPI_CS_HIGH: is ignores - cs are always asserted low
 511         * * cs_change: cs is deasserted after each spi_transfer
 512         * * cs_delay_usec: cs is always deasserted one SCK cycle after
 513         *     a spi_transfer
 514         */
 515        master->num_chipselect = 1;
 516        master->setup = bcm2835aux_spi_setup;
 517        master->transfer_one = bcm2835aux_spi_transfer_one;
 518        master->handle_err = bcm2835aux_spi_handle_err;
 519        master->prepare_message = bcm2835aux_spi_prepare_message;
 520        master->unprepare_message = bcm2835aux_spi_unprepare_message;
 521        master->dev.of_node = pdev->dev.of_node;
 522
 523        bs = spi_master_get_devdata(master);
 524
 525        /* the main area */
 526        bs->regs = devm_platform_ioremap_resource(pdev, 0);
 527        if (IS_ERR(bs->regs)) {
 528                err = PTR_ERR(bs->regs);
 529                goto out_master_put;
 530        }
 531
 532        bs->clk = devm_clk_get(&pdev->dev, NULL);
 533        if (IS_ERR(bs->clk)) {
 534                err = PTR_ERR(bs->clk);
 535                dev_err(&pdev->dev, "could not get clk: %d\n", err);
 536                goto out_master_put;
 537        }
 538
 539        bs->irq = platform_get_irq(pdev, 0);
 540        if (bs->irq <= 0) {
 541                err = bs->irq ? bs->irq : -ENODEV;
 542                goto out_master_put;
 543        }
 544
 545        /* this also enables the HW block */
 546        err = clk_prepare_enable(bs->clk);
 547        if (err) {
 548                dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
 549                goto out_master_put;
 550        }
 551
 552        /* just checking if the clock returns a sane value */
 553        clk_hz = clk_get_rate(bs->clk);
 554        if (!clk_hz) {
 555                dev_err(&pdev->dev, "clock returns 0 Hz\n");
 556                err = -ENODEV;
 557                goto out_clk_disable;
 558        }
 559
 560        /* reset SPI-HW block */
 561        bcm2835aux_spi_reset_hw(bs);
 562
 563        err = devm_request_irq(&pdev->dev, bs->irq,
 564                               bcm2835aux_spi_interrupt,
 565                               IRQF_SHARED,
 566                               dev_name(&pdev->dev), master);
 567        if (err) {
 568                dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 569                goto out_clk_disable;
 570        }
 571
 572        err = spi_register_master(master);
 573        if (err) {
 574                dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
 575                goto out_clk_disable;
 576        }
 577
 578        bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
 579
 580        return 0;
 581
 582out_clk_disable:
 583        clk_disable_unprepare(bs->clk);
 584out_master_put:
 585        spi_master_put(master);
 586        return err;
 587}
 588
 589static int bcm2835aux_spi_remove(struct platform_device *pdev)
 590{
 591        struct spi_master *master = platform_get_drvdata(pdev);
 592        struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
 593
 594        bcm2835aux_debugfs_remove(bs);
 595
 596        spi_unregister_master(master);
 597
 598        bcm2835aux_spi_reset_hw(bs);
 599
 600        /* disable the HW block by releasing the clock */
 601        clk_disable_unprepare(bs->clk);
 602
 603        return 0;
 604}
 605
 606static const struct of_device_id bcm2835aux_spi_match[] = {
 607        { .compatible = "brcm,bcm2835-aux-spi", },
 608        {}
 609};
 610MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
 611
 612static struct platform_driver bcm2835aux_spi_driver = {
 613        .driver         = {
 614                .name           = "spi-bcm2835aux",
 615                .of_match_table = bcm2835aux_spi_match,
 616        },
 617        .probe          = bcm2835aux_spi_probe,
 618        .remove         = bcm2835aux_spi_remove,
 619};
 620module_platform_driver(bcm2835aux_spi_driver);
 621
 622MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
 623MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
 624MODULE_LICENSE("GPL");
 625