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9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/delay.h>
13#include <linux/ioport.h>
14#include <linux/slab.h>
15#include <linux/errno.h>
16#include <linux/list.h>
17#include <linux/interrupt.h>
18#include <linux/proc_fs.h>
19#include <linux/clk.h>
20#include <linux/ctype.h>
21#include <linux/string.h>
22#include <linux/dma-mapping.h>
23#include <linux/workqueue.h>
24#include <linux/device.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28
29#include <linux/irq.h>
30#include <linux/gpio/consumer.h>
31
32#include "emxx_udc.h"
33
34#define DRIVER_DESC "EMXX UDC driver"
35#define DMA_ADDR_INVALID (~(dma_addr_t)0)
36
37static const char driver_name[] = "emxx_udc";
38static const char driver_desc[] = DRIVER_DESC;
39
40
41
42static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *);
43static void _nbu2ss_ep0_enable(struct nbu2ss_udc *);
44
45static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int);
46static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode);
47static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs);
48
49static int _nbu2ss_pullup(struct nbu2ss_udc *, int);
50static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *);
51
52
53
54#define _nbu2ss_zero_len_pkt(udc, epnum) \
55 _nbu2ss_ep_in_end(udc, epnum, 0, 0)
56
57
58
59static struct nbu2ss_udc udc_controller;
60
61
62
63static inline u32 _nbu2ss_readl(void __iomem *address)
64{
65 return __raw_readl(address);
66}
67
68
69
70static inline void _nbu2ss_writel(void __iomem *address, u32 udata)
71{
72 __raw_writel(udata, address);
73}
74
75
76
77static inline void _nbu2ss_bitset(void __iomem *address, u32 udata)
78{
79 u32 reg_dt = __raw_readl(address) | (udata);
80
81 __raw_writel(reg_dt, address);
82}
83
84
85
86static inline void _nbu2ss_bitclr(void __iomem *address, u32 udata)
87{
88 u32 reg_dt = __raw_readl(address) & ~(udata);
89
90 __raw_writel(reg_dt, address);
91}
92
93#ifdef UDC_DEBUG_DUMP
94
95static void _nbu2ss_dump_register(struct nbu2ss_udc *udc)
96{
97 int i;
98 u32 reg_data;
99
100 pr_info("=== %s()\n", __func__);
101
102 if (!udc) {
103 pr_err("%s udc == NULL\n", __func__);
104 return;
105 }
106
107 spin_unlock(&udc->lock);
108
109 dev_dbg(&udc->dev, "\n-USB REG-\n");
110 for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) {
111 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i));
112 dev_dbg(&udc->dev, "USB%04x =%08x", i, (int)reg_data);
113
114 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 4));
115 dev_dbg(&udc->dev, " %08x", (int)reg_data);
116
117 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 8));
118 dev_dbg(&udc->dev, " %08x", (int)reg_data);
119
120 reg_data = _nbu2ss_readl(IO_ADDRESS(USB_BASE_ADDRESS + i + 12));
121 dev_dbg(&udc->dev, " %08x\n", (int)reg_data);
122 }
123
124 spin_lock(&udc->lock);
125}
126#endif
127
128
129
130static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req)
131{
132 u8 recipient;
133 u16 selector;
134 u16 wIndex;
135 u32 test_mode;
136 struct usb_ctrlrequest *p_ctrl;
137 struct nbu2ss_udc *udc;
138
139 if (!_ep || !_req)
140 return;
141
142 udc = (struct nbu2ss_udc *)_req->context;
143 p_ctrl = &udc->ctrl;
144 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
145 if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) {
146
147
148 recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK);
149 selector = le16_to_cpu(p_ctrl->wValue);
150 if ((recipient == USB_RECIP_DEVICE) &&
151 (selector == USB_DEVICE_TEST_MODE)) {
152 wIndex = le16_to_cpu(p_ctrl->wIndex);
153 test_mode = (u32)(wIndex >> 8);
154 _nbu2ss_set_test_mode(udc, test_mode);
155 }
156 }
157 }
158}
159
160
161
162static void _nbu2ss_create_ep0_packet(struct nbu2ss_udc *udc,
163 void *p_buf, unsigned int length)
164{
165 udc->ep0_req.req.buf = p_buf;
166 udc->ep0_req.req.length = length;
167 udc->ep0_req.req.dma = 0;
168 udc->ep0_req.req.zero = true;
169 udc->ep0_req.req.complete = _nbu2ss_ep0_complete;
170 udc->ep0_req.req.status = -EINPROGRESS;
171 udc->ep0_req.req.context = udc;
172 udc->ep0_req.req.actual = 0;
173}
174
175
176
177static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc)
178{
179 u32 num, buf_type;
180 u32 data, last_ram_adr, use_ram_size;
181
182 struct ep_regs __iomem *p_ep_regs;
183
184 last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2;
185 use_ram_size = 0;
186
187 for (num = 0; num < NUM_ENDPOINTS - 1; num++) {
188 p_ep_regs = &udc->p_regs->EP_REGS[num];
189 data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS);
190 buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE;
191 if (buf_type == 0) {
192
193 use_ram_size += (data & EPN_MPKT) / sizeof(u32);
194 } else {
195
196 use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2;
197 }
198
199 if ((data >> 16) > last_ram_adr)
200 last_ram_adr = data >> 16;
201 }
202
203 return last_ram_adr + use_ram_size;
204}
205
206
207
208static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
209{
210 u32 num;
211 u32 data;
212 u32 begin_adrs;
213
214 if (ep->epnum == 0)
215 return -EINVAL;
216
217 num = ep->epnum - 1;
218
219
220
221 begin_adrs = _nbu2ss_get_begin_ram_address(udc);
222 data = (begin_adrs << 16) | ep->ep.maxpacket;
223 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data);
224
225
226
227 data = 1 << (ep->epnum + 8);
228 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data);
229
230
231
232
233 switch (ep->ep_type) {
234 case USB_ENDPOINT_XFER_BULK:
235 data = EPN_BULK;
236 break;
237
238 case USB_ENDPOINT_XFER_INT:
239 data = EPN_BUF_SINGLE | EPN_INTERRUPT;
240 break;
241
242 case USB_ENDPOINT_XFER_ISOC:
243 data = EPN_ISO;
244 break;
245
246 default:
247 data = 0;
248 break;
249 }
250
251 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
252 _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum | ep->direct));
253
254 if (ep->direct == USB_DIR_OUT) {
255
256
257 data = EPN_EN | EPN_BCLR | EPN_DIR0;
258 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
259
260 data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL;
261 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
262
263 data = EPN_OUT_EN | EPN_OUT_END_EN;
264 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
265 } else {
266
267
268 data = EPN_EN | EPN_BCLR | EPN_AUTO;
269 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
270
271 data = EPN_ISTL;
272 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
273
274 data = EPN_IN_EN | EPN_IN_END_EN;
275 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
276 }
277
278 return 0;
279}
280
281
282
283static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
284{
285 u32 num;
286 u32 data;
287
288 if ((ep->epnum == 0) || (udc->vbus_active == 0))
289 return -EINVAL;
290
291 num = ep->epnum - 1;
292
293
294
295 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0);
296
297
298
299 data = 1 << (ep->epnum + 8);
300 _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data);
301
302 if (ep->direct == USB_DIR_OUT) {
303
304
305 data = EPN_ONAK | EPN_BCLR;
306 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
307
308 data = EPN_EN | EPN_DIR0;
309 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
310
311 data = EPN_OUT_EN | EPN_OUT_END_EN;
312 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
313 } else {
314
315
316 data = EPN_BCLR;
317 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
318
319 data = EPN_EN | EPN_AUTO;
320 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
321
322 data = EPN_IN_EN | EPN_IN_END_EN;
323 _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data);
324 }
325
326 return 0;
327}
328
329
330
331static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
332{
333 u32 num;
334 u32 data;
335
336 data = _nbu2ss_readl(&udc->p_regs->USBSSCONF);
337 if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0))
338 return;
339
340 num = ep->epnum - 1;
341
342 if (ep->direct == USB_DIR_OUT) {
343
344
345 data = ep->ep.maxpacket;
346 _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data);
347
348
349
350 data = DCR1_EPN_DIR0;
351 _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data);
352
353
354
355 data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0;
356 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
357 } else {
358
359
360 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO);
361
362
363
364 data = EPN_BURST_SET | EPN_DMAMODE0;
365 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data);
366 }
367}
368
369
370
371static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
372{
373 u32 num;
374 u32 data;
375 struct fc_regs __iomem *preg = udc->p_regs;
376
377 if (udc->vbus_active == 0)
378 return;
379
380 data = _nbu2ss_readl(&preg->USBSSCONF);
381 if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0))
382 return;
383
384 num = ep->epnum - 1;
385
386 _nbu2ss_ep_dma_abort(udc, ep);
387
388 if (ep->direct == USB_DIR_OUT) {
389
390
391 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0);
392 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0);
393 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
394 } else {
395
396
397 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
398 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0);
399 }
400}
401
402
403
404static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
405{
406 struct fc_regs __iomem *preg = udc->p_regs;
407
408 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN);
409 mdelay(DMA_DISABLE_TIME);
410 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN);
411}
412
413
414
415static void _nbu2ss_ep_in_end(struct nbu2ss_udc *udc,
416 u32 epnum, u32 data32, u32 length)
417{
418 u32 data;
419 u32 num;
420 struct fc_regs __iomem *preg = udc->p_regs;
421
422 if (length >= sizeof(u32))
423 return;
424
425 if (epnum == 0) {
426 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO);
427
428
429 if (length)
430 _nbu2ss_writel(&preg->EP0_WRITE, data32);
431
432 data = ((length << 5) & EP0_DW) | EP0_DEND;
433 _nbu2ss_writel(&preg->EP0_CONTROL, data);
434
435 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO);
436 } else {
437 num = epnum - 1;
438
439 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
440
441
442 if (length)
443 _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32);
444
445 data = (((length) << 5) & EPN_DW) | EPN_DEND;
446 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
447
448 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO);
449 }
450}
451
452#ifdef USE_DMA
453
454static void _nbu2ss_dma_map_single(struct nbu2ss_udc *udc,
455 struct nbu2ss_ep *ep,
456 struct nbu2ss_req *req, u8 direct)
457{
458 if (req->req.dma == DMA_ADDR_INVALID) {
459 if (req->unaligned) {
460 req->req.dma = ep->phys_buf;
461 } else {
462 req->req.dma = dma_map_single(udc->gadget.dev.parent,
463 req->req.buf,
464 req->req.length,
465 (direct == USB_DIR_IN)
466 ? DMA_TO_DEVICE
467 : DMA_FROM_DEVICE);
468 }
469 req->mapped = 1;
470 } else {
471 if (!req->unaligned)
472 dma_sync_single_for_device(udc->gadget.dev.parent,
473 req->req.dma,
474 req->req.length,
475 (direct == USB_DIR_IN)
476 ? DMA_TO_DEVICE
477 : DMA_FROM_DEVICE);
478
479 req->mapped = 0;
480 }
481}
482
483
484static void _nbu2ss_dma_unmap_single(struct nbu2ss_udc *udc,
485 struct nbu2ss_ep *ep,
486 struct nbu2ss_req *req, u8 direct)
487{
488 u8 data[4];
489 u8 *p;
490 u32 count = 0;
491
492 if (direct == USB_DIR_OUT) {
493 count = req->req.actual % 4;
494 if (count) {
495 p = req->req.buf;
496 p += (req->req.actual - count);
497 memcpy(data, p, count);
498 }
499 }
500
501 if (req->mapped) {
502 if (req->unaligned) {
503 if (direct == USB_DIR_OUT)
504 memcpy(req->req.buf, ep->virt_buf,
505 req->req.actual & 0xfffffffc);
506 } else {
507 dma_unmap_single(udc->gadget.dev.parent,
508 req->req.dma, req->req.length,
509 (direct == USB_DIR_IN)
510 ? DMA_TO_DEVICE
511 : DMA_FROM_DEVICE);
512 }
513 req->req.dma = DMA_ADDR_INVALID;
514 req->mapped = 0;
515 } else {
516 if (!req->unaligned)
517 dma_sync_single_for_cpu(udc->gadget.dev.parent,
518 req->req.dma, req->req.length,
519 (direct == USB_DIR_IN)
520 ? DMA_TO_DEVICE
521 : DMA_FROM_DEVICE);
522 }
523
524 if (count) {
525 p = req->req.buf;
526 p += (req->req.actual - count);
527 memcpy(p, data, count);
528 }
529}
530#endif
531
532
533
534static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length)
535{
536 u32 i;
537 u32 numreads = length / sizeof(u32);
538 union usb_reg_access *buf32 = (union usb_reg_access *)buf;
539
540 if (!numreads)
541 return 0;
542
543
544 for (i = 0; i < numreads; i++) {
545 buf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
546 buf32++;
547 }
548
549 return numreads * sizeof(u32);
550}
551
552
553
554static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
555{
556 u32 i;
557 u32 i_read_size = 0;
558 union usb_reg_access temp_32;
559 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
560
561 if ((length > 0) && (length < sizeof(u32))) {
562 temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ);
563 for (i = 0 ; i < length ; i++)
564 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
565 i_read_size += length;
566 }
567
568 return i_read_size;
569}
570
571
572
573static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length)
574{
575 u32 i;
576 u32 i_max_length = EP0_PACKETSIZE;
577 u32 i_word_length = 0;
578 u32 i_write_length = 0;
579 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
580
581
582
583 if (i_max_length < length)
584 i_word_length = i_max_length / sizeof(u32);
585 else
586 i_word_length = length / sizeof(u32);
587
588
589
590 for (i = 0; i < i_word_length; i++) {
591 _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw);
592 p_buf_32++;
593 i_write_length += sizeof(u32);
594 }
595
596 return i_write_length;
597}
598
599
600
601static int ep0_in_overbytes(struct nbu2ss_udc *udc,
602 u8 *p_buf,
603 u32 i_remain_size)
604{
605 u32 i;
606 union usb_reg_access temp_32;
607 union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf;
608
609 if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) {
610 for (i = 0 ; i < i_remain_size ; i++)
611 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
612 _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size);
613
614 return i_remain_size;
615 }
616
617 return 0;
618}
619
620
621
622static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag)
623{
624 u32 data;
625
626 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
627 data &= ~(u32)EP0_INAK;
628
629 if (pid_flag)
630 data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND);
631 else
632 data |= (EP0_INAK_EN | EP0_DEND);
633
634 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
635
636 return 0;
637}
638
639
640
641static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag)
642{
643 u32 data;
644
645 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
646 data &= ~(u32)EP0_ONAK;
647
648 if (pid_flag)
649 data |= EP0_PIDCLR;
650
651 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
652
653 return 0;
654}
655
656
657static int _nbu2ss_ep0_in_transfer(struct nbu2ss_udc *udc,
658 struct nbu2ss_req *req)
659{
660 u8 *p_buffer;
661 u32 data;
662 u32 i_remain_size = 0;
663 int result = 0;
664
665
666
667 if (req->req.actual == req->req.length) {
668 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
669 if (req->zero) {
670 req->zero = false;
671 EP0_send_NULL(udc, false);
672 return 1;
673 }
674 }
675
676 return 0;
677 }
678
679
680
681 data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
682 data |= EP0_INAK_EN;
683 data &= ~(u32)EP0_INAK;
684 _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data);
685
686 i_remain_size = req->req.length - req->req.actual;
687 p_buffer = (u8 *)req->req.buf;
688 p_buffer += req->req.actual;
689
690
691
692 result = EP0_in_PIO(udc, p_buffer, i_remain_size);
693
694 req->div_len = result;
695 i_remain_size -= result;
696
697 if (i_remain_size == 0) {
698 EP0_send_NULL(udc, false);
699 return result;
700 }
701
702 if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) {
703 p_buffer += result;
704 result += ep0_in_overbytes(udc, p_buffer, i_remain_size);
705 req->div_len = result;
706 }
707
708 return result;
709}
710
711
712static int _nbu2ss_ep0_out_transfer(struct nbu2ss_udc *udc,
713 struct nbu2ss_req *req)
714{
715 u8 *p_buffer;
716 u32 i_remain_size;
717 u32 i_recv_length;
718 int result = 0;
719 int f_rcv_zero;
720
721
722
723 i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA;
724 if (i_recv_length != 0) {
725 f_rcv_zero = 0;
726
727 i_remain_size = req->req.length - req->req.actual;
728 p_buffer = (u8 *)req->req.buf;
729 p_buffer += req->req.actual;
730
731 result = ep0_out_pio(udc, p_buffer
732 , min(i_remain_size, i_recv_length));
733 if (result < 0)
734 return result;
735
736 req->req.actual += result;
737 i_recv_length -= result;
738
739 if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) {
740 p_buffer += result;
741 i_remain_size -= result;
742
743 result = ep0_out_overbytes(udc, p_buffer
744 , min(i_remain_size, i_recv_length));
745 req->req.actual += result;
746 }
747 } else {
748 f_rcv_zero = 1;
749 }
750
751
752
753 if (req->req.actual == req->req.length) {
754 if ((req->req.actual % EP0_PACKETSIZE) == 0) {
755 if (req->zero) {
756 req->zero = false;
757 EP0_receive_NULL(udc, false);
758 return 1;
759 }
760 }
761
762 return 0;
763 }
764
765 if ((req->req.actual % EP0_PACKETSIZE) != 0)
766 return 0;
767
768 if (req->req.actual > req->req.length) {
769 dev_err(udc->dev, " *** Overrun Error\n");
770 return -EOVERFLOW;
771 }
772
773 if (f_rcv_zero != 0) {
774 i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL);
775 if (i_remain_size & EP0_ONAK) {
776
777
778 _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK);
779 }
780 result = 1;
781 }
782
783 return result;
784}
785
786
787static int _nbu2ss_out_dma(struct nbu2ss_udc *udc, struct nbu2ss_req *req,
788 u32 num, u32 length)
789{
790 dma_addr_t p_buffer;
791 u32 mpkt;
792 u32 lmpkt;
793 u32 dmacnt;
794 u32 burst = 1;
795 u32 data;
796 int result = -EINVAL;
797 struct fc_regs __iomem *preg = udc->p_regs;
798
799 if (req->dma_flag)
800 return 1;
801
802 req->dma_flag = true;
803 p_buffer = req->req.dma;
804 p_buffer += req->req.actual;
805
806
807 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
808
809
810 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
811 dmacnt = length / mpkt;
812 lmpkt = (length % mpkt) & ~(u32)0x03;
813
814 if (dmacnt > DMA_MAX_COUNT) {
815 dmacnt = DMA_MAX_COUNT;
816 lmpkt = 0;
817 } else if (lmpkt != 0) {
818 if (dmacnt == 0)
819 burst = 0;
820 dmacnt++;
821 }
822
823 data = mpkt | (lmpkt << 16);
824 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
825
826 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN;
827 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
828
829 if (burst == 0) {
830 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0);
831 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
832 } else {
833 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT
834 , (dmacnt << 16));
835 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET);
836 }
837 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
838
839 result = length & ~(u32)0x03;
840 req->div_len = result;
841
842 return result;
843}
844
845
846static int _nbu2ss_epn_out_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
847 struct nbu2ss_req *req, u32 length)
848{
849 u8 *p_buffer;
850 u32 i;
851 u32 data;
852 u32 i_word_length;
853 union usb_reg_access temp_32;
854 union usb_reg_access *p_buf_32;
855 int result = 0;
856 struct fc_regs __iomem *preg = udc->p_regs;
857
858 if (req->dma_flag)
859 return 1;
860
861 if (length == 0)
862 return 0;
863
864 p_buffer = (u8 *)req->req.buf;
865 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
866
867 i_word_length = length / sizeof(u32);
868 if (i_word_length > 0) {
869
870
871 for (i = 0; i < i_word_length; i++) {
872 p_buf_32->dw =
873 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
874 p_buf_32++;
875 }
876 result = i_word_length * sizeof(u32);
877 }
878
879 data = length - result;
880 if (data > 0) {
881
882
883 temp_32.dw =
884 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ);
885 for (i = 0 ; i < data ; i++)
886 p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i];
887 result += data;
888 }
889
890 req->req.actual += result;
891
892 if ((req->req.actual == req->req.length) ||
893 ((req->req.actual % ep->ep.maxpacket) != 0)) {
894 result = 0;
895 }
896
897 return result;
898}
899
900
901static int _nbu2ss_epn_out_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
902 struct nbu2ss_req *req, u32 data_size)
903{
904 u32 num;
905 u32 i_buf_size;
906 int nret = 1;
907
908 if (ep->epnum == 0)
909 return -EINVAL;
910
911 num = ep->epnum - 1;
912
913 i_buf_size = min((req->req.length - req->req.actual), data_size);
914
915 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
916 (i_buf_size >= sizeof(u32))) {
917 nret = _nbu2ss_out_dma(udc, req, num, i_buf_size);
918 } else {
919 i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket);
920 nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size);
921 }
922
923 return nret;
924}
925
926
927static int _nbu2ss_epn_out_transfer(struct nbu2ss_udc *udc,
928 struct nbu2ss_ep *ep,
929 struct nbu2ss_req *req)
930{
931 u32 num;
932 u32 i_recv_length;
933 int result = 1;
934 struct fc_regs __iomem *preg = udc->p_regs;
935
936 if (ep->epnum == 0)
937 return -EINVAL;
938
939 num = ep->epnum - 1;
940
941
942
943 i_recv_length =
944 _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA;
945
946 if (i_recv_length != 0) {
947 result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length);
948 if (i_recv_length < ep->ep.maxpacket) {
949 if (i_recv_length == result) {
950 req->req.actual += result;
951 result = 0;
952 }
953 }
954 } else {
955 if ((req->req.actual == req->req.length) ||
956 ((req->req.actual % ep->ep.maxpacket) != 0)) {
957 result = 0;
958 }
959 }
960
961 if (result == 0) {
962 if ((req->req.actual % ep->ep.maxpacket) == 0) {
963 if (req->zero) {
964 req->zero = false;
965 return 1;
966 }
967 }
968 }
969
970 if (req->req.actual > req->req.length) {
971 dev_err(udc->dev, " Overrun Error\n");
972 dev_err(udc->dev, " actual = %d, length = %d\n",
973 req->req.actual, req->req.length);
974 result = -EOVERFLOW;
975 }
976
977 return result;
978}
979
980
981static int _nbu2ss_in_dma(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
982 struct nbu2ss_req *req, u32 num, u32 length)
983{
984 dma_addr_t p_buffer;
985 u32 mpkt;
986 u32 lmpkt;
987 u32 dmacnt;
988 u32 i_write_length;
989 u32 data;
990 int result = -EINVAL;
991 struct fc_regs __iomem *preg = udc->p_regs;
992
993 if (req->dma_flag)
994 return 1;
995
996#ifdef USE_DMA
997 if (req->req.actual == 0)
998 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN);
999#endif
1000 req->dma_flag = true;
1001
1002
1003 mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT;
1004
1005 if ((DMA_MAX_COUNT * mpkt) < length)
1006 i_write_length = DMA_MAX_COUNT * mpkt;
1007 else
1008 i_write_length = length;
1009
1010
1011
1012 if (mpkt < i_write_length) {
1013 dmacnt = i_write_length / mpkt;
1014 lmpkt = (i_write_length % mpkt) & ~(u32)0x3;
1015 if (lmpkt != 0)
1016 dmacnt++;
1017 else
1018 lmpkt = mpkt & ~(u32)0x3;
1019
1020 } else {
1021 dmacnt = 1;
1022 lmpkt = i_write_length & ~(u32)0x3;
1023 }
1024
1025
1026 data = mpkt | (lmpkt << 16);
1027 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data);
1028
1029
1030 p_buffer = req->req.dma;
1031 p_buffer += req->req.actual;
1032 _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer);
1033
1034
1035 data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN;
1036 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data);
1037
1038
1039 data = dmacnt << 16;
1040 _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data);
1041
1042
1043 _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN);
1044
1045 result = i_write_length & ~(u32)0x3;
1046 req->div_len = result;
1047
1048 return result;
1049}
1050
1051
1052static int _nbu2ss_epn_in_pio(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1053 struct nbu2ss_req *req, u32 length)
1054{
1055 u8 *p_buffer;
1056 u32 i;
1057 u32 data;
1058 u32 i_word_length;
1059 union usb_reg_access temp_32;
1060 union usb_reg_access *p_buf_32 = NULL;
1061 int result = 0;
1062 struct fc_regs __iomem *preg = udc->p_regs;
1063
1064 if (req->dma_flag)
1065 return 1;
1066
1067 if (length > 0) {
1068 p_buffer = (u8 *)req->req.buf;
1069 p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual);
1070
1071 i_word_length = length / sizeof(u32);
1072 if (i_word_length > 0) {
1073 for (i = 0; i < i_word_length; i++) {
1074 _nbu2ss_writel(
1075 &preg->EP_REGS[ep->epnum - 1].EP_WRITE,
1076 p_buf_32->dw);
1077
1078 p_buf_32++;
1079 }
1080 result = i_word_length * sizeof(u32);
1081 }
1082 }
1083
1084 if (result != ep->ep.maxpacket) {
1085 data = length - result;
1086 temp_32.dw = 0;
1087 for (i = 0 ; i < data ; i++)
1088 temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i];
1089
1090 _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data);
1091 result += data;
1092 }
1093
1094 req->div_len = result;
1095
1096 return result;
1097}
1098
1099
1100static int _nbu2ss_epn_in_data(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep,
1101 struct nbu2ss_req *req, u32 data_size)
1102{
1103 u32 num;
1104 int nret = 1;
1105
1106 if (ep->epnum == 0)
1107 return -EINVAL;
1108
1109 num = ep->epnum - 1;
1110
1111 if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) &&
1112 (data_size >= sizeof(u32))) {
1113 nret = _nbu2ss_in_dma(udc, ep, req, num, data_size);
1114 } else {
1115 data_size = min_t(u32, data_size, ep->ep.maxpacket);
1116 nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size);
1117 }
1118
1119 return nret;
1120}
1121
1122
1123static int _nbu2ss_epn_in_transfer(struct nbu2ss_udc *udc,
1124 struct nbu2ss_ep *ep, struct nbu2ss_req *req)
1125{
1126 u32 num;
1127 u32 i_buf_size;
1128 int result = 0;
1129 u32 status;
1130
1131 if (ep->epnum == 0)
1132 return -EINVAL;
1133
1134 num = ep->epnum - 1;
1135
1136 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
1137
1138
1139
1140 if (req->req.actual == 0) {
1141 if ((status & EPN_IN_EMPTY) == 0)
1142 return 1;
1143
1144 } else {
1145 if ((status & EPN_IN_FULL) != 0)
1146 return 1;
1147 }
1148
1149
1150
1151 i_buf_size = req->req.length - req->req.actual;
1152 if (i_buf_size > 0)
1153 result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size);
1154 else if (req->req.length == 0)
1155 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1156
1157 return result;
1158}
1159
1160
1161static int _nbu2ss_start_transfer(struct nbu2ss_udc *udc,
1162 struct nbu2ss_ep *ep,
1163 struct nbu2ss_req *req,
1164 bool bflag)
1165{
1166 int nret = -EINVAL;
1167
1168 req->dma_flag = false;
1169 req->div_len = 0;
1170
1171 if (req->req.length == 0) {
1172 req->zero = false;
1173 } else {
1174 if ((req->req.length % ep->ep.maxpacket) == 0)
1175 req->zero = req->req.zero;
1176 else
1177 req->zero = false;
1178 }
1179
1180 if (ep->epnum == 0) {
1181
1182 switch (udc->ep0state) {
1183 case EP0_IN_DATA_PHASE:
1184 nret = _nbu2ss_ep0_in_transfer(udc, req);
1185 break;
1186
1187 case EP0_OUT_DATA_PHASE:
1188 nret = _nbu2ss_ep0_out_transfer(udc, req);
1189 break;
1190
1191 case EP0_IN_STATUS_PHASE:
1192 nret = EP0_send_NULL(udc, true);
1193 break;
1194
1195 default:
1196 break;
1197 }
1198
1199 } else {
1200
1201 if (ep->direct == USB_DIR_OUT) {
1202
1203 if (!bflag)
1204 nret = _nbu2ss_epn_out_transfer(udc, ep, req);
1205 } else {
1206
1207 nret = _nbu2ss_epn_in_transfer(udc, ep, req);
1208 }
1209 }
1210
1211 return nret;
1212}
1213
1214
1215static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep)
1216{
1217 u32 length;
1218 bool bflag = false;
1219 struct nbu2ss_req *req;
1220
1221 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1222 if (!req)
1223 return;
1224
1225 if (ep->epnum > 0) {
1226 length = _nbu2ss_readl(
1227 &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT);
1228
1229 length &= EPN_LDATA;
1230 if (length < ep->ep.maxpacket)
1231 bflag = true;
1232 }
1233
1234 _nbu2ss_start_transfer(ep->udc, ep, req, bflag);
1235}
1236
1237
1238
1239static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs)
1240{
1241 u8 num;
1242 u32 data;
1243
1244 if ((ep_adrs == 0) || (ep_adrs == 0x80))
1245 return;
1246
1247 num = (ep_adrs & 0x7F) - 1;
1248
1249 if (ep_adrs & USB_DIR_IN)
1250 data = EPN_IPIDCLR;
1251 else
1252 data = EPN_BCLR | EPN_OPIDCLR;
1253
1254 _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data);
1255}
1256
1257
1258
1259static void _nbu2ss_set_endpoint_stall(struct nbu2ss_udc *udc,
1260 u8 ep_adrs, bool bstall)
1261{
1262 u8 num, epnum;
1263 u32 data;
1264 struct nbu2ss_ep *ep;
1265 struct fc_regs __iomem *preg = udc->p_regs;
1266
1267 if ((ep_adrs == 0) || (ep_adrs == 0x80)) {
1268 if (bstall) {
1269
1270 _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL);
1271 } else {
1272
1273 _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL);
1274 }
1275 } else {
1276 epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK;
1277 num = epnum - 1;
1278 ep = &udc->ep[epnum];
1279
1280 if (bstall) {
1281
1282 ep->halted = true;
1283
1284 if (ep_adrs & USB_DIR_IN)
1285 data = EPN_BCLR | EPN_ISTL;
1286 else
1287 data = EPN_OSTL_EN | EPN_OSTL;
1288
1289 _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data);
1290 } else {
1291
1292 ep->stalled = false;
1293 if (ep_adrs & USB_DIR_IN) {
1294 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL
1295 , EPN_ISTL);
1296 } else {
1297 data =
1298 _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL);
1299
1300 data &= ~EPN_OSTL;
1301 data |= EPN_OSTL_EN;
1302
1303 _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL
1304 , data);
1305 }
1306
1307 ep->stalled = false;
1308 if (ep->halted) {
1309 ep->halted = false;
1310 _nbu2ss_restert_transfer(ep);
1311 }
1312 }
1313 }
1314}
1315
1316
1317static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode)
1318{
1319 u32 data;
1320
1321 if (mode > MAX_TEST_MODE_NUM)
1322 return;
1323
1324 dev_info(udc->dev, "SET FEATURE : test mode = %d\n", mode);
1325
1326 data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL);
1327 data &= ~TEST_FORCE_ENABLE;
1328 data |= mode << TEST_MODE_SHIFT;
1329
1330 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data);
1331 _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN);
1332}
1333
1334
1335static int _nbu2ss_set_feature_device(struct nbu2ss_udc *udc,
1336 u16 selector, u16 wIndex)
1337{
1338 int result = -EOPNOTSUPP;
1339
1340 switch (selector) {
1341 case USB_DEVICE_REMOTE_WAKEUP:
1342 if (wIndex == 0x0000) {
1343 udc->remote_wakeup = U2F_ENABLE;
1344 result = 0;
1345 }
1346 break;
1347
1348 case USB_DEVICE_TEST_MODE:
1349 wIndex >>= 8;
1350 if (wIndex <= MAX_TEST_MODE_NUM)
1351 result = 0;
1352 break;
1353
1354 default:
1355 break;
1356 }
1357
1358 return result;
1359}
1360
1361
1362static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs)
1363{
1364 u8 epnum;
1365 u32 data = 0, bit_data;
1366 struct fc_regs __iomem *preg = udc->p_regs;
1367
1368 epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK;
1369 if (epnum == 0) {
1370 data = _nbu2ss_readl(&preg->EP0_CONTROL);
1371 bit_data = EP0_STL;
1372
1373 } else {
1374 data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL);
1375 if ((data & EPN_EN) == 0)
1376 return -1;
1377
1378 if (ep_adrs & USB_ENDPOINT_DIR_MASK)
1379 bit_data = EPN_ISTL;
1380 else
1381 bit_data = EPN_OSTL;
1382 }
1383
1384 if ((data & bit_data) == 0)
1385 return 0;
1386 return 1;
1387}
1388
1389
1390static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset)
1391{
1392 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1393 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1394 u16 selector = le16_to_cpu(udc->ctrl.wValue);
1395 u16 wIndex = le16_to_cpu(udc->ctrl.wIndex);
1396 u8 ep_adrs;
1397 int result = -EOPNOTSUPP;
1398
1399 if ((udc->ctrl.wLength != 0x0000) ||
1400 (direction != USB_DIR_OUT)) {
1401 return -EINVAL;
1402 }
1403
1404 switch (recipient) {
1405 case USB_RECIP_DEVICE:
1406 if (bset)
1407 result =
1408 _nbu2ss_set_feature_device(udc, selector, wIndex);
1409 break;
1410
1411 case USB_RECIP_ENDPOINT:
1412 if (0x0000 == (wIndex & 0xFF70)) {
1413 if (selector == USB_ENDPOINT_HALT) {
1414 ep_adrs = wIndex & 0xFF;
1415 if (!bset) {
1416 _nbu2ss_endpoint_toggle_reset(udc,
1417 ep_adrs);
1418 }
1419
1420 _nbu2ss_set_endpoint_stall(udc, ep_adrs, bset);
1421
1422 result = 0;
1423 }
1424 }
1425 break;
1426
1427 default:
1428 break;
1429 }
1430
1431 if (result >= 0)
1432 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1433
1434 return result;
1435}
1436
1437
1438static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc)
1439{
1440 u32 data;
1441 enum usb_device_speed speed = USB_SPEED_FULL;
1442
1443 data = _nbu2ss_readl(&udc->p_regs->USB_STATUS);
1444 if (data & HIGH_SPEED)
1445 speed = USB_SPEED_HIGH;
1446
1447 return speed;
1448}
1449
1450
1451static void _nbu2ss_epn_set_stall(struct nbu2ss_udc *udc,
1452 struct nbu2ss_ep *ep)
1453{
1454 u8 ep_adrs;
1455 u32 regdata;
1456 int limit_cnt = 0;
1457
1458 struct fc_regs __iomem *preg = udc->p_regs;
1459
1460 if (ep->direct == USB_DIR_IN) {
1461 for (limit_cnt = 0
1462 ; limit_cnt < IN_DATA_EMPTY_COUNT
1463 ; limit_cnt++) {
1464 regdata = _nbu2ss_readl(
1465 &preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1466
1467 if ((regdata & EPN_IN_DATA) == 0)
1468 break;
1469
1470 mdelay(1);
1471 }
1472 }
1473
1474 ep_adrs = ep->epnum | ep->direct;
1475 _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1);
1476}
1477
1478
1479static int std_req_get_status(struct nbu2ss_udc *udc)
1480{
1481 u32 length;
1482 u16 status_data = 0;
1483 u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK);
1484 u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN);
1485 u8 ep_adrs;
1486 int result = -EINVAL;
1487
1488 if ((udc->ctrl.wValue != 0x0000) || (direction != USB_DIR_IN))
1489 return result;
1490
1491 length =
1492 min_t(u16, le16_to_cpu(udc->ctrl.wLength), sizeof(status_data));
1493 switch (recipient) {
1494 case USB_RECIP_DEVICE:
1495 if (udc->ctrl.wIndex == 0x0000) {
1496 if (udc->gadget.is_selfpowered)
1497 status_data |= BIT(USB_DEVICE_SELF_POWERED);
1498
1499 if (udc->remote_wakeup)
1500 status_data |= BIT(USB_DEVICE_REMOTE_WAKEUP);
1501
1502 result = 0;
1503 }
1504 break;
1505
1506 case USB_RECIP_ENDPOINT:
1507 if (0x0000 == (le16_to_cpu(udc->ctrl.wIndex) & 0xFF70)) {
1508 ep_adrs = (u8)(le16_to_cpu(udc->ctrl.wIndex) & 0xFF);
1509 result = _nbu2ss_get_ep_stall(udc, ep_adrs);
1510
1511 if (result > 0)
1512 status_data |= BIT(USB_ENDPOINT_HALT);
1513 }
1514 break;
1515
1516 default:
1517 break;
1518 }
1519
1520 if (result >= 0) {
1521 memcpy(udc->ep0_buf, &status_data, length);
1522 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length);
1523 _nbu2ss_ep0_in_transfer(udc, &udc->ep0_req);
1524
1525 } else {
1526 dev_err(udc->dev, " Error GET_STATUS\n");
1527 }
1528
1529 return result;
1530}
1531
1532
1533static int std_req_clear_feature(struct nbu2ss_udc *udc)
1534{
1535 return _nbu2ss_req_feature(udc, false);
1536}
1537
1538
1539static int std_req_set_feature(struct nbu2ss_udc *udc)
1540{
1541 return _nbu2ss_req_feature(udc, true);
1542}
1543
1544
1545static int std_req_set_address(struct nbu2ss_udc *udc)
1546{
1547 int result = 0;
1548 u32 wValue = le16_to_cpu(udc->ctrl.wValue);
1549
1550 if ((udc->ctrl.bRequestType != 0x00) ||
1551 (udc->ctrl.wIndex != 0x0000) ||
1552 (udc->ctrl.wLength != 0x0000)) {
1553 return -EINVAL;
1554 }
1555
1556 if (wValue != (wValue & 0x007F))
1557 return -EINVAL;
1558
1559 wValue <<= USB_ADRS_SHIFT;
1560
1561 _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue);
1562 _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0);
1563
1564 return result;
1565}
1566
1567
1568static int std_req_set_configuration(struct nbu2ss_udc *udc)
1569{
1570 u32 config_value = (u32)(le16_to_cpu(udc->ctrl.wValue) & 0x00ff);
1571
1572 if ((udc->ctrl.wIndex != 0x0000) ||
1573 (udc->ctrl.wLength != 0x0000) ||
1574 (udc->ctrl.bRequestType != 0x00)) {
1575 return -EINVAL;
1576 }
1577
1578 udc->curr_config = config_value;
1579
1580 if (config_value > 0) {
1581 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF);
1582 udc->devstate = USB_STATE_CONFIGURED;
1583
1584 } else {
1585 _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF);
1586 udc->devstate = USB_STATE_ADDRESS;
1587 }
1588
1589 return 0;
1590}
1591
1592
1593static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata)
1594{
1595 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0);
1596 pdata++;
1597 *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1);
1598}
1599
1600
1601static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc)
1602{
1603 bool bcall_back = true;
1604 int nret = -EINVAL;
1605 struct usb_ctrlrequest *p_ctrl;
1606
1607 p_ctrl = &udc->ctrl;
1608 _nbu2ss_read_request_data(udc, (u32 *)p_ctrl);
1609
1610
1611 if (p_ctrl->wLength == 0) {
1612 udc->ep0state = EP0_IN_STATUS_PHASE;
1613
1614 } else {
1615 if (p_ctrl->bRequestType & USB_DIR_IN)
1616 udc->ep0state = EP0_IN_DATA_PHASE;
1617 else
1618 udc->ep0state = EP0_OUT_DATA_PHASE;
1619 }
1620
1621 if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1622 switch (p_ctrl->bRequest) {
1623 case USB_REQ_GET_STATUS:
1624 nret = std_req_get_status(udc);
1625 bcall_back = false;
1626 break;
1627
1628 case USB_REQ_CLEAR_FEATURE:
1629 nret = std_req_clear_feature(udc);
1630 bcall_back = false;
1631 break;
1632
1633 case USB_REQ_SET_FEATURE:
1634 nret = std_req_set_feature(udc);
1635 bcall_back = false;
1636 break;
1637
1638 case USB_REQ_SET_ADDRESS:
1639 nret = std_req_set_address(udc);
1640 bcall_back = false;
1641 break;
1642
1643 case USB_REQ_SET_CONFIGURATION:
1644 nret = std_req_set_configuration(udc);
1645 break;
1646
1647 default:
1648 break;
1649 }
1650 }
1651
1652 if (!bcall_back) {
1653 if (udc->ep0state == EP0_IN_STATUS_PHASE) {
1654 if (nret >= 0) {
1655
1656
1657 nret = EP0_send_NULL(udc, true);
1658 }
1659 }
1660
1661 } else {
1662 spin_unlock(&udc->lock);
1663 nret = udc->driver->setup(&udc->gadget, &udc->ctrl);
1664 spin_lock(&udc->lock);
1665 }
1666
1667 if (nret < 0)
1668 udc->ep0state = EP0_IDLE;
1669
1670 return nret;
1671}
1672
1673
1674static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc)
1675{
1676 int nret;
1677 struct nbu2ss_req *req;
1678 struct nbu2ss_ep *ep = &udc->ep[0];
1679
1680 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1681 if (!req)
1682 req = &udc->ep0_req;
1683
1684 req->req.actual += req->div_len;
1685 req->div_len = 0;
1686
1687 nret = _nbu2ss_ep0_in_transfer(udc, req);
1688 if (nret == 0) {
1689 udc->ep0state = EP0_OUT_STATUS_PAHSE;
1690 EP0_receive_NULL(udc, true);
1691 }
1692
1693 return 0;
1694}
1695
1696
1697static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc)
1698{
1699 int nret;
1700 struct nbu2ss_req *req;
1701 struct nbu2ss_ep *ep = &udc->ep[0];
1702
1703 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1704 if (!req)
1705 req = &udc->ep0_req;
1706
1707 nret = _nbu2ss_ep0_out_transfer(udc, req);
1708 if (nret == 0) {
1709 udc->ep0state = EP0_IN_STATUS_PHASE;
1710 EP0_send_NULL(udc, true);
1711
1712 } else if (nret < 0) {
1713 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR);
1714 req->req.status = nret;
1715 }
1716
1717 return 0;
1718}
1719
1720
1721static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc)
1722{
1723 struct nbu2ss_req *req;
1724 struct nbu2ss_ep *ep = &udc->ep[0];
1725
1726 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
1727 if (!req) {
1728 req = &udc->ep0_req;
1729 if (req->req.complete)
1730 req->req.complete(&ep->ep, &req->req);
1731
1732 } else {
1733 if (req->req.complete)
1734 _nbu2ss_ep_done(ep, req, 0);
1735 }
1736
1737 udc->ep0state = EP0_IDLE;
1738
1739 return 0;
1740}
1741
1742
1743static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc)
1744{
1745 int i;
1746 u32 status;
1747 u32 intr;
1748 int nret = -1;
1749
1750 status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS);
1751 intr = status & EP0_STATUS_RW_BIT;
1752 _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~intr);
1753
1754 status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT
1755 | STG_END_INT | EP0_OUT_NULL_INT);
1756
1757 if (status == 0) {
1758 dev_info(udc->dev, "%s Not Decode Interrupt\n", __func__);
1759 dev_info(udc->dev, "EP0_STATUS = 0x%08x\n", intr);
1760 return;
1761 }
1762
1763 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1764 udc->gadget.speed = _nbu2ss_get_speed(udc);
1765
1766 for (i = 0; i < EP0_END_XFER; i++) {
1767 switch (udc->ep0state) {
1768 case EP0_IDLE:
1769 if (status & SETUP_INT) {
1770 status = 0;
1771 nret = _nbu2ss_decode_request(udc);
1772 }
1773 break;
1774
1775 case EP0_IN_DATA_PHASE:
1776 if (status & EP0_IN_INT) {
1777 status &= ~EP0_IN_INT;
1778 nret = _nbu2ss_ep0_in_data_stage(udc);
1779 }
1780 break;
1781
1782 case EP0_OUT_DATA_PHASE:
1783 if (status & EP0_OUT_INT) {
1784 status &= ~EP0_OUT_INT;
1785 nret = _nbu2ss_ep0_out_data_stage(udc);
1786 }
1787 break;
1788
1789 case EP0_IN_STATUS_PHASE:
1790 if ((status & STG_END_INT) || (status & SETUP_INT)) {
1791 status &= ~(STG_END_INT | EP0_IN_INT);
1792 nret = _nbu2ss_ep0_status_stage(udc);
1793 }
1794 break;
1795
1796 case EP0_OUT_STATUS_PAHSE:
1797 if ((status & STG_END_INT) || (status & SETUP_INT) ||
1798 (status & EP0_OUT_NULL_INT)) {
1799 status &= ~(STG_END_INT
1800 | EP0_OUT_INT
1801 | EP0_OUT_NULL_INT);
1802
1803 nret = _nbu2ss_ep0_status_stage(udc);
1804 }
1805
1806 break;
1807
1808 default:
1809 status = 0;
1810 break;
1811 }
1812
1813 if (status == 0)
1814 break;
1815 }
1816
1817 if (nret < 0) {
1818
1819 _nbu2ss_set_endpoint_stall(udc, 0, true);
1820 }
1821}
1822
1823
1824static void _nbu2ss_ep_done(struct nbu2ss_ep *ep,
1825 struct nbu2ss_req *req,
1826 int status)
1827{
1828 struct nbu2ss_udc *udc = ep->udc;
1829
1830 list_del_init(&req->queue);
1831
1832 if (status == -ECONNRESET)
1833 _nbu2ss_fifo_flush(udc, ep);
1834
1835 if (likely(req->req.status == -EINPROGRESS))
1836 req->req.status = status;
1837
1838 if (ep->stalled) {
1839 _nbu2ss_epn_set_stall(udc, ep);
1840 } else {
1841 if (!list_empty(&ep->queue))
1842 _nbu2ss_restert_transfer(ep);
1843 }
1844
1845#ifdef USE_DMA
1846 if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) &&
1847 (req->req.dma != 0))
1848 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT);
1849#endif
1850
1851 spin_unlock(&udc->lock);
1852 req->req.complete(&ep->ep, &req->req);
1853 spin_lock(&udc->lock);
1854}
1855
1856
1857static inline void _nbu2ss_epn_in_int(struct nbu2ss_udc *udc,
1858 struct nbu2ss_ep *ep,
1859 struct nbu2ss_req *req)
1860{
1861 int result = 0;
1862 u32 status;
1863
1864 struct fc_regs __iomem *preg = udc->p_regs;
1865
1866 if (req->dma_flag)
1867 return;
1868
1869 req->req.actual += req->div_len;
1870 req->div_len = 0;
1871
1872 if (req->req.actual != req->req.length) {
1873
1874
1875 result = _nbu2ss_epn_in_transfer(udc, ep, req);
1876
1877 } else {
1878 if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) {
1879 status =
1880 _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS);
1881
1882 if ((status & EPN_IN_FULL) == 0) {
1883
1884
1885 req->zero = false;
1886 _nbu2ss_zero_len_pkt(udc, ep->epnum);
1887 }
1888 return;
1889 }
1890 }
1891
1892 if (result <= 0) {
1893
1894
1895 _nbu2ss_ep_done(ep, req, result);
1896 }
1897}
1898
1899
1900static inline void _nbu2ss_epn_out_int(struct nbu2ss_udc *udc,
1901 struct nbu2ss_ep *ep,
1902 struct nbu2ss_req *req)
1903{
1904 int result;
1905
1906 result = _nbu2ss_epn_out_transfer(udc, ep, req);
1907 if (result <= 0)
1908 _nbu2ss_ep_done(ep, req, result);
1909}
1910
1911
1912static inline void _nbu2ss_epn_in_dma_int(struct nbu2ss_udc *udc,
1913 struct nbu2ss_ep *ep,
1914 struct nbu2ss_req *req)
1915{
1916 u32 mpkt;
1917 u32 size;
1918 struct usb_request *preq;
1919
1920 preq = &req->req;
1921
1922 if (!req->dma_flag)
1923 return;
1924
1925 preq->actual += req->div_len;
1926 req->div_len = 0;
1927 req->dma_flag = false;
1928
1929#ifdef USE_DMA
1930 _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN);
1931#endif
1932
1933 if (preq->actual != preq->length) {
1934 _nbu2ss_epn_in_transfer(udc, ep, req);
1935 } else {
1936 mpkt = ep->ep.maxpacket;
1937 size = preq->actual % mpkt;
1938 if (size > 0) {
1939 if (((preq->actual & 0x03) == 0) && (size < mpkt))
1940 _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0);
1941 } else {
1942 _nbu2ss_epn_in_int(udc, ep, req);
1943 }
1944 }
1945}
1946
1947
1948static inline void _nbu2ss_epn_out_dma_int(struct nbu2ss_udc *udc,
1949 struct nbu2ss_ep *ep,
1950 struct nbu2ss_req *req)
1951{
1952 int i;
1953 u32 num;
1954 u32 dmacnt, ep_dmacnt;
1955 u32 mpkt;
1956 struct fc_regs __iomem *preg = udc->p_regs;
1957
1958 num = ep->epnum - 1;
1959
1960 if (req->req.actual == req->req.length) {
1961 if ((req->req.length % ep->ep.maxpacket) && !req->zero) {
1962 req->div_len = 0;
1963 req->dma_flag = false;
1964 _nbu2ss_ep_done(ep, req, 0);
1965 return;
1966 }
1967 }
1968
1969 ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT)
1970 & EPN_DMACNT;
1971 ep_dmacnt >>= 16;
1972
1973 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
1974 dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1)
1975 & DCR1_EPN_DMACNT;
1976 dmacnt >>= 16;
1977 if (ep_dmacnt == dmacnt)
1978 break;
1979 }
1980
1981 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN);
1982
1983 if (dmacnt != 0) {
1984 mpkt = ep->ep.maxpacket;
1985 if ((req->div_len % mpkt) == 0)
1986 req->div_len -= mpkt * dmacnt;
1987 }
1988
1989 if ((req->req.actual % ep->ep.maxpacket) > 0) {
1990 if (req->req.actual == req->div_len) {
1991 req->div_len = 0;
1992 req->dma_flag = false;
1993 _nbu2ss_ep_done(ep, req, 0);
1994 return;
1995 }
1996 }
1997
1998 req->req.actual += req->div_len;
1999 req->div_len = 0;
2000 req->dma_flag = false;
2001
2002 _nbu2ss_epn_out_int(udc, ep, req);
2003}
2004
2005
2006static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum)
2007{
2008 u32 num;
2009 u32 status;
2010
2011 struct nbu2ss_req *req;
2012 struct nbu2ss_ep *ep = &udc->ep[epnum];
2013
2014 num = epnum - 1;
2015
2016
2017 status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS);
2018
2019
2020 _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~status);
2021
2022 req = list_first_entry_or_null(&ep->queue, struct nbu2ss_req, queue);
2023 if (!req) {
2024
2025 return;
2026 }
2027
2028 if (status & EPN_OUT_END_INT) {
2029 status &= ~EPN_OUT_INT;
2030 _nbu2ss_epn_out_dma_int(udc, ep, req);
2031 }
2032
2033 if (status & EPN_OUT_INT)
2034 _nbu2ss_epn_out_int(udc, ep, req);
2035
2036 if (status & EPN_IN_END_INT) {
2037 status &= ~EPN_IN_INT;
2038 _nbu2ss_epn_in_dma_int(udc, ep, req);
2039 }
2040
2041 if (status & EPN_IN_INT)
2042 _nbu2ss_epn_in_int(udc, ep, req);
2043}
2044
2045
2046static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum)
2047{
2048 if (epnum == 0)
2049 _nbu2ss_ep0_int(udc);
2050 else
2051 _nbu2ss_epn_int(udc, epnum);
2052}
2053
2054
2055static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc)
2056{
2057 _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR));
2058 _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT);
2059}
2060
2061
2062static int _nbu2ss_nuke(struct nbu2ss_udc *udc,
2063 struct nbu2ss_ep *ep,
2064 int status)
2065{
2066 struct nbu2ss_req *req;
2067
2068
2069 _nbu2ss_epn_exit(udc, ep);
2070
2071
2072 _nbu2ss_ep_dma_exit(udc, ep);
2073
2074 if (list_empty(&ep->queue))
2075 return 0;
2076
2077
2078 list_for_each_entry(req, &ep->queue, queue) {
2079 _nbu2ss_ep_done(ep, req, status);
2080 }
2081
2082 return 0;
2083}
2084
2085
2086static void _nbu2ss_quiesce(struct nbu2ss_udc *udc)
2087{
2088 struct nbu2ss_ep *ep;
2089
2090 udc->gadget.speed = USB_SPEED_UNKNOWN;
2091
2092 _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN);
2093
2094
2095 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2096 _nbu2ss_nuke(udc, ep, -ESHUTDOWN);
2097 }
2098}
2099
2100
2101static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on)
2102{
2103 u32 reg_dt;
2104
2105 if (udc->vbus_active == 0)
2106 return -ESHUTDOWN;
2107
2108 if (is_on) {
2109
2110 if (udc->driver) {
2111 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL)
2112 | PUE2) & ~(u32)CONNECTB;
2113
2114 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2115 }
2116
2117 } else {
2118
2119 reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB)
2120 & ~(u32)PUE2;
2121
2122 _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt);
2123 udc->gadget.speed = USB_SPEED_UNKNOWN;
2124 }
2125
2126 return 0;
2127}
2128
2129
2130static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep)
2131{
2132 struct fc_regs __iomem *p = udc->p_regs;
2133
2134 if (udc->vbus_active == 0)
2135 return;
2136
2137 if (ep->epnum == 0) {
2138
2139 _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR);
2140
2141 } else {
2142
2143 _nbu2ss_ep_dma_abort(udc, ep);
2144 _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR);
2145 }
2146}
2147
2148
2149static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc)
2150{
2151 int waitcnt = 0;
2152
2153 if (udc->udc_enabled)
2154 return 0;
2155
2156
2157 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2158 udelay(EPC_RST_DISABLE_TIME);
2159
2160 _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD);
2161 mdelay(EPC_DIRPD_DISABLE_TIME);
2162
2163 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2164
2165 _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE);
2166
2167 _nbu2ss_writel(&udc->p_regs->AHBMCTR,
2168 HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE);
2169
2170 while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) {
2171 waitcnt++;
2172 udelay(1);
2173 if (waitcnt == EPC_PLL_LOCK_COUNT) {
2174 dev_err(udc->dev, "*** Reset Cancel failed\n");
2175 return -EINVAL;
2176 }
2177 }
2178
2179 _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET);
2180
2181 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV));
2182
2183
2184 _nbu2ss_ep0_enable(udc);
2185
2186
2187 _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT);
2188
2189 udc->udc_enabled = true;
2190
2191 return 0;
2192}
2193
2194
2195static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc)
2196{
2197 _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST);
2198 _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST);
2199}
2200
2201
2202static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc)
2203{
2204 if (udc->udc_enabled) {
2205 udc->udc_enabled = false;
2206 _nbu2ss_reset_controller(udc);
2207 _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST));
2208 }
2209}
2210
2211
2212static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc)
2213{
2214 int nret;
2215 u32 reg_dt;
2216
2217
2218 mdelay(VBUS_CHATTERING_MDELAY);
2219
2220
2221 reg_dt = gpiod_get_value(vbus_gpio);
2222 if (reg_dt == 0) {
2223 udc->linux_suspended = 0;
2224
2225 _nbu2ss_reset_controller(udc);
2226 dev_info(udc->dev, " ----- VBUS OFF\n");
2227
2228 if (udc->vbus_active == 1) {
2229
2230 udc->vbus_active = 0;
2231 if (udc->usb_suspended) {
2232 udc->usb_suspended = 0;
2233
2234 }
2235 udc->devstate = USB_STATE_NOTATTACHED;
2236
2237 _nbu2ss_quiesce(udc);
2238 if (udc->driver) {
2239 spin_unlock(&udc->lock);
2240 udc->driver->disconnect(&udc->gadget);
2241 spin_lock(&udc->lock);
2242 }
2243
2244 _nbu2ss_disable_controller(udc);
2245 }
2246 } else {
2247 mdelay(5);
2248 reg_dt = gpiod_get_value(vbus_gpio);
2249 if (reg_dt == 0)
2250 return;
2251
2252 dev_info(udc->dev, " ----- VBUS ON\n");
2253
2254 if (udc->linux_suspended)
2255 return;
2256
2257 if (udc->vbus_active == 0) {
2258
2259 udc->vbus_active = 1;
2260 udc->devstate = USB_STATE_POWERED;
2261
2262 nret = _nbu2ss_enable_controller(udc);
2263 if (nret < 0) {
2264 _nbu2ss_disable_controller(udc);
2265 udc->vbus_active = 0;
2266 return;
2267 }
2268
2269 _nbu2ss_pullup(udc, 1);
2270
2271#ifdef UDC_DEBUG_DUMP
2272 _nbu2ss_dump_register(udc);
2273#endif
2274
2275 } else {
2276 if (udc->devstate == USB_STATE_POWERED)
2277 _nbu2ss_pullup(udc, 1);
2278 }
2279 }
2280}
2281
2282
2283static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc)
2284{
2285 udc->devstate = USB_STATE_DEFAULT;
2286 udc->remote_wakeup = 0;
2287
2288 _nbu2ss_quiesce(udc);
2289
2290 udc->ep0state = EP0_IDLE;
2291}
2292
2293
2294static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc)
2295{
2296 if (udc->usb_suspended == 1) {
2297 udc->usb_suspended = 0;
2298 if (udc->driver && udc->driver->resume) {
2299 spin_unlock(&udc->lock);
2300 udc->driver->resume(&udc->gadget);
2301 spin_lock(&udc->lock);
2302 }
2303 }
2304}
2305
2306
2307static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc)
2308{
2309 u32 reg_dt;
2310
2311 if (udc->usb_suspended == 0) {
2312 reg_dt = gpiod_get_value(vbus_gpio);
2313
2314 if (reg_dt == 0)
2315 return;
2316
2317 udc->usb_suspended = 1;
2318 if (udc->driver && udc->driver->suspend) {
2319 spin_unlock(&udc->lock);
2320 udc->driver->suspend(&udc->gadget);
2321 spin_lock(&udc->lock);
2322 }
2323
2324 _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND);
2325 }
2326}
2327
2328
2329
2330static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc)
2331{
2332 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2333
2334 spin_lock(&udc->lock);
2335 _nbu2ss_check_vbus(udc);
2336 spin_unlock(&udc->lock);
2337
2338 return IRQ_HANDLED;
2339}
2340
2341
2342
2343static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc)
2344{
2345 u8 suspend_flag = 0;
2346 u32 status;
2347 u32 epnum, int_bit;
2348
2349 struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc;
2350 struct fc_regs __iomem *preg = udc->p_regs;
2351
2352 if (gpiod_get_value(vbus_gpio) == 0) {
2353 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2354 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2355 return IRQ_HANDLED;
2356 }
2357
2358 spin_lock(&udc->lock);
2359
2360 for (;;) {
2361 if (gpiod_get_value(vbus_gpio) == 0) {
2362 _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW);
2363 _nbu2ss_writel(&preg->USB_INT_ENA, 0);
2364 status = 0;
2365 } else {
2366 status = _nbu2ss_readl(&preg->USB_INT_STA);
2367 }
2368
2369 if (status == 0)
2370 break;
2371
2372 _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW));
2373
2374 if (status & USB_RST_INT) {
2375
2376 _nbu2ss_int_bus_reset(udc);
2377 }
2378
2379 if (status & RSUM_INT) {
2380
2381 _nbu2ss_int_usb_resume(udc);
2382 }
2383
2384 if (status & SPND_INT) {
2385
2386 suspend_flag = 1;
2387 }
2388
2389 if (status & EPN_INT) {
2390
2391 int_bit = status >> 8;
2392
2393 for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) {
2394 if (0x01 & int_bit)
2395 _nbu2ss_ep_int(udc, epnum);
2396
2397 int_bit >>= 1;
2398
2399 if (int_bit == 0)
2400 break;
2401 }
2402 }
2403 }
2404
2405 if (suspend_flag)
2406 _nbu2ss_int_usb_suspend(udc);
2407
2408 spin_unlock(&udc->lock);
2409
2410 return IRQ_HANDLED;
2411}
2412
2413
2414
2415static int nbu2ss_ep_enable(struct usb_ep *_ep,
2416 const struct usb_endpoint_descriptor *desc)
2417{
2418 u8 ep_type;
2419 unsigned long flags;
2420
2421 struct nbu2ss_ep *ep;
2422 struct nbu2ss_udc *udc;
2423
2424 if (!_ep || !desc) {
2425 pr_err(" *** %s, bad param\n", __func__);
2426 return -EINVAL;
2427 }
2428
2429 ep = container_of(_ep, struct nbu2ss_ep, ep);
2430 if (!ep->udc) {
2431 pr_err(" *** %s, ep == NULL !!\n", __func__);
2432 return -EINVAL;
2433 }
2434
2435 ep_type = usb_endpoint_type(desc);
2436 if ((ep_type == USB_ENDPOINT_XFER_CONTROL) ||
2437 (ep_type == USB_ENDPOINT_XFER_ISOC)) {
2438 pr_err(" *** %s, bat bmAttributes\n", __func__);
2439 return -EINVAL;
2440 }
2441
2442 udc = ep->udc;
2443 if (udc->vbus_active == 0)
2444 return -ESHUTDOWN;
2445
2446 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
2447 dev_err(ep->udc->dev, " *** %s, udc !!\n", __func__);
2448 return -ESHUTDOWN;
2449 }
2450
2451 spin_lock_irqsave(&udc->lock, flags);
2452
2453 ep->desc = desc;
2454 ep->epnum = usb_endpoint_num(desc);
2455 ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
2456 ep->ep_type = ep_type;
2457 ep->wedged = 0;
2458 ep->halted = false;
2459 ep->stalled = false;
2460
2461 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
2462
2463
2464 _nbu2ss_ep_dma_init(udc, ep);
2465
2466
2467 _nbu2ss_ep_init(udc, ep);
2468
2469 spin_unlock_irqrestore(&udc->lock, flags);
2470
2471 return 0;
2472}
2473
2474
2475static int nbu2ss_ep_disable(struct usb_ep *_ep)
2476{
2477 struct nbu2ss_ep *ep;
2478 struct nbu2ss_udc *udc;
2479 unsigned long flags;
2480
2481 if (!_ep) {
2482 pr_err(" *** %s, bad param\n", __func__);
2483 return -EINVAL;
2484 }
2485
2486 ep = container_of(_ep, struct nbu2ss_ep, ep);
2487 if (!ep->udc) {
2488 pr_err("udc: *** %s, ep == NULL !!\n", __func__);
2489 return -EINVAL;
2490 }
2491
2492 udc = ep->udc;
2493 if (udc->vbus_active == 0)
2494 return -ESHUTDOWN;
2495
2496 spin_lock_irqsave(&udc->lock, flags);
2497 _nbu2ss_nuke(udc, ep, -EINPROGRESS);
2498 spin_unlock_irqrestore(&udc->lock, flags);
2499
2500 return 0;
2501}
2502
2503
2504static struct usb_request *nbu2ss_ep_alloc_request(struct usb_ep *ep,
2505 gfp_t gfp_flags)
2506{
2507 struct nbu2ss_req *req;
2508
2509 req = kzalloc(sizeof(*req), gfp_flags);
2510 if (!req)
2511 return NULL;
2512
2513#ifdef USE_DMA
2514 req->req.dma = DMA_ADDR_INVALID;
2515#endif
2516 INIT_LIST_HEAD(&req->queue);
2517
2518 return &req->req;
2519}
2520
2521
2522static void nbu2ss_ep_free_request(struct usb_ep *_ep,
2523 struct usb_request *_req)
2524{
2525 struct nbu2ss_req *req;
2526
2527 if (_req) {
2528 req = container_of(_req, struct nbu2ss_req, req);
2529
2530 kfree(req);
2531 }
2532}
2533
2534
2535static int nbu2ss_ep_queue(struct usb_ep *_ep,
2536 struct usb_request *_req, gfp_t gfp_flags)
2537{
2538 struct nbu2ss_req *req;
2539 struct nbu2ss_ep *ep;
2540 struct nbu2ss_udc *udc;
2541 unsigned long flags;
2542 bool bflag;
2543 int result = -EINVAL;
2544
2545
2546 if (!_ep || !_req) {
2547 if (!_ep)
2548 pr_err("udc: %s --- _ep == NULL\n", __func__);
2549
2550 if (!_req)
2551 pr_err("udc: %s --- _req == NULL\n", __func__);
2552
2553 return -EINVAL;
2554 }
2555
2556 req = container_of(_req, struct nbu2ss_req, req);
2557 if (unlikely(!_req->complete ||
2558 !_req->buf ||
2559 !list_empty(&req->queue))) {
2560 if (!_req->complete)
2561 pr_err("udc: %s --- !_req->complete\n", __func__);
2562
2563 if (!_req->buf)
2564 pr_err("udc:%s --- !_req->buf\n", __func__);
2565
2566 if (!list_empty(&req->queue))
2567 pr_err("%s --- !list_empty(&req->queue)\n", __func__);
2568
2569 return -EINVAL;
2570 }
2571
2572 ep = container_of(_ep, struct nbu2ss_ep, ep);
2573 udc = ep->udc;
2574
2575 if (udc->vbus_active == 0) {
2576 dev_info(udc->dev, "Can't ep_queue (VBUS OFF)\n");
2577 return -ESHUTDOWN;
2578 }
2579
2580 if (unlikely(!udc->driver)) {
2581 dev_err(udc->dev, "%s, bogus device state %p\n", __func__,
2582 udc->driver);
2583 return -ESHUTDOWN;
2584 }
2585
2586 spin_lock_irqsave(&udc->lock, flags);
2587
2588#ifdef USE_DMA
2589 if ((uintptr_t)req->req.buf & 0x3)
2590 req->unaligned = true;
2591 else
2592 req->unaligned = false;
2593
2594 if (req->unaligned) {
2595 if (!ep->virt_buf)
2596 ep->virt_buf = dma_alloc_coherent(NULL, PAGE_SIZE,
2597 &ep->phys_buf,
2598 GFP_ATOMIC | GFP_DMA);
2599 if (ep->epnum > 0) {
2600 if (ep->direct == USB_DIR_IN)
2601 memcpy(ep->virt_buf, req->req.buf,
2602 req->req.length);
2603 }
2604 }
2605
2606 if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) &&
2607 (req->req.dma != 0))
2608 _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT);
2609#endif
2610
2611 _req->status = -EINPROGRESS;
2612 _req->actual = 0;
2613
2614 bflag = list_empty(&ep->queue);
2615 list_add_tail(&req->queue, &ep->queue);
2616
2617 if (bflag && !ep->stalled) {
2618 result = _nbu2ss_start_transfer(udc, ep, req, false);
2619 if (result < 0) {
2620 dev_err(udc->dev, " *** %s, result = %d\n", __func__,
2621 result);
2622 list_del(&req->queue);
2623 } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) {
2624#ifdef USE_DMA
2625 if (req->req.length < 4 &&
2626 req->req.length == req->req.actual)
2627#else
2628 if (req->req.length == req->req.actual)
2629#endif
2630 _nbu2ss_ep_done(ep, req, result);
2631 }
2632 }
2633
2634 spin_unlock_irqrestore(&udc->lock, flags);
2635
2636 return 0;
2637}
2638
2639
2640static int nbu2ss_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
2641{
2642 struct nbu2ss_req *req;
2643 struct nbu2ss_ep *ep;
2644 struct nbu2ss_udc *udc;
2645 unsigned long flags;
2646
2647
2648 if (!_ep || !_req) {
2649
2650 return -EINVAL;
2651 }
2652
2653 ep = container_of(_ep, struct nbu2ss_ep, ep);
2654
2655 udc = ep->udc;
2656 if (!udc)
2657 return -EINVAL;
2658
2659 spin_lock_irqsave(&udc->lock, flags);
2660
2661
2662 list_for_each_entry(req, &ep->queue, queue) {
2663 if (&req->req == _req) {
2664 _nbu2ss_ep_done(ep, req, -ECONNRESET);
2665 spin_unlock_irqrestore(&udc->lock, flags);
2666 return 0;
2667 }
2668 }
2669
2670 spin_unlock_irqrestore(&udc->lock, flags);
2671
2672 pr_debug("%s no queue(EINVAL)\n", __func__);
2673
2674 return -EINVAL;
2675}
2676
2677
2678static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value)
2679{
2680 u8 ep_adrs;
2681 unsigned long flags;
2682
2683 struct nbu2ss_ep *ep;
2684 struct nbu2ss_udc *udc;
2685
2686 if (!_ep) {
2687 pr_err("%s, bad param\n", __func__);
2688 return -EINVAL;
2689 }
2690
2691 ep = container_of(_ep, struct nbu2ss_ep, ep);
2692
2693 udc = ep->udc;
2694 if (!udc) {
2695 dev_err(ep->udc->dev, " *** %s, bad udc\n", __func__);
2696 return -EINVAL;
2697 }
2698
2699 spin_lock_irqsave(&udc->lock, flags);
2700
2701 ep_adrs = ep->epnum | ep->direct;
2702 if (value == 0) {
2703 _nbu2ss_set_endpoint_stall(udc, ep_adrs, value);
2704 ep->stalled = false;
2705 } else {
2706 if (list_empty(&ep->queue))
2707 _nbu2ss_epn_set_stall(udc, ep);
2708 else
2709 ep->stalled = true;
2710 }
2711
2712 if (value == 0)
2713 ep->wedged = 0;
2714
2715 spin_unlock_irqrestore(&udc->lock, flags);
2716
2717 return 0;
2718}
2719
2720static int nbu2ss_ep_set_wedge(struct usb_ep *_ep)
2721{
2722 return nbu2ss_ep_set_halt(_ep, 1);
2723}
2724
2725
2726static int nbu2ss_ep_fifo_status(struct usb_ep *_ep)
2727{
2728 u32 data;
2729 struct nbu2ss_ep *ep;
2730 struct nbu2ss_udc *udc;
2731 unsigned long flags;
2732 struct fc_regs __iomem *preg;
2733
2734 if (!_ep) {
2735 pr_err("%s, bad param\n", __func__);
2736 return -EINVAL;
2737 }
2738
2739 ep = container_of(_ep, struct nbu2ss_ep, ep);
2740
2741 udc = ep->udc;
2742 if (!udc) {
2743 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2744 return -EINVAL;
2745 }
2746
2747 preg = udc->p_regs;
2748
2749 data = gpiod_get_value(vbus_gpio);
2750 if (data == 0)
2751 return -EINVAL;
2752
2753 spin_lock_irqsave(&udc->lock, flags);
2754
2755 if (ep->epnum == 0) {
2756 data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA;
2757
2758 } else {
2759 data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT)
2760 & EPN_LDATA;
2761 }
2762
2763 spin_unlock_irqrestore(&udc->lock, flags);
2764
2765 return 0;
2766}
2767
2768
2769static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep)
2770{
2771 u32 data;
2772 struct nbu2ss_ep *ep;
2773 struct nbu2ss_udc *udc;
2774 unsigned long flags;
2775
2776 if (!_ep) {
2777 pr_err("udc: %s, bad param\n", __func__);
2778 return;
2779 }
2780
2781 ep = container_of(_ep, struct nbu2ss_ep, ep);
2782
2783 udc = ep->udc;
2784 if (!udc) {
2785 dev_err(ep->udc->dev, "%s, bad udc\n", __func__);
2786 return;
2787 }
2788
2789 data = gpiod_get_value(vbus_gpio);
2790 if (data == 0)
2791 return;
2792
2793 spin_lock_irqsave(&udc->lock, flags);
2794 _nbu2ss_fifo_flush(udc, ep);
2795 spin_unlock_irqrestore(&udc->lock, flags);
2796}
2797
2798
2799static const struct usb_ep_ops nbu2ss_ep_ops = {
2800 .enable = nbu2ss_ep_enable,
2801 .disable = nbu2ss_ep_disable,
2802
2803 .alloc_request = nbu2ss_ep_alloc_request,
2804 .free_request = nbu2ss_ep_free_request,
2805
2806 .queue = nbu2ss_ep_queue,
2807 .dequeue = nbu2ss_ep_dequeue,
2808
2809 .set_halt = nbu2ss_ep_set_halt,
2810 .set_wedge = nbu2ss_ep_set_wedge,
2811
2812 .fifo_status = nbu2ss_ep_fifo_status,
2813 .fifo_flush = nbu2ss_ep_fifo_flush,
2814};
2815
2816
2817
2818
2819
2820static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget)
2821{
2822 u32 data;
2823 struct nbu2ss_udc *udc;
2824
2825 if (!pgadget) {
2826 pr_err("udc: %s, bad param\n", __func__);
2827 return -EINVAL;
2828 }
2829
2830 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2831 data = gpiod_get_value(vbus_gpio);
2832 if (data == 0)
2833 return -EINVAL;
2834
2835 return _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME;
2836}
2837
2838
2839static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget)
2840{
2841 int i;
2842 u32 data;
2843
2844 struct nbu2ss_udc *udc;
2845
2846 if (!pgadget) {
2847 pr_err("%s, bad param\n", __func__);
2848 return -EINVAL;
2849 }
2850
2851 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2852
2853 data = gpiod_get_value(vbus_gpio);
2854 if (data == 0) {
2855 dev_warn(&pgadget->dev, "VBUS LEVEL = %d\n", data);
2856 return -EINVAL;
2857 }
2858
2859 _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME);
2860
2861 for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) {
2862 data = _nbu2ss_readl(&udc->p_regs->EPCTR);
2863
2864 if (data & PLL_LOCK)
2865 break;
2866 }
2867
2868 _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME);
2869
2870 return 0;
2871}
2872
2873
2874static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget,
2875 int is_selfpowered)
2876{
2877 struct nbu2ss_udc *udc;
2878 unsigned long flags;
2879
2880 if (!pgadget) {
2881 pr_err("%s, bad param\n", __func__);
2882 return -EINVAL;
2883 }
2884
2885 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2886
2887 spin_lock_irqsave(&udc->lock, flags);
2888 pgadget->is_selfpowered = (is_selfpowered != 0);
2889 spin_unlock_irqrestore(&udc->lock, flags);
2890
2891 return 0;
2892}
2893
2894
2895static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active)
2896{
2897 return 0;
2898}
2899
2900
2901static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA)
2902{
2903 struct nbu2ss_udc *udc;
2904 unsigned long flags;
2905
2906 if (!pgadget) {
2907 pr_err("%s, bad param\n", __func__);
2908 return -EINVAL;
2909 }
2910
2911 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2912
2913 spin_lock_irqsave(&udc->lock, flags);
2914 udc->mA = mA;
2915 spin_unlock_irqrestore(&udc->lock, flags);
2916
2917 return 0;
2918}
2919
2920
2921static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on)
2922{
2923 struct nbu2ss_udc *udc;
2924 unsigned long flags;
2925
2926 if (!pgadget) {
2927 pr_err("%s, bad param\n", __func__);
2928 return -EINVAL;
2929 }
2930
2931 udc = container_of(pgadget, struct nbu2ss_udc, gadget);
2932
2933 if (!udc->driver) {
2934 pr_warn("%s, Not Regist Driver\n", __func__);
2935 return -EINVAL;
2936 }
2937
2938 if (udc->vbus_active == 0)
2939 return -ESHUTDOWN;
2940
2941 spin_lock_irqsave(&udc->lock, flags);
2942 _nbu2ss_pullup(udc, is_on);
2943 spin_unlock_irqrestore(&udc->lock, flags);
2944
2945 return 0;
2946}
2947
2948
2949static int nbu2ss_gad_ioctl(struct usb_gadget *pgadget,
2950 unsigned int code, unsigned long param)
2951{
2952 return 0;
2953}
2954
2955static const struct usb_gadget_ops nbu2ss_gadget_ops = {
2956 .get_frame = nbu2ss_gad_get_frame,
2957 .wakeup = nbu2ss_gad_wakeup,
2958 .set_selfpowered = nbu2ss_gad_set_selfpowered,
2959 .vbus_session = nbu2ss_gad_vbus_session,
2960 .vbus_draw = nbu2ss_gad_vbus_draw,
2961 .pullup = nbu2ss_gad_pullup,
2962 .ioctl = nbu2ss_gad_ioctl,
2963};
2964
2965static const struct {
2966 const char *name;
2967 const struct usb_ep_caps caps;
2968} ep_info[NUM_ENDPOINTS] = {
2969#define EP_INFO(_name, _caps) \
2970 { \
2971 .name = _name, \
2972 .caps = _caps, \
2973 }
2974
2975 EP_INFO("ep0",
2976 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
2977 EP_INFO("ep1-bulk",
2978 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2979 EP_INFO("ep2-bulk",
2980 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2981 EP_INFO("ep3in-int",
2982 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2983 EP_INFO("ep4-iso",
2984 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2985 EP_INFO("ep5-iso",
2986 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2987 EP_INFO("ep6-bulk",
2988 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2989 EP_INFO("ep7-bulk",
2990 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2991 EP_INFO("ep8in-int",
2992 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
2993 EP_INFO("ep9-iso",
2994 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2995 EP_INFO("epa-iso",
2996 USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, USB_EP_CAPS_DIR_ALL)),
2997 EP_INFO("epb-bulk",
2998 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
2999 EP_INFO("epc-bulk",
3000 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_ALL)),
3001 EP_INFO("epdin-int",
3002 USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, USB_EP_CAPS_DIR_IN)),
3003
3004#undef EP_INFO
3005};
3006
3007
3008static void nbu2ss_drv_ep_init(struct nbu2ss_udc *udc)
3009{
3010 int i;
3011
3012 INIT_LIST_HEAD(&udc->gadget.ep_list);
3013 udc->gadget.ep0 = &udc->ep[0].ep;
3014
3015 for (i = 0; i < NUM_ENDPOINTS; i++) {
3016 struct nbu2ss_ep *ep = &udc->ep[i];
3017
3018 ep->udc = udc;
3019 ep->desc = NULL;
3020
3021 ep->ep.driver_data = NULL;
3022 ep->ep.name = ep_info[i].name;
3023 ep->ep.caps = ep_info[i].caps;
3024 ep->ep.ops = &nbu2ss_ep_ops;
3025
3026 usb_ep_set_maxpacket_limit(&ep->ep,
3027 i == 0 ? EP0_PACKETSIZE
3028 : EP_PACKETSIZE);
3029
3030 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
3031 INIT_LIST_HEAD(&ep->queue);
3032 }
3033
3034 list_del_init(&udc->ep[0].ep.ep_list);
3035}
3036
3037
3038
3039static int nbu2ss_drv_contest_init(struct platform_device *pdev,
3040 struct nbu2ss_udc *udc)
3041{
3042 spin_lock_init(&udc->lock);
3043 udc->dev = &pdev->dev;
3044
3045 udc->gadget.is_selfpowered = 1;
3046 udc->devstate = USB_STATE_NOTATTACHED;
3047 udc->pdev = pdev;
3048 udc->mA = 0;
3049
3050 udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
3051
3052
3053 nbu2ss_drv_ep_init(udc);
3054
3055
3056 udc->gadget.ops = &nbu2ss_gadget_ops;
3057 udc->gadget.ep0 = &udc->ep[0].ep;
3058 udc->gadget.speed = USB_SPEED_UNKNOWN;
3059 udc->gadget.name = driver_name;
3060
3061
3062 device_initialize(&udc->gadget.dev);
3063
3064 dev_set_name(&udc->gadget.dev, "gadget");
3065 udc->gadget.dev.parent = &pdev->dev;
3066 udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
3067
3068 return 0;
3069}
3070
3071
3072
3073
3074static int nbu2ss_drv_probe(struct platform_device *pdev)
3075{
3076 int status = -ENODEV;
3077 struct nbu2ss_udc *udc;
3078 int irq;
3079 void __iomem *mmio_base;
3080
3081 udc = &udc_controller;
3082 memset(udc, 0, sizeof(struct nbu2ss_udc));
3083
3084 platform_set_drvdata(pdev, udc);
3085
3086
3087 mmio_base = devm_platform_ioremap_resource(pdev, 0);
3088 if (IS_ERR(mmio_base))
3089 return PTR_ERR(mmio_base);
3090
3091 irq = platform_get_irq(pdev, 0);
3092 if (irq < 0)
3093 return irq;
3094 status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq,
3095 0, driver_name, udc);
3096
3097
3098 udc->p_regs = (struct fc_regs __iomem *)mmio_base;
3099
3100
3101 if (status != 0) {
3102 dev_err(udc->dev, "request_irq(USB_UDC_IRQ_1) failed\n");
3103 return status;
3104 }
3105
3106
3107 status = nbu2ss_drv_contest_init(pdev, udc);
3108 if (status < 0) {
3109
3110 return status;
3111 }
3112
3113
3114 vbus_irq = gpiod_to_irq(vbus_gpio);
3115 irq_set_irq_type(vbus_irq, IRQ_TYPE_EDGE_BOTH);
3116 status = request_irq(vbus_irq,
3117 _nbu2ss_vbus_irq, IRQF_SHARED, driver_name, udc);
3118
3119 if (status != 0) {
3120 dev_err(udc->dev, "request_irq(vbus_irq) failed\n");
3121 return status;
3122 }
3123
3124 return status;
3125}
3126
3127
3128static void nbu2ss_drv_shutdown(struct platform_device *pdev)
3129{
3130 struct nbu2ss_udc *udc;
3131
3132 udc = platform_get_drvdata(pdev);
3133 if (!udc)
3134 return;
3135
3136 _nbu2ss_disable_controller(udc);
3137}
3138
3139
3140static int nbu2ss_drv_remove(struct platform_device *pdev)
3141{
3142 struct nbu2ss_udc *udc;
3143 struct nbu2ss_ep *ep;
3144 int i;
3145
3146 udc = &udc_controller;
3147
3148 for (i = 0; i < NUM_ENDPOINTS; i++) {
3149 ep = &udc->ep[i];
3150 if (ep->virt_buf)
3151 dma_free_coherent(NULL, PAGE_SIZE, (void *)ep->virt_buf,
3152 ep->phys_buf);
3153 }
3154
3155
3156 free_irq(vbus_irq, udc);
3157
3158 return 0;
3159}
3160
3161
3162static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state)
3163{
3164 struct nbu2ss_udc *udc;
3165
3166 udc = platform_get_drvdata(pdev);
3167 if (!udc)
3168 return 0;
3169
3170 if (udc->vbus_active) {
3171 udc->vbus_active = 0;
3172 udc->devstate = USB_STATE_NOTATTACHED;
3173 udc->linux_suspended = 1;
3174
3175 if (udc->usb_suspended) {
3176 udc->usb_suspended = 0;
3177 _nbu2ss_reset_controller(udc);
3178 }
3179
3180 _nbu2ss_quiesce(udc);
3181 }
3182 _nbu2ss_disable_controller(udc);
3183
3184 return 0;
3185}
3186
3187
3188static int nbu2ss_drv_resume(struct platform_device *pdev)
3189{
3190 u32 data;
3191 struct nbu2ss_udc *udc;
3192
3193 udc = platform_get_drvdata(pdev);
3194 if (!udc)
3195 return 0;
3196
3197 data = gpiod_get_value(vbus_gpio);
3198 if (data) {
3199 udc->vbus_active = 1;
3200 udc->devstate = USB_STATE_POWERED;
3201 _nbu2ss_enable_controller(udc);
3202 _nbu2ss_pullup(udc, 1);
3203 }
3204
3205 udc->linux_suspended = 0;
3206
3207 return 0;
3208}
3209
3210static struct platform_driver udc_driver = {
3211 .probe = nbu2ss_drv_probe,
3212 .shutdown = nbu2ss_drv_shutdown,
3213 .remove = nbu2ss_drv_remove,
3214 .suspend = nbu2ss_drv_suspend,
3215 .resume = nbu2ss_drv_resume,
3216 .driver = {
3217 .name = driver_name,
3218 },
3219};
3220
3221module_platform_driver(udc_driver);
3222
3223MODULE_DESCRIPTION(DRIVER_DESC);
3224MODULE_AUTHOR("Renesas Electronics Corporation");
3225MODULE_LICENSE("GPL");
3226
