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12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/serial_8250.h>
17#include <linux/serial_reg.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21#include <linux/platform_device.h>
22#include <linux/workqueue.h>
23#include <linux/notifier.h>
24#include <linux/slab.h>
25#include <linux/acpi.h>
26#include <linux/clk.h>
27#include <linux/reset.h>
28#include <linux/pm_runtime.h>
29
30#include <asm/byteorder.h>
31
32#include "8250_dwlib.h"
33
34
35#define DW_UART_USR 0x1f
36
37
38#define DW_UART_MCR_SIRE BIT(6)
39
40struct dw8250_data {
41 struct dw8250_port_data data;
42
43 u8 usr_reg;
44 int msr_mask_on;
45 int msr_mask_off;
46 struct clk *clk;
47 struct clk *pclk;
48 struct notifier_block clk_notifier;
49 struct work_struct clk_work;
50 struct reset_control *rst;
51
52 unsigned int skip_autocfg:1;
53 unsigned int uart_16550_compatible:1;
54};
55
56static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
57{
58 return container_of(data, struct dw8250_data, data);
59}
60
61static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
62{
63 return container_of(nb, struct dw8250_data, clk_notifier);
64}
65
66static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
67{
68 return container_of(work, struct dw8250_data, clk_work);
69}
70
71static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
72{
73 struct dw8250_data *d = to_dw8250_data(p->private_data);
74
75
76 if (offset == UART_MSR) {
77 value |= d->msr_mask_on;
78 value &= ~d->msr_mask_off;
79 }
80
81 return value;
82}
83
84static void dw8250_force_idle(struct uart_port *p)
85{
86 struct uart_8250_port *up = up_to_u8250p(p);
87
88 serial8250_clear_and_reinit_fifos(up);
89 (void)p->serial_in(p, UART_RX);
90}
91
92static void dw8250_check_lcr(struct uart_port *p, int value)
93{
94 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
95 int tries = 1000;
96
97
98 while (tries--) {
99 unsigned int lcr = p->serial_in(p, UART_LCR);
100
101 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
102 return;
103
104 dw8250_force_idle(p);
105
106#ifdef CONFIG_64BIT
107 if (p->type == PORT_OCTEON)
108 __raw_writeq(value & 0xff, offset);
109 else
110#endif
111 if (p->iotype == UPIO_MEM32)
112 writel(value, offset);
113 else if (p->iotype == UPIO_MEM32BE)
114 iowrite32be(value, offset);
115 else
116 writeb(value, offset);
117 }
118
119
120
121
122}
123
124
125static void dw8250_tx_wait_empty(struct uart_port *p)
126{
127 unsigned int tries = 20000;
128 unsigned int delay_threshold = tries - 1000;
129 unsigned int lsr;
130
131 while (tries--) {
132 lsr = readb (p->membase + (UART_LSR << p->regshift));
133 if (lsr & UART_LSR_TEMT)
134 break;
135
136
137
138
139
140 if (tries < delay_threshold)
141 udelay (1);
142 }
143}
144
145static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
146{
147 struct dw8250_data *d = to_dw8250_data(p->private_data);
148
149
150 if (offset == UART_LCR)
151 dw8250_tx_wait_empty(p);
152
153 writeb(value, p->membase + (offset << p->regshift));
154
155 if (offset == UART_LCR && !d->uart_16550_compatible)
156 dw8250_check_lcr(p, value);
157}
158
159
160static void dw8250_serial_out(struct uart_port *p, int offset, int value)
161{
162 struct dw8250_data *d = to_dw8250_data(p->private_data);
163
164 writeb(value, p->membase + (offset << p->regshift));
165
166 if (offset == UART_LCR && !d->uart_16550_compatible)
167 dw8250_check_lcr(p, value);
168}
169
170static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
171{
172 unsigned int value = readb(p->membase + (offset << p->regshift));
173
174 return dw8250_modify_msr(p, offset, value);
175}
176
177#ifdef CONFIG_64BIT
178static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
179{
180 unsigned int value;
181
182 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
183
184 return dw8250_modify_msr(p, offset, value);
185}
186
187static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
188{
189 struct dw8250_data *d = to_dw8250_data(p->private_data);
190
191 value &= 0xff;
192 __raw_writeq(value, p->membase + (offset << p->regshift));
193
194 __raw_readq(p->membase + (UART_LCR << p->regshift));
195
196 if (offset == UART_LCR && !d->uart_16550_compatible)
197 dw8250_check_lcr(p, value);
198}
199#endif
200
201static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
202{
203 struct dw8250_data *d = to_dw8250_data(p->private_data);
204
205 writel(value, p->membase + (offset << p->regshift));
206
207 if (offset == UART_LCR && !d->uart_16550_compatible)
208 dw8250_check_lcr(p, value);
209}
210
211static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
212{
213 unsigned int value = readl(p->membase + (offset << p->regshift));
214
215 return dw8250_modify_msr(p, offset, value);
216}
217
218static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
219{
220 struct dw8250_data *d = to_dw8250_data(p->private_data);
221
222 iowrite32be(value, p->membase + (offset << p->regshift));
223
224 if (offset == UART_LCR && !d->uart_16550_compatible)
225 dw8250_check_lcr(p, value);
226}
227
228static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
229{
230 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
231
232 return dw8250_modify_msr(p, offset, value);
233}
234
235
236static int dw8250_handle_irq(struct uart_port *p)
237{
238 struct uart_8250_port *up = up_to_u8250p(p);
239 struct dw8250_data *d = to_dw8250_data(p->private_data);
240 unsigned int iir = p->serial_in(p, UART_IIR);
241 unsigned int status;
242 unsigned long flags;
243
244
245
246
247
248
249
250
251
252
253
254 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
255 spin_lock_irqsave(&p->lock, flags);
256 status = p->serial_in(p, UART_LSR);
257
258 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
259 (void) p->serial_in(p, UART_RX);
260
261 spin_unlock_irqrestore(&p->lock, flags);
262 }
263
264 if (serial8250_handle_irq(p, iir))
265 return 1;
266
267 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
268
269 (void)p->serial_in(p, d->usr_reg);
270
271 return 1;
272 }
273
274 return 0;
275}
276
277static void dw8250_clk_work_cb(struct work_struct *work)
278{
279 struct dw8250_data *d = work_to_dw8250_data(work);
280 struct uart_8250_port *up;
281 unsigned long rate;
282
283 rate = clk_get_rate(d->clk);
284 if (rate <= 0)
285 return;
286
287 up = serial8250_get_port(d->data.line);
288
289 serial8250_update_uartclk(&up->port, rate);
290}
291
292static int dw8250_clk_notifier_cb(struct notifier_block *nb,
293 unsigned long event, void *data)
294{
295 struct dw8250_data *d = clk_to_dw8250_data(nb);
296
297
298
299
300
301
302
303
304
305
306
307
308
309 if (event == POST_RATE_CHANGE) {
310 queue_work(system_unbound_wq, &d->clk_work);
311 return NOTIFY_OK;
312 }
313
314 return NOTIFY_DONE;
315}
316
317static void
318dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
319{
320 if (!state)
321 pm_runtime_get_sync(port->dev);
322
323 serial8250_do_pm(port, state, old);
324
325 if (state)
326 pm_runtime_put_sync_suspend(port->dev);
327}
328
329static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
330 struct ktermios *old)
331{
332 unsigned long newrate = tty_termios_baud_rate(termios) * 16;
333 struct dw8250_data *d = to_dw8250_data(p->private_data);
334 long rate;
335 int ret;
336
337 clk_disable_unprepare(d->clk);
338 rate = clk_round_rate(d->clk, newrate);
339 if (rate > 0) {
340
341
342
343
344
345
346 swap(p->uartclk, rate);
347 ret = clk_set_rate(d->clk, newrate);
348 if (ret)
349 swap(p->uartclk, rate);
350 }
351 clk_prepare_enable(d->clk);
352
353 p->status &= ~UPSTAT_AUTOCTS;
354 if (termios->c_cflag & CRTSCTS)
355 p->status |= UPSTAT_AUTOCTS;
356
357 serial8250_do_set_termios(p, termios, old);
358}
359
360static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
361{
362 struct uart_8250_port *up = up_to_u8250p(p);
363 unsigned int mcr = p->serial_in(p, UART_MCR);
364
365 if (up->capabilities & UART_CAP_IRDA) {
366 if (termios->c_line == N_IRDA)
367 mcr |= DW_UART_MCR_SIRE;
368 else
369 mcr &= ~DW_UART_MCR_SIRE;
370
371 p->serial_out(p, UART_MCR, mcr);
372 }
373 serial8250_do_set_ldisc(p, termios);
374}
375
376static int dw8250_startup(struct uart_port *p)
377{
378 struct dw8250_data *d = to_dw8250_data(p->private_data);
379 int ret;
380
381
382
383
384
385
386
387 if (d->clk) {
388 ret = clk_notifier_register(d->clk, &d->clk_notifier);
389 if (ret)
390 dev_warn(p->dev, "Failed to set the clock notifier\n");
391 }
392
393 return serial8250_do_startup(p);
394}
395
396static void dw8250_shutdown(struct uart_port *p)
397{
398 struct dw8250_data *d = to_dw8250_data(p->private_data);
399
400 serial8250_do_shutdown(p);
401
402 if (d->clk) {
403 clk_notifier_unregister(d->clk, &d->clk_notifier);
404
405 flush_work(&d->clk_work);
406 }
407}
408
409
410
411
412
413
414
415
416
417static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
418{
419 return false;
420}
421
422static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
423{
424 return param == chan->device->dev;
425}
426
427static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
428{
429 if (p->dev->of_node) {
430 struct device_node *np = p->dev->of_node;
431 int id;
432
433
434 id = of_alias_get_id(np, "serial");
435 if (id >= 0)
436 p->line = id;
437#ifdef CONFIG_64BIT
438 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
439 p->serial_in = dw8250_serial_inq;
440 p->serial_out = dw8250_serial_outq;
441 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
442 p->type = PORT_OCTEON;
443 data->usr_reg = 0x27;
444 data->skip_autocfg = true;
445 }
446#endif
447 if (of_device_is_big_endian(p->dev->of_node)) {
448 p->iotype = UPIO_MEM32BE;
449 p->serial_in = dw8250_serial_in32be;
450 p->serial_out = dw8250_serial_out32be;
451 }
452 if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
453 p->serial_out = dw8250_serial_out38x;
454
455 } else if (acpi_dev_present("APMC0D08", NULL, -1)) {
456 p->iotype = UPIO_MEM32;
457 p->regshift = 2;
458 p->serial_in = dw8250_serial_in32;
459 data->uart_16550_compatible = true;
460 }
461
462
463 if (platform_get_resource_byname(to_platform_device(p->dev),
464 IORESOURCE_MEM, "lpss_priv")) {
465 data->data.dma.rx_param = p->dev->parent;
466 data->data.dma.tx_param = p->dev->parent;
467 data->data.dma.fn = dw8250_idma_filter;
468 }
469}
470
471static int dw8250_probe(struct platform_device *pdev)
472{
473 struct uart_8250_port uart = {}, *up = &uart;
474 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 struct uart_port *p = &up->port;
476 struct device *dev = &pdev->dev;
477 struct dw8250_data *data;
478 int irq;
479 int err;
480 u32 val;
481
482 if (!regs) {
483 dev_err(dev, "no registers defined\n");
484 return -EINVAL;
485 }
486
487 irq = platform_get_irq(pdev, 0);
488 if (irq < 0)
489 return irq;
490
491 spin_lock_init(&p->lock);
492 p->mapbase = regs->start;
493 p->irq = irq;
494 p->handle_irq = dw8250_handle_irq;
495 p->pm = dw8250_do_pm;
496 p->type = PORT_8250;
497 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
498 p->dev = dev;
499 p->iotype = UPIO_MEM;
500 p->serial_in = dw8250_serial_in;
501 p->serial_out = dw8250_serial_out;
502 p->set_ldisc = dw8250_set_ldisc;
503 p->set_termios = dw8250_set_termios;
504 p->startup = dw8250_startup;
505 p->shutdown = dw8250_shutdown;
506
507 p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
508 if (!p->membase)
509 return -ENOMEM;
510
511 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
512 if (!data)
513 return -ENOMEM;
514
515 data->data.dma.fn = dw8250_fallback_dma_filter;
516 data->usr_reg = DW_UART_USR;
517 p->private_data = &data->data;
518
519 data->uart_16550_compatible = device_property_read_bool(dev,
520 "snps,uart-16550-compatible");
521
522 err = device_property_read_u32(dev, "reg-shift", &val);
523 if (!err)
524 p->regshift = val;
525
526 err = device_property_read_u32(dev, "reg-io-width", &val);
527 if (!err && val == 4) {
528 p->iotype = UPIO_MEM32;
529 p->serial_in = dw8250_serial_in32;
530 p->serial_out = dw8250_serial_out32;
531 }
532
533 if (device_property_read_bool(dev, "dcd-override")) {
534
535 data->msr_mask_on |= UART_MSR_DCD;
536 data->msr_mask_off |= UART_MSR_DDCD;
537 }
538
539 if (device_property_read_bool(dev, "dsr-override")) {
540
541 data->msr_mask_on |= UART_MSR_DSR;
542 data->msr_mask_off |= UART_MSR_DDSR;
543 }
544
545 if (device_property_read_bool(dev, "cts-override")) {
546
547 data->msr_mask_on |= UART_MSR_CTS;
548 data->msr_mask_off |= UART_MSR_DCTS;
549 }
550
551 if (device_property_read_bool(dev, "ri-override")) {
552
553 data->msr_mask_off |= UART_MSR_RI;
554 data->msr_mask_off |= UART_MSR_TERI;
555 }
556
557
558 device_property_read_u32(dev, "clock-frequency", &p->uartclk);
559
560
561 data->clk = devm_clk_get_optional(dev, "baudclk");
562 if (data->clk == NULL)
563 data->clk = devm_clk_get_optional(dev, NULL);
564 if (IS_ERR(data->clk))
565 return PTR_ERR(data->clk);
566
567 INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
568 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
569
570 err = clk_prepare_enable(data->clk);
571 if (err)
572 dev_warn(dev, "could not enable optional baudclk: %d\n", err);
573
574 if (data->clk)
575 p->uartclk = clk_get_rate(data->clk);
576
577
578 if (!p->uartclk) {
579 dev_err(dev, "clock rate not defined\n");
580 err = -EINVAL;
581 goto err_clk;
582 }
583
584 data->pclk = devm_clk_get_optional(dev, "apb_pclk");
585 if (IS_ERR(data->pclk)) {
586 err = PTR_ERR(data->pclk);
587 goto err_clk;
588 }
589
590 err = clk_prepare_enable(data->pclk);
591 if (err) {
592 dev_err(dev, "could not enable apb_pclk\n");
593 goto err_clk;
594 }
595
596 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
597 if (IS_ERR(data->rst)) {
598 err = PTR_ERR(data->rst);
599 goto err_pclk;
600 }
601 reset_control_deassert(data->rst);
602
603 dw8250_quirks(p, data);
604
605
606 if (data->uart_16550_compatible)
607 p->handle_irq = NULL;
608
609 if (!data->skip_autocfg)
610 dw8250_setup_port(p);
611
612
613 if (p->fifosize) {
614 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
615 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
616 up->dma = &data->data.dma;
617 }
618
619 data->data.line = serial8250_register_8250_port(up);
620 if (data->data.line < 0) {
621 err = data->data.line;
622 goto err_reset;
623 }
624
625 platform_set_drvdata(pdev, data);
626
627 pm_runtime_set_active(dev);
628 pm_runtime_enable(dev);
629
630 return 0;
631
632err_reset:
633 reset_control_assert(data->rst);
634
635err_pclk:
636 clk_disable_unprepare(data->pclk);
637
638err_clk:
639 clk_disable_unprepare(data->clk);
640
641 return err;
642}
643
644static int dw8250_remove(struct platform_device *pdev)
645{
646 struct dw8250_data *data = platform_get_drvdata(pdev);
647 struct device *dev = &pdev->dev;
648
649 pm_runtime_get_sync(dev);
650
651 serial8250_unregister_port(data->data.line);
652
653 reset_control_assert(data->rst);
654
655 clk_disable_unprepare(data->pclk);
656
657 clk_disable_unprepare(data->clk);
658
659 pm_runtime_disable(dev);
660 pm_runtime_put_noidle(dev);
661
662 return 0;
663}
664
665#ifdef CONFIG_PM_SLEEP
666static int dw8250_suspend(struct device *dev)
667{
668 struct dw8250_data *data = dev_get_drvdata(dev);
669
670 serial8250_suspend_port(data->data.line);
671
672 return 0;
673}
674
675static int dw8250_resume(struct device *dev)
676{
677 struct dw8250_data *data = dev_get_drvdata(dev);
678
679 serial8250_resume_port(data->data.line);
680
681 return 0;
682}
683#endif
684
685#ifdef CONFIG_PM
686static int dw8250_runtime_suspend(struct device *dev)
687{
688 struct dw8250_data *data = dev_get_drvdata(dev);
689
690 clk_disable_unprepare(data->clk);
691
692 clk_disable_unprepare(data->pclk);
693
694 return 0;
695}
696
697static int dw8250_runtime_resume(struct device *dev)
698{
699 struct dw8250_data *data = dev_get_drvdata(dev);
700
701 clk_prepare_enable(data->pclk);
702
703 clk_prepare_enable(data->clk);
704
705 return 0;
706}
707#endif
708
709static const struct dev_pm_ops dw8250_pm_ops = {
710 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
711 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
712};
713
714static const struct of_device_id dw8250_of_match[] = {
715 { .compatible = "snps,dw-apb-uart" },
716 { .compatible = "cavium,octeon-3860-uart" },
717 { .compatible = "marvell,armada-38x-uart" },
718 { .compatible = "renesas,rzn1-uart" },
719 { }
720};
721MODULE_DEVICE_TABLE(of, dw8250_of_match);
722
723static const struct acpi_device_id dw8250_acpi_match[] = {
724 { "INT33C4", 0 },
725 { "INT33C5", 0 },
726 { "INT3434", 0 },
727 { "INT3435", 0 },
728 { "80860F0A", 0 },
729 { "8086228A", 0 },
730 { "APMC0D08", 0},
731 { "AMD0020", 0 },
732 { "AMDI0020", 0 },
733 { "BRCM2032", 0 },
734 { "HISI0031", 0 },
735 { },
736};
737MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
738
739static struct platform_driver dw8250_platform_driver = {
740 .driver = {
741 .name = "dw-apb-uart",
742 .pm = &dw8250_pm_ops,
743 .of_match_table = dw8250_of_match,
744 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
745 },
746 .probe = dw8250_probe,
747 .remove = dw8250_remove,
748};
749
750module_platform_driver(dw8250_platform_driver);
751
752MODULE_AUTHOR("Jamie Iles");
753MODULE_LICENSE("GPL");
754MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
755MODULE_ALIAS("platform:dw-apb-uart");
756