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15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/tty_flip.h>
21#include <linux/console.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26#include <asm/parisc-device.h>
27
28#include <linux/sysrq.h>
29#include <linux/serial_core.h>
30
31#define MUX_OFFSET 0x800
32#define MUX_LINE_OFFSET 0x80
33
34#define MUX_FIFO_SIZE 255
35#define MUX_POLL_DELAY (30 * HZ / 1000)
36
37#define IO_DATA_REG_OFFSET 0x3c
38#define IO_DCOUNT_REG_OFFSET 0x40
39
40#define MUX_EOFIFO(status) ((status & 0xF000) == 0xF000)
41#define MUX_STATUS(status) ((status & 0xF000) == 0x8000)
42#define MUX_BREAK(status) ((status & 0xF000) == 0x2000)
43
44#define MUX_NR 256
45static unsigned int port_cnt __read_mostly;
46struct mux_port {
47 struct uart_port port;
48 int enabled;
49};
50static struct mux_port mux_ports[MUX_NR];
51
52static struct uart_driver mux_driver = {
53 .owner = THIS_MODULE,
54 .driver_name = "ttyB",
55 .dev_name = "ttyB",
56 .major = MUX_MAJOR,
57 .minor = 0,
58 .nr = MUX_NR,
59};
60
61static struct timer_list mux_timer;
62
63#define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
64#define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
65
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75
76static int __init get_mux_port_count(struct parisc_device *dev)
77{
78 int status;
79 u8 iodc_data[32];
80 unsigned long bytecnt;
81
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83
84
85
86 if(dev->id.hversion == 0x15)
87 return 1;
88
89 status = pdc_iodc_read(&bytecnt, dev->hpa.start, 0, iodc_data, 32);
90 BUG_ON(status != PDC_OK);
91
92
93 return ((((iodc_data)[4] & 0xf0) >> 4) * 8) + 8;
94}
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103
104static unsigned int mux_tx_empty(struct uart_port *port)
105{
106 return UART_GET_FIFO_CNT(port) ? 0 : TIOCSER_TEMT;
107}
108
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116
117static void mux_set_mctrl(struct uart_port *port, unsigned int mctrl)
118{
119}
120
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127
128static unsigned int mux_get_mctrl(struct uart_port *port)
129{
130 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
131}
132
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137
138
139static void mux_stop_tx(struct uart_port *port)
140{
141}
142
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147
148
149static void mux_start_tx(struct uart_port *port)
150{
151}
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158
159static void mux_stop_rx(struct uart_port *port)
160{
161}
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169
170static void mux_break_ctl(struct uart_port *port, int break_state)
171{
172}
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179
180
181static void mux_write(struct uart_port *port)
182{
183 int count;
184 struct circ_buf *xmit = &port->state->xmit;
185
186 if(port->x_char) {
187 UART_PUT_CHAR(port, port->x_char);
188 port->icount.tx++;
189 port->x_char = 0;
190 return;
191 }
192
193 if(uart_circ_empty(xmit) || uart_tx_stopped(port)) {
194 mux_stop_tx(port);
195 return;
196 }
197
198 count = (port->fifosize) - UART_GET_FIFO_CNT(port);
199 do {
200 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
201 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
202 port->icount.tx++;
203 if(uart_circ_empty(xmit))
204 break;
205
206 } while(--count > 0);
207
208 while(UART_GET_FIFO_CNT(port))
209 udelay(1);
210
211 if(uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(port);
213
214 if (uart_circ_empty(xmit))
215 mux_stop_tx(port);
216}
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224
225static void mux_read(struct uart_port *port)
226{
227 struct tty_port *tport = &port->state->port;
228 int data;
229 __u32 start_count = port->icount.rx;
230
231 while(1) {
232 data = __raw_readl(port->membase + IO_DATA_REG_OFFSET);
233
234 if (MUX_STATUS(data))
235 continue;
236
237 if (MUX_EOFIFO(data))
238 break;
239
240 port->icount.rx++;
241
242 if (MUX_BREAK(data)) {
243 port->icount.brk++;
244 if(uart_handle_break(port))
245 continue;
246 }
247
248 if (uart_handle_sysrq_char(port, data & 0xffu))
249 continue;
250
251 tty_insert_flip_char(tport, data & 0xFF, TTY_NORMAL);
252 }
253
254 if (start_count != port->icount.rx)
255 tty_flip_buffer_push(tport);
256}
257
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264
265static int mux_startup(struct uart_port *port)
266{
267 mux_ports[port->line].enabled = 1;
268 return 0;
269}
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276
277static void mux_shutdown(struct uart_port *port)
278{
279 mux_ports[port->line].enabled = 0;
280}
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289
290static void
291mux_set_termios(struct uart_port *port, struct ktermios *termios,
292 struct ktermios *old)
293{
294}
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302
303static const char *mux_type(struct uart_port *port)
304{
305 return "Mux";
306}
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315static void mux_release_port(struct uart_port *port)
316{
317}
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327static int mux_request_port(struct uart_port *port)
328{
329 return 0;
330}
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342
343static void mux_config_port(struct uart_port *port, int type)
344{
345 port->type = PORT_MUX;
346}
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355
356static int mux_verify_port(struct uart_port *port, struct serial_struct *ser)
357{
358 if(port->membase == NULL)
359 return -EINVAL;
360
361 return 0;
362}
363
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368
369
370static void mux_poll(struct timer_list *unused)
371{
372 int i;
373
374 for(i = 0; i < port_cnt; ++i) {
375 if(!mux_ports[i].enabled)
376 continue;
377
378 mux_read(&mux_ports[i].port);
379 mux_write(&mux_ports[i].port);
380 }
381
382 mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
383}
384
385
386#ifdef CONFIG_SERIAL_MUX_CONSOLE
387static void mux_console_write(struct console *co, const char *s, unsigned count)
388{
389
390 while(UART_GET_FIFO_CNT(&mux_ports[0].port))
391 udelay(1);
392
393 while(count--) {
394 if(*s == '\n') {
395 UART_PUT_CHAR(&mux_ports[0].port, '\r');
396 }
397 UART_PUT_CHAR(&mux_ports[0].port, *s++);
398 }
399
400}
401
402static int mux_console_setup(struct console *co, char *options)
403{
404 return 0;
405}
406
407static struct console mux_console = {
408 .name = "ttyB",
409 .write = mux_console_write,
410 .device = uart_console_device,
411 .setup = mux_console_setup,
412 .flags = CON_ENABLED | CON_PRINTBUFFER,
413 .index = 0,
414 .data = &mux_driver,
415};
416
417#define MUX_CONSOLE &mux_console
418#else
419#define MUX_CONSOLE NULL
420#endif
421
422static const struct uart_ops mux_pops = {
423 .tx_empty = mux_tx_empty,
424 .set_mctrl = mux_set_mctrl,
425 .get_mctrl = mux_get_mctrl,
426 .stop_tx = mux_stop_tx,
427 .start_tx = mux_start_tx,
428 .stop_rx = mux_stop_rx,
429 .break_ctl = mux_break_ctl,
430 .startup = mux_startup,
431 .shutdown = mux_shutdown,
432 .set_termios = mux_set_termios,
433 .type = mux_type,
434 .release_port = mux_release_port,
435 .request_port = mux_request_port,
436 .config_port = mux_config_port,
437 .verify_port = mux_verify_port,
438};
439
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444
445
446
447static int __init mux_probe(struct parisc_device *dev)
448{
449 int i, status;
450
451 int port_count = get_mux_port_count(dev);
452 printk(KERN_INFO "Serial mux driver (%d ports) Revision: 0.6\n", port_count);
453
454 dev_set_drvdata(&dev->dev, (void *)(long)port_count);
455 request_mem_region(dev->hpa.start + MUX_OFFSET,
456 port_count * MUX_LINE_OFFSET, "Mux");
457
458 if(!port_cnt) {
459 mux_driver.cons = MUX_CONSOLE;
460
461 status = uart_register_driver(&mux_driver);
462 if(status) {
463 printk(KERN_ERR "Serial mux: Unable to register driver.\n");
464 return 1;
465 }
466 }
467
468 for(i = 0; i < port_count; ++i, ++port_cnt) {
469 struct uart_port *port = &mux_ports[port_cnt].port;
470 port->iobase = 0;
471 port->mapbase = dev->hpa.start + MUX_OFFSET +
472 (i * MUX_LINE_OFFSET);
473 port->membase = ioremap(port->mapbase, MUX_LINE_OFFSET);
474 port->iotype = UPIO_MEM;
475 port->type = PORT_MUX;
476 port->irq = 0;
477 port->uartclk = 0;
478 port->fifosize = MUX_FIFO_SIZE;
479 port->ops = &mux_pops;
480 port->flags = UPF_BOOT_AUTOCONF;
481 port->line = port_cnt;
482 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MUX_CONSOLE);
483
484
485
486
487
488
489 port->timeout = HZ / 50;
490 spin_lock_init(&port->lock);
491
492 status = uart_add_one_port(&mux_driver, port);
493 BUG_ON(status);
494 }
495
496 return 0;
497}
498
499static int __exit mux_remove(struct parisc_device *dev)
500{
501 int i, j;
502 int port_count = (long)dev_get_drvdata(&dev->dev);
503
504
505 for(i = 0; i < port_cnt; ++i) {
506 if(mux_ports[i].port.mapbase == dev->hpa.start + MUX_OFFSET)
507 break;
508 }
509 BUG_ON(i + port_count > port_cnt);
510
511
512 for(j = 0; j < port_count; ++j, ++i) {
513 struct uart_port *port = &mux_ports[i].port;
514
515 uart_remove_one_port(&mux_driver, port);
516 if(port->membase)
517 iounmap(port->membase);
518 }
519
520 release_mem_region(dev->hpa.start + MUX_OFFSET, port_count * MUX_LINE_OFFSET);
521 return 0;
522}
523
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530
531
532static const struct parisc_device_id builtin_mux_tbl[] __initconst = {
533 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, 0x15, 0x0000D },
534 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, 0x44, 0x0000D },
535 { 0, }
536};
537
538static const struct parisc_device_id mux_tbl[] __initconst = {
539 { HPHW_A_DIRECT, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0000D },
540 { 0, }
541};
542
543MODULE_DEVICE_TABLE(parisc, builtin_mux_tbl);
544MODULE_DEVICE_TABLE(parisc, mux_tbl);
545
546static struct parisc_driver builtin_serial_mux_driver __refdata = {
547 .name = "builtin_serial_mux",
548 .id_table = builtin_mux_tbl,
549 .probe = mux_probe,
550 .remove = __exit_p(mux_remove),
551};
552
553static struct parisc_driver serial_mux_driver __refdata = {
554 .name = "serial_mux",
555 .id_table = mux_tbl,
556 .probe = mux_probe,
557 .remove = __exit_p(mux_remove),
558};
559
560
561
562
563
564
565static int __init mux_init(void)
566{
567 register_parisc_driver(&builtin_serial_mux_driver);
568 register_parisc_driver(&serial_mux_driver);
569
570 if(port_cnt > 0) {
571
572 timer_setup(&mux_timer, mux_poll, 0);
573 mod_timer(&mux_timer, jiffies + MUX_POLL_DELAY);
574
575#ifdef CONFIG_SERIAL_MUX_CONSOLE
576 register_console(&mux_console);
577#endif
578 }
579
580 return 0;
581}
582
583
584
585
586
587
588static void __exit mux_exit(void)
589{
590
591 if(port_cnt > 0) {
592 del_timer_sync(&mux_timer);
593#ifdef CONFIG_SERIAL_MUX_CONSOLE
594 unregister_console(&mux_console);
595#endif
596 }
597
598 unregister_parisc_driver(&builtin_serial_mux_driver);
599 unregister_parisc_driver(&serial_mux_driver);
600 uart_unregister_driver(&mux_driver);
601}
602
603module_init(mux_init);
604module_exit(mux_exit);
605
606MODULE_AUTHOR("Ryan Bradetich");
607MODULE_DESCRIPTION("Serial MUX driver");
608MODULE_LICENSE("GPL");
609MODULE_ALIAS_CHARDEV_MAJOR(MUX_MAJOR);
610