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12#ifndef __LINUX_CDNS3_GADGET
13#define __LINUX_CDNS3_GADGET
14#include <linux/usb/gadget.h>
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70struct cdns3_usb_regs {
71 __le32 usb_conf;
72 __le32 usb_sts;
73 __le32 usb_cmd;
74 __le32 usb_itpn;
75 __le32 usb_lpm;
76 __le32 usb_ien;
77 __le32 usb_ists;
78 __le32 ep_sel;
79 __le32 ep_traddr;
80 __le32 ep_cfg;
81 __le32 ep_cmd;
82 __le32 ep_sts;
83 __le32 ep_sts_sid;
84 __le32 ep_sts_en;
85 __le32 drbl;
86 __le32 ep_ien;
87 __le32 ep_ists;
88 __le32 usb_pwr;
89 __le32 usb_conf2;
90 __le32 usb_cap1;
91 __le32 usb_cap2;
92 __le32 usb_cap3;
93 __le32 usb_cap4;
94 __le32 usb_cap5;
95 __le32 usb_cap6;
96 __le32 usb_cpkt1;
97 __le32 usb_cpkt2;
98 __le32 usb_cpkt3;
99 __le32 ep_dma_ext_addr;
100 __le32 buf_addr;
101 __le32 buf_data;
102 __le32 buf_ctrl;
103 __le32 dtrans;
104 __le32 tdl_from_trb;
105 __le32 tdl_beh;
106 __le32 ep_tdl;
107 __le32 tdl_beh2;
108 __le32 dma_adv_td;
109 __le32 reserved1[26];
110 __le32 cfg_reg1;
111 __le32 dbg_link1;
112 __le32 dbg_link2;
113 __le32 cfg_regs[74];
114 __le32 reserved2[51];
115 __le32 dma_axi_ctrl;
116 __le32 dma_axi_id;
117 __le32 dma_axi_cap;
118 __le32 dma_axi_ctrl0;
119 __le32 dma_axi_ctrl1;
120};
121
122
123
124#define USB_CONF_CFGRST BIT(0)
125
126#define USB_CONF_CFGSET BIT(1)
127
128#define USB_CONF_USB3DIS BIT(3)
129
130#define USB_CONF_USB2DIS BIT(4)
131
132#define USB_CONF_LENDIAN BIT(5)
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136
137
138#define USB_CONF_BENDIAN BIT(6)
139
140#define USB_CONF_SWRST BIT(7)
141
142#define USB_CONF_DSING BIT(8)
143
144#define USB_CONF_DMULT BIT(9)
145
146#define USB_CONF_DMAOFFEN BIT(10)
147
148#define USB_CONF_DMAOFFDS BIT(11)
149
150#define USB_CONF_CFORCE_FS BIT(12)
151
152#define USB_CONF_SFORCE_FS BIT(13)
153
154#define USB_CONF_DEVEN BIT(14)
155
156#define USB_CONF_DEVDS BIT(15)
157
158#define USB_CONF_L1EN BIT(16)
159
160#define USB_CONF_L1DS BIT(17)
161
162#define USB_CONF_CLK2OFFEN BIT(18)
163
164#define USB_CONF_CLK2OFFDS BIT(19)
165
166#define USB_CONF_LGO_L0 BIT(20)
167
168#define USB_CONF_CLK3OFFEN BIT(21)
169
170#define USB_CONF_CLK3OFFDS BIT(22)
171
172
173#define USB_CONF_U1EN BIT(24)
174
175#define USB_CONF_U1DS BIT(25)
176
177#define USB_CONF_U2EN BIT(26)
178
179#define USB_CONF_U2DS BIT(27)
180
181#define USB_CONF_LGO_U0 BIT(28)
182
183#define USB_CONF_LGO_U1 BIT(29)
184
185#define USB_CONF_LGO_U2 BIT(30)
186
187#define USB_CONF_LGO_SSINACT BIT(31)
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194
195#define USB_STS_CFGSTS_MASK BIT(0)
196#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
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201
202#define USB_STS_OV_MASK BIT(1)
203#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
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208
209#define USB_STS_USB3CONS_MASK BIT(2)
210#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
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216
217#define USB_STS_DTRANS_MASK BIT(3)
218#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
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226
227#define USB_STS_USBSPEED_MASK GENMASK(6, 4)
228#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
229#define USB_STS_LS (0x1 << 4)
230#define USB_STS_FS (0x2 << 4)
231#define USB_STS_HS (0x3 << 4)
232#define USB_STS_SS (0x4 << 4)
233#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
234#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
235#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
236#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
237#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
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242
243#define USB_STS_ENDIAN_MASK BIT(7)
244#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
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250
251#define USB_STS_CLK2OFF_MASK BIT(8)
252#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
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258
259#define USB_STS_CLK3OFF_MASK BIT(9)
260#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
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265
266#define USB_STS_IN_RST_MASK BIT(10)
267#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
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273
274#define USB_STS_TDL_TRB_ENABLED BIT(11)
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280#define USB_STS_DEVS_MASK BIT(14)
281#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
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286
287#define USB_STS_ADDRESSED_MASK BIT(15)
288#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
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293
294#define USB_STS_L1ENS_MASK BIT(16)
295#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
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300
301#define USB_STS_VBUSS_MASK BIT(17)
302#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
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309
310#define USB_STS_LPMST_MASK GENMASK(19, 18)
311#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
312#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
313#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
314#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
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319
320#define USB_STS_USB2CONS_MASK BIT(20)
321#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
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326
327#define USB_STS_DISABLE_HS_MASK BIT(21)
328#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
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333
334#define USB_STS_U1ENS_MASK BIT(24)
335#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
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341#define USB_STS_U2ENS_MASK BIT(25)
342#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
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346
347#define USB_STS_LST_MASK GENMASK(29, 26)
348#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
349#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
350#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
351#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
352#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
353#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
354#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
355#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
356#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
357#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
358#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
359#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
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364
365#define USB_STS_DMAOFF_MASK BIT(30)
366#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
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371
372#define USB_STS_ENDIAN2_MASK BIT(31)
373#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
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375
376
377#define USB_CMD_SET_ADDR BIT(0)
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385#define USB_CMD_FADDR_MASK GENMASK(7, 1)
386#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
387
388#define USB_CMD_SDNFW BIT(8)
389
390#define USB_CMD_STMODE BIT(9)
391
392#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
393#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
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397
398#define USB_CMD_SDNLTM BIT(12)
399
400#define USB_CMD_SPKT BIT(13)
401
402#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
403#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
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407
408#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
409#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
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416
417#define USB_ITPN_MASK GENMASK(13, 0)
418#define USB_ITPN(p) ((p) & USB_ITPN_MASK)
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421
422#define USB_LPM_HIRD_MASK GENMASK(3, 0)
423#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
424
425#define USB_LPM_BRW BIT(4)
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428
429#define USB_IEN_CONIEN BIT(0)
430
431#define USB_IEN_DISIEN BIT(1)
432
433#define USB_IEN_UWRESIEN BIT(2)
434
435#define USB_IEN_UHRESIEN BIT(3)
436
437#define USB_IEN_U3ENTIEN BIT(4)
438
439#define USB_IEN_U3EXTIEN BIT(5)
440
441#define USB_IEN_U2ENTIEN BIT(6)
442
443#define USB_IEN_U2EXTIEN BIT(7)
444
445#define USB_IEN_U1ENTIEN BIT(8)
446
447#define USB_IEN_U1EXTIEN BIT(9)
448
449#define USB_IEN_ITPIEN BIT(10)
450
451#define USB_IEN_WAKEIEN BIT(11)
452
453#define USB_IEN_SPKTIEN BIT(12)
454
455#define USB_IEN_CON2IEN BIT(16)
456
457#define USB_IEN_DIS2IEN BIT(17)
458
459#define USB_IEN_U2RESIEN BIT(18)
460
461#define USB_IEN_L2ENTIEN BIT(20)
462
463#define USB_IEN_L2EXTIEN BIT(21)
464
465#define USB_IEN_L1ENTIEN BIT(24)
466
467#define USB_IEN_L1EXTIEN BIT(25)
468
469#define USB_IEN_CFGRESIEN BIT(26)
470
471#define USB_IEN_UWRESSIEN BIT(28)
472
473#define USB_IEN_UWRESEIEN BIT(29)
474
475#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
476 | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
477 | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
478 | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
479
480
481
482#define USB_ISTS_CONI BIT(0)
483
484#define USB_ISTS_DISI BIT(1)
485
486#define USB_ISTS_UWRESI BIT(2)
487
488#define USB_ISTS_UHRESI BIT(3)
489
490#define USB_ISTS_U3ENTI BIT(4)
491
492#define USB_ISTS_U3EXTI BIT(5)
493
494#define USB_ISTS_U2ENTI BIT(6)
495
496#define USB_ISTS_U2EXTI BIT(7)
497
498#define USB_ISTS_U1ENTI BIT(8)
499
500#define USB_ISTS_U1EXTI BIT(9)
501
502#define USB_ISTS_ITPI BIT(10)
503
504#define USB_ISTS_WAKEI BIT(11)
505
506#define USB_ISTS_SPKTI BIT(12)
507
508#define USB_ISTS_CON2I BIT(16)
509
510#define USB_ISTS_DIS2I BIT(17)
511
512#define USB_ISTS_U2RESI BIT(18)
513
514#define USB_ISTS_L2ENTI BIT(20)
515
516#define USB_ISTS_L2EXTI BIT(21)
517
518#define USB_ISTS_L1ENTI BIT(24)
519
520#define USB_ISTS_L1EXTI BIT(25)
521
522#define USB_ISTS_CFGRESI BIT(26)
523
524#define USB_ISTS_UWRESSI BIT(28)
525
526#define USB_ISTS_UWRESEI BIT(29)
527
528
529#define EP_SEL_EPNO_MASK GENMASK(3, 0)
530
531#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
532
533#define EP_SEL_DIR BIT(7)
534
535#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
536#define select_ep_out (EP_SEL_EPNO(p))
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540#define EP_TRADDR_TRADDR(p) ((p))
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543
544#define EP_CFG_ENABLE BIT(0)
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550
551#define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
552#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
553
554#define EP_CFG_STREAM_EN BIT(3)
555
556#define EP_CFG_TDL_CHK BIT(4)
557
558#define EP_CFG_SID_CHK BIT(5)
559
560#define EP_CFG_EPENDIAN BIT(7)
561
562#define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
563#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
564
565#define EP_CFG_MULT_MASK GENMASK(15, 14)
566#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
567
568#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
569#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
570
571#define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
572#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
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574
575
576#define EP_CMD_EPRST BIT(0)
577
578#define EP_CMD_SSTALL BIT(1)
579
580#define EP_CMD_CSTALL BIT(2)
581
582#define EP_CMD_ERDY BIT(3)
583
584#define EP_CMD_REQ_CMPL BIT(5)
585
586#define EP_CMD_DRDY BIT(6)
587
588#define EP_CMD_DFLUSH BIT(7)
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592
593
594#define EP_CMD_STDL BIT(8)
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598
599#define EP_CMD_TDL_MASK GENMASK(15, 9)
600#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
601#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
602#define EP_CMD_TDL_MAX (EP_CMD_TDL_MASK >> 9)
603
604
605#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
606#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
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608
609
610#define EP_STS_SETUP BIT(0)
611
612#define EP_STS_STALL(p) ((p) & BIT(1))
613
614#define EP_STS_IOC BIT(2)
615
616#define EP_STS_ISP BIT(3)
617
618#define EP_STS_DESCMIS BIT(4)
619
620#define EP_STS_STREAMR BIT(5)
621
622#define EP_STS_MD_EXIT BIT(6)
623
624#define EP_STS_TRBERR BIT(7)
625
626#define EP_STS_NRDY BIT(8)
627
628#define EP_STS_DBUSY BIT(9)
629
630#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
631
632#define EP_STS_CCS(p) ((p) & BIT(11))
633
634#define EP_STS_PRIME BIT(12)
635
636#define EP_STS_SIDERR BIT(13)
637
638#define EP_STS_OUTSMM BIT(14)
639
640#define EP_STS_ISOERR BIT(15)
641
642#define EP_STS_HOSTPP(p) ((p) & BIT(16))
643
644#define EP_STS_SPSMST_MASK GENMASK(18, 17)
645#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
646#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
647#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
648#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
649
650#define EP_STS_IOT BIT(19)
651
652#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
653#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
654
655#define EP_STS_OUTQ_VAL_MASK BIT(28)
656#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
657
658#define EP_STS_STPWAIT BIT(31)
659
660
661
662#define EP_STS_SID_MASK GENMASK(15, 0)
663#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
664
665
666
667#define EP_STS_EN_SETUPEN BIT(0)
668
669#define EP_STS_EN_DESCMISEN BIT(4)
670
671#define EP_STS_EN_STREAMREN BIT(5)
672
673#define EP_STS_EN_MD_EXITEN BIT(6)
674
675#define EP_STS_EN_TRBERREN BIT(7)
676
677#define EP_STS_EN_NRDYEN BIT(8)
678
679#define EP_STS_EN_PRIMEEEN BIT(12)
680
681#define EP_STS_EN_SIDERREN BIT(13)
682
683#define EP_STS_EN_OUTSMMEN BIT(14)
684
685#define EP_STS_EN_ISOERREN BIT(15)
686
687#define EP_STS_EN_IOTEN BIT(19)
688
689#define EP_STS_EN_STPWAITEN BIT(31)
690
691
692#define DB_VALUE_BY_INDEX(index) (1 << (index))
693#define DB_VALUE_EP0_OUT BIT(0)
694#define DB_VALUE_EP0_IN BIT(16)
695
696
697#define EP_IEN(index) (1 << (index))
698#define EP_IEN_EP_OUT0 BIT(0)
699#define EP_IEN_EP_IN0 BIT(16)
700
701
702#define EP_ISTS(index) (1 << (index))
703#define EP_ISTS_EP_OUT0 BIT(0)
704#define EP_ISTS_EP_IN0 BIT(16)
705
706
707
708#define PUSB_PWR_PSO_EN BIT(0)
709
710#define PUSB_PWR_PSO_DS BIT(1)
711
712
713
714
715
716#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
717
718
719
720
721#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
722
723#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
724
725#define PUSB_PWR_FST_REG_ACCESS BIT(31)
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731
732
733#define USB_CONF2_DIS_TDL_TRB BIT(1)
734
735
736
737
738
739#define USB_CONF2_EN_TDL_TRB BIT(2)
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750
751#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
752#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
753#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
754#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
755#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
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764
765#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
766#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
767#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
768#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
769#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
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778
779#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
780#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
781#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
782#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
783#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
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792
793#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
794#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
795#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
796
797
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799
800
801
802
803#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
804#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
805#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
806
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815
816
817#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
818#define DEV_U3PHY_WIDTH_8(p) \
819 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
820#define DEV_U3PHY_WIDTH_16(p) \
821 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
822#define DEV_U3PHY_WIDTH_32(p) \
823 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
824#define DEV_U3PHY_WIDTH_64(p) \
825 (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
826
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830
831
832
833#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
834
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838
839
840#define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
841
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844
845
846
847
848#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
849
850
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852
853
854#define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
855
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859
860
861#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
862
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867
868
869#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
870
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882
883
884#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
885
886
887#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
888
889
890#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
891
892
893#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
894
895
896
897#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
898
899#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
900
901#define DEV_VER_NXP_V1 0x00024502
902#define DEV_VER_TI_V1 0x00024509
903#define DEV_VER_V2 0x0002450C
904#define DEV_VER_V3 0x0002450d
905
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909
910
911#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
912
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915
916#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
917#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
918
919
920
921
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924
925
926#define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
927
928#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
929
930
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932
933
934#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
935
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937
938
939
940#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
941
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944
945
946#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
947
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950
951
952#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
953
954
955
956#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
957
958#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
959#define DMA_AXI_CTRL_NON_SECURE 0x02
960
961#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
962
963#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
964
965
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967
968
969#define TRBS_PER_SEGMENT 40
970
971#define ISO_MAX_INTERVAL 10
972
973#define MAX_TRB_LENGTH BIT(16)
974
975#if TRBS_PER_SEGMENT < 2
976#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
977#endif
978
979#define TRBS_PER_STREAM_SEGMENT 2
980
981#if TRBS_PER_STREAM_SEGMENT < 2
982#error "Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2."
983#endif
984
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990
991
992#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
993
994#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
995 TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
996
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1003
1004struct cdns3_trb {
1005 __le32 buffer;
1006 __le32 length;
1007 __le32 control;
1008};
1009
1010#define TRB_SIZE (sizeof(struct cdns3_trb))
1011#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
1012#define TRB_STREAM_RING_SIZE (TRB_SIZE * TRBS_PER_STREAM_SEGMENT)
1013#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
1014#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
1015
1016
1017#define TRB_TYPE_BITMASK GENMASK(15, 10)
1018#define TRB_TYPE(p) ((p) << 10)
1019#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1020
1021
1022
1023#define TRB_NORMAL 1
1024
1025#define TRB_LINK 6
1026
1027
1028#define TRB_CYCLE BIT(0)
1029
1030
1031
1032#define TRB_TOGGLE BIT(1)
1033
1034
1035
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1038
1039
1040
1041
1042#define TRB_SP BIT(1)
1043
1044
1045#define TRB_ISP BIT(2)
1046
1047#define TRB_FIFO_MODE BIT(3)
1048
1049#define TRB_CHAIN BIT(4)
1050
1051#define TRB_IOC BIT(5)
1052
1053
1054#define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
1055#define TRB_STREAM_ID(p) ((p) << 16)
1056#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
1057
1058
1059#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
1060#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
1061
1062
1063#define TRB_LEN(p) ((p) & GENMASK(16, 0))
1064
1065
1066#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
1067#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
1068
1069
1070#define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24))
1071#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
1072
1073
1074#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
1075
1076
1077
1078
1079
1080#define USB_DEVICE_MAX_ADDRESS 127
1081
1082
1083#define CDNS3_EP_MAX_PACKET_LIMIT 1024
1084#define CDNS3_EP_MAX_STREAMS 15
1085#define CDNS3_EP0_MAX_PACKET_LIMIT 512
1086
1087
1088#define CDNS3_ENDPOINTS_MAX_COUNT 32
1089#define CDNS3_EP_ZLP_BUF_SIZE 1024
1090
1091#define CDNS3_EP_BUF_SIZE 4
1092#define CDNS3_EP_ISO_HS_MULT 3
1093#define CDNS3_EP_ISO_SS_BURST 3
1094#define CDNS3_MAX_NUM_DESCMISS_BUF 32
1095#define CDNS3_DESCMIS_BUF_SIZE 2048
1096#define CDNS3_WA2_NUM_BUFFERS 128
1097
1098
1099
1100struct cdns3_device;
1101
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1128
1129struct cdns3_endpoint {
1130 struct usb_ep endpoint;
1131 struct list_head pending_req_list;
1132 struct list_head deferred_req_list;
1133 struct list_head wa2_descmiss_req_list;
1134 int wa2_counter;
1135
1136 struct cdns3_trb *trb_pool;
1137 dma_addr_t trb_pool_dma;
1138
1139 struct cdns3_device *cdns3_dev;
1140 char name[20];
1141
1142#define EP_ENABLED BIT(0)
1143#define EP_STALLED BIT(1)
1144#define EP_STALL_PENDING BIT(2)
1145#define EP_WEDGE BIT(3)
1146#define EP_TRANSFER_STARTED BIT(4)
1147#define EP_UPDATE_EP_TRBADDR BIT(5)
1148#define EP_PENDING_REQUEST BIT(6)
1149#define EP_RING_FULL BIT(7)
1150#define EP_CLAIMED BIT(8)
1151#define EP_DEFERRED_DRDY BIT(9)
1152#define EP_QUIRK_ISO_OUT_EN BIT(10)
1153#define EP_QUIRK_END_TRANSFER BIT(11)
1154#define EP_QUIRK_EXTRA_BUF_DET BIT(12)
1155#define EP_QUIRK_EXTRA_BUF_EN BIT(13)
1156#define EP_TDLCHK_EN BIT(15)
1157 u32 flags;
1158
1159 struct cdns3_request *descmis_req;
1160
1161 u8 dir;
1162 u8 num;
1163 u8 type;
1164 int interval;
1165
1166 int free_trbs;
1167 int num_trbs;
1168 int alloc_ring_size;
1169 u8 pcs;
1170 u8 ccs;
1171 int enqueue;
1172 int dequeue;
1173 u8 trb_burst_size;
1174
1175 unsigned int wa1_set:1;
1176 struct cdns3_trb *wa1_trb;
1177 unsigned int wa1_trb_index;
1178 unsigned int wa1_cycle_bit:1;
1179
1180
1181 unsigned int use_streams:1;
1182 unsigned int prime_flag:1;
1183 u32 ep_sts_pending;
1184 u16 last_stream_id;
1185 u16 pending_tdl;
1186 unsigned int stream_sg_idx;
1187};
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198struct cdns3_aligned_buf {
1199 void *buf;
1200 dma_addr_t dma;
1201 u32 size;
1202 unsigned in_use:1;
1203 struct list_head list;
1204};
1205
1206
1207
1208
1209
1210
1211
1212
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1216
1217
1218
1219struct cdns3_request {
1220 struct usb_request request;
1221 struct cdns3_endpoint *priv_ep;
1222 struct cdns3_trb *trb;
1223 int start_trb;
1224 int end_trb;
1225 struct cdns3_aligned_buf *aligned_buf;
1226#define REQUEST_PENDING BIT(0)
1227#define REQUEST_INTERNAL BIT(1)
1228#define REQUEST_INTERNAL_CH BIT(2)
1229#define REQUEST_ZLP BIT(3)
1230#define REQUEST_UNALIGNED BIT(4)
1231 u32 flags;
1232 struct list_head list;
1233};
1234
1235#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
1236
1237
1238#define CDNS3_SETUP_STAGE 0x0
1239#define CDNS3_DATA_STAGE 0x1
1240#define CDNS3_STATUS_STAGE 0x2
1241
1242
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1244
1245
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1273
1274
1275struct cdns3_device {
1276 struct device *dev;
1277 struct device *sysdev;
1278
1279 struct usb_gadget gadget;
1280 struct usb_gadget_driver *gadget_driver;
1281
1282#define CDNS_REVISION_V0 0x00024501
1283#define CDNS_REVISION_V1 0x00024509
1284 u32 dev_ver;
1285
1286
1287 spinlock_t lock;
1288
1289 struct cdns3_usb_regs __iomem *regs;
1290
1291 struct usb_ctrlrequest *setup_buf;
1292 dma_addr_t setup_dma;
1293 void *zlp_buf;
1294
1295 u8 ep0_stage;
1296 int ep0_data_dir;
1297
1298 struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
1299
1300 struct list_head aligned_buf_list;
1301 struct work_struct aligned_buf_wq;
1302
1303 u32 selected_ep;
1304 u16 isoch_delay;
1305
1306 unsigned wait_for_setup:1;
1307 unsigned u1_allowed:1;
1308 unsigned u2_allowed:1;
1309 unsigned is_selfpowered:1;
1310 unsigned setup_pending:1;
1311 unsigned hw_configured_flag:1;
1312 unsigned wake_up_flag:1;
1313 unsigned status_completion_no_call:1;
1314 unsigned using_streams:1;
1315 int out_mem_is_allocated;
1316
1317 struct work_struct pending_status_wq;
1318 struct usb_request *pending_status_request;
1319
1320
1321 u16 onchip_buffers;
1322 u16 onchip_used_size;
1323};
1324
1325void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
1326dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
1327 struct cdns3_trb *trb);
1328enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
1329void cdns3_pending_setup_status_handler(struct work_struct *work);
1330void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
1331void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
1332void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
1333void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
1334struct usb_request *cdns3_next_request(struct list_head *list);
1335void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
1336int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
1337u8 cdns3_ep_addr_to_index(u8 ep_addr);
1338int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
1339int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
1340void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
1341int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
1342struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
1343 gfp_t gfp_flags);
1344void cdns3_gadget_ep_free_request(struct usb_ep *ep,
1345 struct usb_request *request);
1346int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
1347void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
1348 struct cdns3_request *priv_req,
1349 int status);
1350
1351int cdns3_init_ep0(struct cdns3_device *priv_dev,
1352 struct cdns3_endpoint *priv_ep);
1353void cdns3_ep0_config(struct cdns3_device *priv_dev);
1354void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
1355void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
1356int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
1357
1358#endif
1359